From b63a9506296b10b9730c3ff4a0e9611f6f98e7db Mon Sep 17 00:00:00 2001 From: York Sun Date: Wed, 3 Aug 2016 12:33:00 -0700 Subject: armv8: ls2080a: Remove debug server support Debug server feature has been dropped from roadmap. Signed-off-by: York Sun --- include/configs/ls2080a_common.h | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) (limited to 'include/configs') diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index ebe1415..903f6dd 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -153,11 +153,6 @@ unsigned long long get_qixis_addr(void); #define CONFIG_SYS_NAND_BASE 0x530000000ULL #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 -/* Debug Server firmware */ -#define CONFIG_FSL_DEBUG_SERVER -/* 2 sec timeout */ -#define CONFIG_SYS_DEBUG_SERVER_TIMEOUT (2 * 1000 * 1000) - /* MC firmware */ #define CONFIG_FSL_MC_ENET /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ @@ -175,8 +170,7 @@ unsigned long long get_qixis_addr(void); * It will be used by MC and Debug Server. The MC region must be * 512MB aligned, so the min size to hide is 512MB. */ -#if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER) -#define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE (254UL * 1024 * 1024) +#ifdef CONFIG_FSL_MC_ENET #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) #define CONFIG_SYS_MC_RSV_MEM_ALIGN (512UL * 1024 * 1024) #endif -- cgit v1.1 From 349cfc973f8470a7839d762c25b62b4c4f4e8683 Mon Sep 17 00:00:00 2001 From: Hongbo Zhang Date: Fri, 19 Aug 2016 17:20:31 +0800 Subject: nxp: ls102xa: add registers definition for system sleep This patch adds definitions of all the regesters necessary for system sleep. Signed-off-by: Hongbo Zhang Reviewed-by: York Sun --- include/configs/ls1021aqds.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'include/configs') diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 105702d..7a256da 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -287,6 +287,13 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_CTL_SYS 0x5 +#define QIXIS_CTL_SYS_EVTSW_MASK 0x0c +#define QIXIS_CTL_SYS_EVTSW_IRQ 0x04 +#define QIXIS_RST_FORCE_3 0x45 +#define QIXIS_RST_FORCE_3_PCIESLOT1 0x80 +#define QIXIS_PWR_CTL2 0x21 +#define QIXIS_PWR_CTL2_PCTL 0x2 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ -- cgit v1.1 From 214ffae02d03cd548549c6390eb9c19b9e6b085f Mon Sep 17 00:00:00 2001 From: Hongbo Zhang Date: Fri, 19 Aug 2016 17:20:33 +0800 Subject: nxp: ls102xa: add LS1 PSCI system suspend The deep sleep function of LS1 platform, is mapped into PSCI system suspend function, this patch adds implementation of it. Signed-off-by: Hongbo Zhang Reviewed-by: York Sun --- include/configs/ls1021aqds.h | 1 + include/configs/ls1021atwr.h | 1 + 2 files changed, 2 insertions(+) (limited to 'include/configs') diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 7a256da..5aaecc7 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -10,6 +10,7 @@ #define CONFIG_LS102XA #define CONFIG_ARMV7_PSCI_1_0 +#define CONFIG_LS1_DEEP_SLEEP #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 90ae770..ef238a4 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -10,6 +10,7 @@ #define CONFIG_LS102XA #define CONFIG_ARMV7_PSCI_1_0 +#define CONFIG_LS1_DEEP_SLEEP #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR -- cgit v1.1 From b9e745bbe2562fda710d668dc9cef46e0b23049f Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Fri, 26 Aug 2016 18:30:39 +0800 Subject: driver/ddr/fsl: Add general MMDC driver and reuse common MMDC driver for ls1012a This general MMDC driver adds basic support for Freescale MMDC (Multi Mode DDR Controller). Currently MMDC is integrated on ARMv8 LS1012A SoC for DDR3L, there will be a update to this driver to support more flexible configuration if new features (DDR4, multiple controllers/chip selections, etc) are implimented in future. Meantime, reuse common MMDC driver for LS1012ARDB/LS1012AQDS/ LS1012AFRDM. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun --- include/configs/ls1012afrdm.h | 22 ++++++++++++++++++---- include/configs/ls1012aqds.h | 23 ++++++++++++++++++++--- include/configs/ls1012ardb.h | 21 ++++++++++++++++----- 3 files changed, 54 insertions(+), 12 deletions(-) (limited to 'include/configs') diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h index 19ad194..136d648 100644 --- a/include/configs/ls1012afrdm.h +++ b/include/configs/ls1012afrdm.h @@ -9,19 +9,33 @@ #include "ls1012a_common.h" +/* DDR */ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 #define CONFIG_NR_DRAM_BANKS 2 #define CONFIG_SYS_SDRAM_SIZE 0x20000000 - -#define CONFIG_SYS_MMDC_CORE_CONTROL_1 0x04180000 -#define CONFIG_SYS_MMDC_CORE_CONTROL_2 0x84180000 - +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 #define CONFIG_CMD_MEMINFO #define CONFIG_CMD_MEMTEST #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END 0x9fffffff +/* DDR board-specific timing parameters */ +#define CONFIG_MMDC_MDCTL 0x04180000 +#define CONFIG_MMDC_MDPDC 0x00030035 +#define CONFIG_MMDC_MDOTC 0x12554000 +#define CONFIG_MMDC_MDCFG0 0xbabf7954 +#define CONFIG_MMDC_MDCFG1 0xdb328f64 +#define CONFIG_MMDC_MDCFG2 0x01ff00db +#define CONFIG_MMDC_MDMISC 0x00001680 +#define CONFIG_MMDC_MDREF 0x0f3c8000 +#define CONFIG_MMDC_MDRWD 0x00002000 +#define CONFIG_MMDC_MDOR 0x00bf1023 +#define CONFIG_MMDC_MDASP 0x0000003f +#define CONFIG_MMDC_MPODTCTRL 0x0000022a +#define CONFIG_MMDC_MPZQHWCTRL 0xa1390003 + + /* * USB */ diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index 75b60fa..b6d12dd 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -9,14 +9,31 @@ #include "ls1012a_common.h" - +/* DDR */ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 #define CONFIG_NR_DRAM_BANKS 2 #define CONFIG_SYS_SDRAM_SIZE 0x40000000 +#define CONFIG_CMD_MEMINFO +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END 0x9fffffff + +/* DDR board-specific timing parameters */ +#define CONFIG_MMDC_MDCTL 0x05180000 +#define CONFIG_MMDC_MDPDC 0x00030035 +#define CONFIG_MMDC_MDOTC 0x12554000 +#define CONFIG_MMDC_MDCFG0 0xbabf7954 +#define CONFIG_MMDC_MDCFG1 0xdb328f64 +#define CONFIG_MMDC_MDCFG2 0x01ff00db +#define CONFIG_MMDC_MDMISC 0x00001680 +#define CONFIG_MMDC_MDREF 0x0f3c8000 +#define CONFIG_MMDC_MDRWD 0x00002000 +#define CONFIG_MMDC_MDOR 0x00bf1023 +#define CONFIG_MMDC_MDASP 0x0000003f +#define CONFIG_MMDC_MPODTCTRL 0x0000022a +#define CONFIG_MMDC_MPZQHWCTRL 0xa1390003 -#define CONFIG_SYS_MMDC_CORE_CONTROL_1 0x05180000 -#define CONFIG_SYS_MMDC_CORE_CONTROL_2 0x85180000 /* * QIXIS Definitions diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index d3117e7..2076ce5 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -9,20 +9,31 @@ #include "ls1012a_common.h" - +/* DDR */ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 #define CONFIG_NR_DRAM_BANKS 2 #define CONFIG_SYS_SDRAM_SIZE 0x40000000 - -#define CONFIG_SYS_MMDC_CORE_CONTROL_1 0x05180000 -#define CONFIG_SYS_MMDC_CORE_CONTROL_2 0x85180000 - #define CONFIG_CMD_MEMINFO #define CONFIG_CMD_MEMTEST #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END 0x9fffffff +/* DDR board-specific timing parameters */ +#define CONFIG_MMDC_MDCTL 0x05180000 +#define CONFIG_MMDC_MDPDC 0x00030035 +#define CONFIG_MMDC_MDOTC 0x12554000 +#define CONFIG_MMDC_MDCFG0 0xbabf7954 +#define CONFIG_MMDC_MDCFG1 0xdb328f64 +#define CONFIG_MMDC_MDCFG2 0x01ff00db +#define CONFIG_MMDC_MDMISC 0x00001680 +#define CONFIG_MMDC_MDREF 0x0f3c8000 +#define CONFIG_MMDC_MDRWD 0x00002000 +#define CONFIG_MMDC_MDOR 0x00bf1023 +#define CONFIG_MMDC_MDASP 0x0000003f +#define CONFIG_MMDC_MPODTCTRL 0x0000022a +#define CONFIG_MMDC_MPZQHWCTRL 0xa1390003 + /* * USB */ -- cgit v1.1 From dd02936f81de477680f27af244fd2085ce460152 Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Wed, 7 Sep 2016 18:47:28 +0800 Subject: armv8: ls1046ardb: Add LS1046ARDB board support LS1046ARDB Specification: ------------------------- Memory subsystem: * 8GByte DDR4 SDRAM (64bit bus) * 512 Mbyte NAND flash * Two 64 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card * On-board 4G eMMC Ethernet: * Two XFI 10G ports * Two SGMII ports * Two RGMII ports PCIe: * PCIe1 (SerDes2 Lane0) to miniPCIe slot * PCIe2 (SerDes2 Lane1) to x2 PCIe slot * PCIe3 (SerDes2 Lane2) to x4 PCIe slot SATA: * SerDes2 Lane3 to SATA port USB 3.0: one super speed USB 3.0 type A port one Micro-AB port UART: supports two UARTs up to 115200 bps for console Signed-off-by: Mingkai Hu Signed-off-by: Shaohui Xie Signed-off-by: Gong Qianyu Reviewed-by: York Sun --- include/configs/ls1046a_common.h | 175 ++++++++++++++++++++++++++++ include/configs/ls1046ardb.h | 240 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 415 insertions(+) create mode 100644 include/configs/ls1046a_common.h create mode 100644 include/configs/ls1046ardb.h (limited to 'include/configs') diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h new file mode 100644 index 0000000..9ee29b4 --- /dev/null +++ b/include/configs/ls1046a_common.h @@ -0,0 +1,175 @@ +/* + * Copyright 2016 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LS1046A_COMMON_H +#define __LS1046A_COMMON_H + +#define CONFIG_REMAKE_ELF +#define CONFIG_FSL_LAYERSCAPE +#define CONFIG_FSL_LSCH2 +#define CONFIG_LS1046A +#define CONFIG_MP +#define CONFIG_SYS_FSL_CLK +#define CONFIG_GICV2 + +#include +#ifdef CONFIG_SYS_FSL_SRDS_1 +#define CONFIG_SYS_HAS_SERDES +#endif + +/* Link Definitions */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) + +#define CONFIG_SUPPORT_RAW_INITRD + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F 1 + +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL + +#define CPU_RELEASE_ADDR secondary_boot_func + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 25000000 /* 25MHz */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* SD boot SPL */ +#ifdef CONFIG_SD_BOOT +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT + +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x110 +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x500 +#define CONFIG_SPL_TEXT_BASE 0x10000000 +#define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */ +#define CONFIG_SPL_STACK 0x10020000 +#define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */ +#define CONFIG_SPL_BSS_START_ADDR 0x8f000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#define CONFIG_SYS_MONITOR_LEN 0xa0000 +#endif + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 +#define CONFIG_SYS_I2C_MXC_I2C2 +#define CONFIG_SYS_I2C_MXC_I2C3 +#define CONFIG_SYS_I2C_MXC_I2C4 + +/* Command line configuration */ +#define CONFIG_CMD_ENV + +/* MMC */ +#define CONFIG_MMC +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 +#define CONFIG_GENERIC_MMC +#define CONFIG_DOS_PARTITION +#endif + +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ + +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ + +/* FMan ucode */ +#define CONFIG_SYS_DPAA_FMAN +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_FM_MURAM_SIZE 0x60000 + +#ifdef CONFIG_SD_BOOT +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 1MB (2048 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_MMC +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) +#else +#define CONFIG_SYS_QE_FW_IN_SPIFLASH +#define CONFIG_SYS_FMAN_FW_ADDR 0x40300000 +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 1000000 +#define CONFIG_ENV_SPI_MODE 0x03 +#endif +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) +#endif + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) +#define CONFIG_ARCH_EARLY_INIT_R +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_HWCONFIG +#define HWCONFIG_BUFFER_SIZE 128 + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "loadaddr=0x80100000\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0x1000000\0" \ + "kernel_load=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "console=ttyS0,115200\0" \ + MTDPARTS_DEFAULT "\0" + +#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ + "earlycon=uart8250,mmio,0x21c0500 " \ + MTDPARTS_DEFAULT +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_MAXARGS 64 /* max command args */ + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + +#endif /* __LS1046A_COMMON_H */ diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h new file mode 100644 index 0000000..693cc8d --- /dev/null +++ b/include/configs/ls1046ardb.h @@ -0,0 +1,240 @@ +/* + * Copyright 2016 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LS1046ARDB_H__ +#define __LS1046ARDB_H__ + +#include "ls1046a_common.h" + +#if defined(CONFIG_FSL_LS_PPA) +#define CONFIG_ARMV8_PSCI +#define CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#define CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE (1UL * 1024 * 1024) + +#define CONFIG_SYS_LS_PPA_FW_IN_XIP +#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP +#define CONFIG_SYS_LS_PPA_FW_ADDR 0x40500000 +#endif +#endif + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SYS_TEXT_BASE 0x82000000 +#else +#define CONFIG_SYS_TEXT_BASE 0x40100000 +#endif + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 + +#define CONFIG_LAYERSCAPE_NS_ACCESS +#define CONFIG_MISC_INIT_R + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +/* Physical Memory Map */ +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#define CONFIG_NR_DRAM_BANKS 2 + +#define CONFIG_DDR_SPD +#define SPD_EEPROM_ADDRESS 0x51 +#define CONFIG_SYS_SPD_BUS_NUM 0 + +#define CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ +#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg +#endif + +#ifdef CONFIG_SD_BOOT +#ifdef CONFIG_EMMC_BOOT +#define CONFIG_SYS_FSL_PBL_RCW \ + board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg +#else +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg +#endif +#endif + +/* No NOR flash */ +#define CONFIG_SYS_NO_FLASH + +/* IFC */ +#define CONFIG_FSL_IFC + +/* + * NAND Flash Definitions + */ +#define CONFIG_NAND_FSL_IFC + +#define CONFIG_SYS_NAND_BASE 0x7e800000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE + +#define CONFIG_SYS_NAND_CSPR_EXT (0x0) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_NAND \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ + | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ + | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ + | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x7) | \ + FTIM0_NAND_TWH(0xa)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0xe) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ + FTIM2_NAND_TREH(0xa) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND + +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +/* + * CPLD + */ +#define CONFIG_SYS_CPLD_BASE 0x7fb00000 +#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE + +#define CONFIG_SYS_CPLD_CSPR_EXT (0x0) +#define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ + CSPR_PORT_SIZE_8 | \ + CSPR_MSEL_GPCM | \ + CSPR_V) +#define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) +#define CONFIG_SYS_CPLD_CSOR CSOR_NOR_ADM_SHIFT(16) + +/* CPLD Timing parameters for IFC GPCM */ +#define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ + FTIM1_GPCM_TRAD(0x3f)) +#define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ + FTIM2_GPCM_TCH(0xf) | \ + FTIM2_GPCM_TWP(0x3E)) +#define CONFIG_SYS_CPLD_FTIM3 0x0 + +/* IFC Timing Params */ +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 + +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 +#define I2C_RETIMER_ADDR 0x18 + +/* + * Environment + */ +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_SD_BOOT) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_OFFSET (1024 * 1024) +#define CONFIG_ENV_SIZE 0x2000 +#else +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x200000 /* 2MB */ +#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */ +#endif + +/* FMan */ +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET +#define CONFIG_PHYLIB +#define CONFIG_PHYLIB_10G +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ + +#define CONFIG_PHY_REALTEK +#define CONFIG_PHY_AQUANTIA +#define AQR105_IRQ_MASK 0x80000000 + +#define RGMII_PHY1_ADDR 0x1 +#define RGMII_PHY2_ADDR 0x2 + +#define SGMII_PHY1_ADDR 0x3 +#define SGMII_PHY2_ADDR 0x4 + +#define FM1_10GEC1_PHY_ADDR 0x0 + +#define CONFIG_ETHPRIME "FM1@DTSEC3" +#endif + +/* QSPI device */ +#ifdef CONFIG_FSL_QSPI +#define CONFIG_SPI_FLASH_SPANSION +#define FSL_QSPI_FLASH_SIZE (1 << 26) +#define FSL_QSPI_FLASH_NUM 2 +#define CONFIG_SPI_FLASH_BAR +#endif + +/* SATA */ +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SCSI +#define CONFIG_DOS_PARTITION +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_SYS_SATA AHCI_BASE_ADDR + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) +#define CONFIG_BOOTCOMMAND "sf probe 0:0;sf read $kernel_load" \ + "$kernel_start $kernel_size;" \ + "bootm $kernel_load" + +#define MTDPARTS_DEFAULT "mtdparts=1550000.quadspi:1m(rcw)," \ + "15m(u-boot),48m(kernel.itb);" \ + "7e800000.flash:16m(nand_uboot)," \ + "48m(nand_kernel),448m(nand_free)" + +#endif /* __LS1046ARDB_H__ */ -- cgit v1.1 From 126fe70d7746d7e60a6331391cab6713368b78dc Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Wed, 7 Sep 2016 17:56:14 +0800 Subject: armv8: ls1046aqds: Add LS1046AQDS board support LS1046AQDS Specification: ------------------------- Memory subsystem: * 8GByte DDR4 SDRAM (64bit bus) * 128 Mbyte NOR flash single-chip memory * 512 Mbyte NAND flash * 64 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card Ethernet: * Two XFI 10G ports * Two SGMII ports * Two RGMII ports PCIe: supports Gen 1 and Gen 2 SATA 3.0: one SATA 3.0 port USB 3.0: two micro AB connector and one type A connector UART: supports two UARTs up to 115200 bps for console Signed-off-by: Shaohui Xie Signed-off-by: Mingkai Hu Signed-off-by: Gong Qianyu Reviewed-by: York Sun --- include/configs/ls1046a_common.h | 38 ++- include/configs/ls1046aqds.h | 487 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 524 insertions(+), 1 deletion(-) create mode 100644 include/configs/ls1046aqds.h (limited to 'include/configs') diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 9ee29b4..5856de8 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -80,6 +80,36 @@ #define CONFIG_SYS_MONITOR_LEN 0xa0000 #endif +/* NAND SPL */ +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SPL_PBL_PAD +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT + +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_TEXT_BASE 0x10000000 +#define CONFIG_SPL_MAX_SIZE 0x1d000 /* 116 KiB */ +#define CONFIG_SPL_STACK 0x1001f000 +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + +#define CONFIG_SPL_BSS_START_ADDR 0x8f000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#define CONFIG_SYS_MONITOR_LEN 0xa0000 +#endif + /* I2C */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC @@ -117,13 +147,19 @@ */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) -#else +#elif defined(CONFIG_QSPI_BOOT) #define CONFIG_SYS_QE_FW_IN_SPIFLASH #define CONFIG_SYS_FMAN_FW_ADDR 0x40300000 #define CONFIG_ENV_SPI_BUS 0 #define CONFIG_ENV_SPI_CS 0 #define CONFIG_ENV_SPI_MAX_HZ 1000000 #define CONFIG_ENV_SPI_MODE 0x03 +#elif defined(CONFIG_NAND_BOOT) +#define CONFIG_SYS_QE_FMAN_FW_IN_NAND +#define CONFIG_SYS_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#else +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_FMAN_FW_ADDR 0x60300000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h new file mode 100644 index 0000000..2e5c2f1 --- /dev/null +++ b/include/configs/ls1046aqds.h @@ -0,0 +1,487 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LS1046AQDS_H__ +#define __LS1046AQDS_H__ + +#include "ls1046a_common.h" + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) +#define CONFIG_SYS_TEXT_BASE 0x82000000 +#elif defined(CONFIG_QSPI_BOOT) +#define CONFIG_SYS_TEXT_BASE 0x40010000 +#else +#define CONFIG_SYS_TEXT_BASE 0x60100000 +#endif + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif + +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_LAYERSCAPE_NS_ACCESS + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +/* Physical Memory Map */ +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#define CONFIG_NR_DRAM_BANKS 2 + +#define CONFIG_DDR_SPD +#define SPD_EEPROM_ADDRESS 0x51 +#define CONFIG_SYS_SPD_BUS_NUM 0 + +#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ + +#define CONFIG_DDR_ECC +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#define CONFIG_SYS_HAS_SERDES + +/* DSPI */ +#ifdef CONFIG_FSL_DSPI +#define CONFIG_SPI_FLASH_STMICRO /* cs0 */ +#define CONFIG_SPI_FLASH_SST /* cs1 */ +#define CONFIG_SPI_FLASH_EON /* cs2 */ +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_SF_DEFAULT_BUS 1 +#define CONFIG_SF_DEFAULT_CS 0 +#endif +#endif + +/* QSPI */ +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#ifdef CONFIG_FSL_QSPI +#define CONFIG_SPI_FLASH_SPANSION +#define FSL_QSPI_FLASH_SIZE (1 << 24) +#define FSL_QSPI_FLASH_NUM 2 +#endif +#endif + +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET +#define CONFIG_PHYLIB +#define CONFIG_PHY_VITESSE +#define CONFIG_PHY_REALTEK +#define CONFIG_PHYLIB_10G +#define RGMII_PHY1_ADDR 0x1 +#define RGMII_PHY2_ADDR 0x2 +#define SGMII_CARD_PORT1_PHY_ADDR 0x1C +#define SGMII_CARD_PORT2_PHY_ADDR 0x1D +#define SGMII_CARD_PORT3_PHY_ADDR 0x1E +#define SGMII_CARD_PORT4_PHY_ADDR 0x1F +/* PHY address on QSGMII riser card on slot 2 */ +#define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8 +#define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9 +#define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA +#define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB +#endif + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI \ + board/freescale/ls1046aqds/ls1046aqds_pbi.cfg +#endif + +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SYS_FSL_PBL_RCW \ + board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg +#endif + +#ifdef CONFIG_SD_BOOT +#ifdef CONFIG_SD_BOOT_QSPI +#define CONFIG_SYS_FSL_PBL_RCW \ + board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg +#else +#define CONFIG_SYS_FSL_PBL_RCW \ + board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg +#endif +#endif + +/* IFC */ +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_FSL_IFC +/* + * CONFIG_SYS_FLASH_BASE has the final address (core view) + * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) + * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address + * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting + */ +#define CONFIG_SYS_FLASH_BASE 0x60000000 +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 + +#ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ +#endif +#endif + +/* SATA */ +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SCSI +#define CONFIG_DOS_PARTITION +#define CONFIG_BOARD_LATE_INIT + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +#define CONFIG_SYS_SATA AHCI_BASE_ADDR + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + +/* + * IFC Definitions + */ +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR1_CSPR_EXT (0x0) +#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) + +#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NOR_TRHZ_80) +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1a) | \ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0xe) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0 + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ + CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} + +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define CONFIG_SYS_WRITE_SWAPPED_DATA + +/* + * NAND Flash Definitions + */ +#define CONFIG_NAND_FSL_IFC + +#define CONFIG_SYS_NAND_BASE 0x7e800000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE + +#define CONFIG_SYS_NAND_CSPR_EXT (0x0) + +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_NAND \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ + | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ + | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ + | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x7) | \ + FTIM0_NAND_TWH(0xa)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0xe) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ + FTIM2_NAND_TREH(0xa) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND + +#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) +#endif + +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SPL_PAD_TO 0x40000 /* block aligned */ +#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO +#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) +#endif + +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_QIXIS_I2C_ACCESS +#define CONFIG_SYS_I2C_EARLY_INIT +#define CONFIG_SYS_NO_FLASH +#endif + +/* + * QIXIS Definitions + */ +#define CONFIG_FSL_QIXIS + +#ifdef CONFIG_FSL_QIXIS +#define QIXIS_BASE 0x7fb00000 +#define QIXIS_BASE_PHYS QIXIS_BASE +#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define QIXIS_LBMAP_SWITCH 6 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_LBMAP_SHIFT 0 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x04 +#define QIXIS_LBMAP_NAND 0x09 +#define QIXIS_LBMAP_SD 0x00 +#define QIXIS_LBMAP_SD_QSPI 0xff +#define QIXIS_LBMAP_QSPI 0xff +#define QIXIS_RCW_SRC_NAND 0x110 +#define QIXIS_RCW_SRC_SD 0x040 +#define QIXIS_RCW_SRC_QSPI 0x045 +#define QIXIS_RST_CTL_RESET 0x41 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 + +#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) +#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ + CSPR_PORT_SIZE_8 | \ + CSPR_MSEL_GPCM | \ + CSPR_V) +#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) +#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NOR_NOR_MODE_AVD_NOR | \ + CSOR_NOR_TRHZ_80) + +/* + * QIXIS Timing parameters for IFC GPCM + */ +#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ + FTIM0_GPCM_TEADC(0x20) | \ + FTIM0_GPCM_TEAHC(0x10)) +#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ + FTIM1_GPCM_TRAD(0x1f)) +#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ + FTIM2_GPCM_TCH(0x8) | \ + FTIM2_GPCM_TWP(0xf0)) +#define CONFIG_SYS_FPGA_FTIM3 0x0 +#endif + +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT +#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR +#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK +#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR +#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 +#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 +#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 +#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT +#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR +#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK +#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR +#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 +#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 +#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 +#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#endif + +/* + * I2C bus multiplexer + */ +#define I2C_MUX_PCA_ADDR_PRI 0x77 +#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ +#define I2C_RETIMER_ADDR 0x18 +#define I2C_MUX_CH_DEFAULT 0x8 +#define I2C_MUX_CH_CH7301 0xC +#define I2C_MUX_CH5 0xD +#define I2C_MUX_CH6 0xE +#define I2C_MUX_CH7 0xF + +#define I2C_MUX_CH_VOL_MONITOR 0xa + +/* Voltage monitor on channel 2*/ +#define I2C_VOL_MONITOR_ADDR 0x40 +#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 +#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 +#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 + +#define CONFIG_VID_FLS_ENV "ls1046aqds_vdd_mv" +#ifndef CONFIG_SPL_BUILD +#define CONFIG_VID +#endif +#define CONFIG_VOL_MONITOR_IR36021_SET +#define CONFIG_VOL_MONITOR_INA220 +/* The lowest and highest voltage allowed for LS1046AQDS */ +#define VDD_MV_MIN 819 +#define VDD_MV_MAX 1212 + +/* + * Miscellaneous configurable options + */ +#define CONFIG_MISC_INIT_R +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END 0x9fffffff + +#define CONFIG_SYS_HZ 1000 + +/* + * Stack sizes + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (30 * 1024) + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +/* + * Environment + */ +#define CONFIG_ENV_OVERWRITE + +#ifdef CONFIG_NAND_BOOT +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SD_BOOT) +#define CONFIG_ENV_OFFSET (1024 * 1024) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#elif defined(CONFIG_QSPI_BOOT) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_SIZE 0x20000 +#endif + +#define CONFIG_CMDLINE_TAG + +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \ + "e0000 f00000 && bootm $kernel_load" +#else +#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ + "$kernel_size && bootm $kernel_load" +#endif + +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#define MTDPARTS_DEFAULT "mtdparts=1550000.quadspi:2m(uboot)," \ + "14m(free)" +#else +#define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \ + "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \ + "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \ + "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \ + "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \ + "40m(nor_bank4_fit);7e800000.flash:" \ + "4m(nand_uboot),36m(nand_kernel)," \ + "472m(nand_free);spi0.0:2m(uboot)," \ + "14m(free)" +#endif + +#include + +#endif /* __LS1046AQDS_H__ */ -- cgit v1.1 From da28e58a7fc169625334b1e40f72067b481b352a Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 26 Sep 2016 08:09:24 -0700 Subject: armv8: ls1046a: Convert CONFIG_LS1046A to Kconfig option ARCH_LS1046A Move this option to Kconfig and clean up existing uses. Signed-off-by: York Sun CC: Mingkai Hu CC: Gong Qianyu Reviewed-by: Tom Rini --- include/configs/ls1046a_common.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 5856de8..7c5e635 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -10,7 +10,6 @@ #define CONFIG_REMAKE_ELF #define CONFIG_FSL_LAYERSCAPE #define CONFIG_FSL_LSCH2 -#define CONFIG_LS1046A #define CONFIG_MP #define CONFIG_SYS_FSL_CLK #define CONFIG_GICV2 -- cgit v1.1 From 1fdcc8dfc7612acc765cd483051dcfaac399f4f1 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 26 Sep 2016 08:09:25 -0700 Subject: driver: ddr: fsl_mmdc: Pass board parameters through data structure Instead of using multiple macros, a data structure is used to pass board-specific parameters to MMDC DDR driver. Signed-off-by: York Sun CC: Shengzhou Liu Reviewed-by: Tom Rini --- include/configs/ls1012afrdm.h | 16 ---------------- include/configs/ls1012aqds.h | 16 ---------------- include/configs/ls1012ardb.h | 15 --------------- 3 files changed, 47 deletions(-) (limited to 'include/configs') diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h index 136d648..612f243 100644 --- a/include/configs/ls1012afrdm.h +++ b/include/configs/ls1012afrdm.h @@ -20,22 +20,6 @@ #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END 0x9fffffff -/* DDR board-specific timing parameters */ -#define CONFIG_MMDC_MDCTL 0x04180000 -#define CONFIG_MMDC_MDPDC 0x00030035 -#define CONFIG_MMDC_MDOTC 0x12554000 -#define CONFIG_MMDC_MDCFG0 0xbabf7954 -#define CONFIG_MMDC_MDCFG1 0xdb328f64 -#define CONFIG_MMDC_MDCFG2 0x01ff00db -#define CONFIG_MMDC_MDMISC 0x00001680 -#define CONFIG_MMDC_MDREF 0x0f3c8000 -#define CONFIG_MMDC_MDRWD 0x00002000 -#define CONFIG_MMDC_MDOR 0x00bf1023 -#define CONFIG_MMDC_MDASP 0x0000003f -#define CONFIG_MMDC_MPODTCTRL 0x0000022a -#define CONFIG_MMDC_MPZQHWCTRL 0xa1390003 - - /* * USB */ diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index b6d12dd..54abf30 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -19,22 +19,6 @@ #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END 0x9fffffff -/* DDR board-specific timing parameters */ -#define CONFIG_MMDC_MDCTL 0x05180000 -#define CONFIG_MMDC_MDPDC 0x00030035 -#define CONFIG_MMDC_MDOTC 0x12554000 -#define CONFIG_MMDC_MDCFG0 0xbabf7954 -#define CONFIG_MMDC_MDCFG1 0xdb328f64 -#define CONFIG_MMDC_MDCFG2 0x01ff00db -#define CONFIG_MMDC_MDMISC 0x00001680 -#define CONFIG_MMDC_MDREF 0x0f3c8000 -#define CONFIG_MMDC_MDRWD 0x00002000 -#define CONFIG_MMDC_MDOR 0x00bf1023 -#define CONFIG_MMDC_MDASP 0x0000003f -#define CONFIG_MMDC_MPODTCTRL 0x0000022a -#define CONFIG_MMDC_MPZQHWCTRL 0xa1390003 - - /* * QIXIS Definitions */ diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index 2076ce5..0c13dde 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -19,21 +19,6 @@ #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END 0x9fffffff -/* DDR board-specific timing parameters */ -#define CONFIG_MMDC_MDCTL 0x05180000 -#define CONFIG_MMDC_MDPDC 0x00030035 -#define CONFIG_MMDC_MDOTC 0x12554000 -#define CONFIG_MMDC_MDCFG0 0xbabf7954 -#define CONFIG_MMDC_MDCFG1 0xdb328f64 -#define CONFIG_MMDC_MDCFG2 0x01ff00db -#define CONFIG_MMDC_MDMISC 0x00001680 -#define CONFIG_MMDC_MDREF 0x0f3c8000 -#define CONFIG_MMDC_MDRWD 0x00002000 -#define CONFIG_MMDC_MDOR 0x00bf1023 -#define CONFIG_MMDC_MDASP 0x0000003f -#define CONFIG_MMDC_MPODTCTRL 0x0000022a -#define CONFIG_MMDC_MPZQHWCTRL 0xa1390003 - /* * USB */ -- cgit v1.1 From 9533acf36c8763af914edcff7c09573e160c1f4d Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 26 Sep 2016 08:09:26 -0700 Subject: armv8: ls1012a: Convert CONFIG_LS1012A to Kconfig option ARCH_LS1021A Move this config to Kconfig option and clean up existing uses. Signed-off-by: York Sun CC: Calvin Johnson CC: Prabhakar Kushwaha Reviewed-by: Tom Rini --- include/configs/ls1012a_common.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index fba2fac..5fb6c47 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -9,7 +9,6 @@ #define CONFIG_FSL_LAYERSCAPE #define CONFIG_FSL_LSCH2 -#define CONFIG_LS1012A #define CONFIG_GICV2 #define CONFIG_SYS_HAS_SERDES -- cgit v1.1 From 5e8bd7e117157eee591e377c80e024f12318cf9d Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 26 Sep 2016 08:09:29 -0700 Subject: armv7: ls1021a: Convert CONFIG_LS1_DEEP_SLEEP to Kconfig option Move this option to Kconfig and clean up existing uses. Signed-off-by: York Sun CC: Hongbo Zhang Reviewed-by: Tom Rini --- include/configs/ls1021aqds.h | 1 - include/configs/ls1021atwr.h | 1 - 2 files changed, 2 deletions(-) (limited to 'include/configs') diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 5aaecc7..7a256da 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -10,7 +10,6 @@ #define CONFIG_LS102XA #define CONFIG_ARMV7_PSCI_1_0 -#define CONFIG_LS1_DEEP_SLEEP #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index ef238a4..90ae770 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -10,7 +10,6 @@ #define CONFIG_LS102XA #define CONFIG_ARMV7_PSCI_1_0 -#define CONFIG_LS1_DEEP_SLEEP #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR -- cgit v1.1