From 0fe247b973d9b8f7e2c04cc159fcdd2e64591e55 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 5 Jul 2010 22:46:33 +0200 Subject: Drop support for GTH board The board maintainer states: The GTH board is obsolete and has not been manufactured for several years. To my knowledge, no recent U-Boot build has been tested on that card. So drop support for this board. Signed-off-by: Wolfgang Denk Cc: Thomas Lange Acked-by: Thomas Lange --- include/configs/GTH.h | 389 -------------------------------------------------- 1 file changed, 389 deletions(-) delete mode 100644 include/configs/GTH.h (limited to 'include/configs') diff --git a/include/configs/GTH.h b/include/configs/GTH.h deleted file mode 100644 index c2cf852..0000000 --- a/include/configs/GTH.h +++ /dev/null @@ -1,389 +0,0 @@ -/* - * Parameters for GTH board - * Based on FADS860T - * by thomas.lange@corelatus.com - - * A collection of structures, addresses, and values associated with - * the Motorola 860T FADS board. Copied from the MBX stuff. - * Magnus Damm added defines for 8xxrom and extended bd_info. - * Helmut Buchsbaum added bitvalues for BCSRx - * - * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) - */ - -/* - * ff000000 -> ff00ffff : IMAP internal in the cpu - * e0000000 -> ennnnnnn : pcmcia - * 98000000 -> 983nnnnn : FPGA 4MB - * 90000000 -> 903nnnnn : FPGA 4MB - * 80000000 -> 80nnnnnn : flash connected to CS0, final ( real ) location - * 00000000 -> nnnnnnnn : sdram - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#include - -#define CONFIG_MPC860 1 -#define CONFIG_MPC860T 1 -#define CONFIG_GTH 1 - -#define CONFIG_MISC_INIT_R 1 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 9600 -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ - -#define MPC8XX_FACT 3 /* Multiply by 3 */ -#define MPC8XX_XIN 16384000 /* 16.384 MHz */ -#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) - -#define CONFIG_BOOTDELAY 1 /* autoboot after 0 seconds */ - -#define CONFIG_ENV_OVERWRITE 1 /* Allow change of ethernet address */ - -#define CONFIG_BOOT_RETRY_TIME 5 /* Retry boot in 5 secs */ - -#define CONFIG_RESET_TO_RETRY 1 /* If timeout waiting for command, perform a reset */ - -/* Only interrupt boot if space is pressed */ -/* If a long serial cable is connected but */ -/* other end is dead, garbage will be read */ -#define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT \ - "Press space to abort autoboot in %d second\n", bootdelay -#define CONFIG_AUTOBOOT_DELAY_STR "d" -#define CONFIG_AUTOBOOT_STOP_STR " " - -#if 0 -/* Net boot */ -/* Loads a tftp image and starts it */ -#define CONFIG_BOOTCOMMAND "bootp;bootm 100000" /* autoboot command */ -#define CONFIG_BOOTARGS "panic=1" -#else -/* Compact flash boot */ -#define CONFIG_BOOTARGS "panic=1 root=/dev/hda7" -#define CONFIG_BOOTCOMMAND "disk 100000 0:5;bootm 100000" -#endif - -/* Enable watchdog */ -#define CONFIG_WATCHDOG 1 - -/* choose SCC1 ethernet (10BASET on motherboard) - * or FEC ethernet (10/100 on daughterboard) - */ -#if 1 -#define CONFIG_SCC1_ENET 1 /* use SCC1 ethernet */ -#undef CONFIG_FEC_ENET /* disable FEC ethernet */ -#define CONFIG_SYS_DISCOVER_PHY -#else -#undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */ -#define CONFIG_FEC_ENET 1 /* use FEC ethernet */ -#define CONFIG_SYS_DISCOVER_PHY -#endif -#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) -#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured -#endif - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_IDE - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_PROMPT "=>" /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ - -/* Default location to load data from net */ -#define CONFIG_SYS_LOAD_ADDR 0x100000 - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 -#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024)) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -#define CONFIG_SYS_FLASH_BASE 0x80000000 - -#define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ - -#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ - -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE - -#define CONFIG_SYS_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#undef CONFIG_ENV_IS_IN_EEPROM -#define CONFIG_ENV_OFFSET 0x000E0000 -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -#define CONFIG_ENV_SECT_SIZE 0x50000 /* see README - env sector total size */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*---------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ - -/*FIXME dont use for now */ -/*#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */ -/*#define CONFIG_SYS_RTCSC (RTCSC_RTF) */ - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) -/* PITE */ -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * set the PLL, the low-power modes and the reset control (15-29) - */ -#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ - -/* FIXME check values */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_TBS|SCCR_RTSEL|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00) - - /*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* Because of the way the 860 starts up and assigns CS0 the -* entire address space, we have to set the memory controller -* differently. Normally, you write the option register -* first, and then enable the chip select by writing the -* base register. For CS0, you must write the base register -* first, followed by the option register. -*/ - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ -/* the other CS:s are determined by looking at parameters in BCSRx */ - -#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ - -#define CONFIG_SYS_REMAP_OR_AM 0xFF800000 /* 4 MB OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ - -#define FPGA_2_BASE 0x90000000 -#define FPGA_3_BASE 0x98000000 - -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) - - -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/ -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16 ) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CONFIG_ETHADDR DE:AD:BE:EF:00:01 /* Ethernet address */ - -#ifdef CONFIG_MPC860T - -/* Interrupt level assignments. -*/ -#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ - -#endif /* CONFIG_MPC860T */ - -/* We don't use the 8259. -*/ -#define NR_8259_INTS 0 - -/* Machine type -*/ -#define _MACH_8xx (_MACH_gth) - -#ifdef CONFIG_MPC860 -#define PCMCIA_SLOT_A 1 -#define CONFIG_PCMCIA_SLOT_A 1 -#endif - -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ /* Force it - dont measure it */ - -#define PA_FRONT_LED ((u16)0x4) /* PA 13 */ -#define PA_FL_CONFIG ((u16)0x20) /* PA 10 */ -#define PA_FL_CE ((u16)0x1000) /* PA 3 */ - -#define PB_ID_GND ((u32)1) /* PB 31 */ -#define PB_REV_1 ((u32)2) /* PB 30 */ -#define PB_REV_0 ((u32)4) /* PB 29 */ -#define PB_BLUE_LED ((u32)0x400) /* PB 21 */ -#define PB_EEPROM ((u32)0x800) /* PB 20 */ -#define PB_ID_3 ((u32)0x2000) /* PB 18 */ -#define PB_ID_2 ((u32)0x4000) /* PB 17 */ -#define PB_ID_1 ((u32)0x8000) /* PB 16 */ -#define PB_ID_0 ((u32)0x10000) /* PB 15 */ - -/* NOTE. This is reset for 100Mbit port only */ -#define PC_ENET100_RESET ((ushort)0x0080) /* PC 8 */ - -#endif /* __CONFIG_H */ -- cgit v1.1 From 99d9c07edc6e0b7b35694992f1cc40b540eec3ce Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 8 Jul 2010 22:23:54 -0500 Subject: powerpc/85xx: Move PCI/PCIe address defines into common immap_85xx.h Remove dupliacted setting of PCI/PCIe address and offsets in board config.h. Signed-off-by: Kumar Gala --- include/configs/ATUM8548.h | 3 --- include/configs/MPC8536DS.h | 5 ----- include/configs/MPC8544DS.h | 5 ----- include/configs/MPC8548CDS.h | 4 ---- include/configs/MPC8568MDS.h | 3 --- include/configs/MPC8569MDS.h | 3 --- include/configs/MPC8572DS.h | 4 ---- include/configs/P1022DS.h | 4 ---- include/configs/P1_P2_RDB.h | 3 --- include/configs/P2020DS.h | 4 ---- include/configs/TQM85xx.h | 4 ---- include/configs/XPEDITE5200.h | 1 - include/configs/XPEDITE5370.h | 2 -- include/configs/sbc8548.h | 4 ---- 14 files changed, 49 deletions(-) (limited to 'include/configs') diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h index 49a86fd..c133033 100644 --- a/include/configs/ATUM8548.h +++ b/include/configs/ATUM8548.h @@ -91,9 +91,6 @@ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ #define PCI_SPEED 33333000 /* CPLD currenlty does not have PCI setup info */ -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) /* DDR Setup */ #define CONFIG_FSL_DDR2 diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index a014ad0..24a75c6 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -125,11 +125,6 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #endif -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) -#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR + 0xb000) - /* DDR Setup */ #define CONFIG_VERY_BIG_RAM #define CONFIG_FSL_DDR2 diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index faba353..96fd024 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -79,11 +79,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) -#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0xb000) - /* DDR Setup */ #define CONFIG_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index fdd3597..23594a7 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -80,10 +80,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) - /* DDR Setup */ #define CONFIG_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 0cc2d47..bc6c5c7 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -75,9 +75,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) - /* DDR Setup */ #define CONFIG_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index bb7bb47..92c2b49 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -103,9 +103,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #endif -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) - /* DDR Setup */ #define CONFIG_FSL_DDR3 #undef CONFIG_FSL_DDR_INTERACTIVE diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 57c2f2f..51e5d06 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -89,10 +89,6 @@ #endif #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ -#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) - /* DDR Setup */ #define CONFIG_VERY_BIG_RAM #define CONFIG_FSL_DDR2 diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index b42b5d0..d31b550 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -60,10 +60,6 @@ #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) /* pci0 */ -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0xa000) /* pci1 */ -#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR + 0xb000) /* pci2 */ - /* DDR Setup */ #define CONFIG_DDR_SPD #define CONFIG_VERY_BIG_RAM diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 3cebbab..fca3cdd 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -129,9 +129,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #endif -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) - /* DDR Setup */ #define CONFIG_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 569da4f..bf2acbf 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -90,10 +90,6 @@ #endif #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ -#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) - /* DDR Setup */ #define CONFIG_VERY_BIG_RAM #define CONFIG_FSL_DDR3 1 diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index 90abe14..d8f2602 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -137,10 +137,6 @@ #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000) -#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000) - /* * DDR Setup */ diff --git a/include/configs/XPEDITE5200.h b/include/configs/XPEDITE5200.h index df5ef78..83aeffd 100644 --- a/include/configs/XPEDITE5200.h +++ b/include/configs/XPEDITE5200.h @@ -81,7 +81,6 @@ #define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */ #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000) /* * Diagnostics diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h index 1d6091c..fc4a986 100644 --- a/include/configs/XPEDITE5370.h +++ b/include/configs/XPEDITE5370.h @@ -99,8 +99,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */ #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) /* * Diagnostics diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 3f4056e..c8b8d0d 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -109,10 +109,6 @@ #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) - /* DDR Setup */ #define CONFIG_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE -- cgit v1.1 From dd2cda3dbd0130445e5186c6f038016474666337 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 8 Jul 2010 22:35:59 -0500 Subject: powerpc/86xx: Move PCI/PCIe address defines into common immap_86xx.h Remove dupliacted setting of PCI/PCIe address and offsets in board config.h. Renamed CONFIG_SYS_PCI1/2_ADDR to CONFIG_SYS_PCI1/2ADDR on MPC8641 boards since its really PCIE controllers and not PCI. Signed-off-by: Kumar Gala --- include/configs/MPC8610HPCD.h | 4 ---- include/configs/MPC8641HPCN.h | 3 --- include/configs/XPEDITE5170.h | 2 -- include/configs/sbc8641d.h | 3 --- 4 files changed, 12 deletions(-) (limited to 'include/configs') diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 8382e3c..4d9606e 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -82,10 +82,6 @@ #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) - #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR+0x2c000) /* DDR Setup */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 94e4d24..b183e02 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -122,9 +122,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW #endif -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) - /* * DDR Setup */ diff --git a/include/configs/XPEDITE5170.h b/include/configs/XPEDITE5170.h index c63fd42..8770a8d 100644 --- a/include/configs/XPEDITE5170.h +++ b/include/configs/XPEDITE5170.h @@ -97,8 +97,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) /* * Diagnostics diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 315eebe..6662bbe 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -108,9 +108,6 @@ #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) - /* * DDR Setup */ -- cgit v1.1 From 46f3e3851dac0c4acecf4192d8e13c8521ce98b4 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 9 Jul 2010 00:02:34 -0500 Subject: powerpc/86xx: Rename PCI1/2 to PCIE1/2 on MPC8641HPCN & SBC8641 The MPC8641 boards actually only have PCIE not PCI. Rename so we are uniform with regards to names so we can replace this code with templated code. Signed-off-by: Kumar Gala --- include/configs/MPC8641HPCN.h | 80 +++++++++++++++++++++---------------------- include/configs/sbc8641d.h | 50 +++++++++++++-------------- 2 files changed, 64 insertions(+), 66 deletions(-) (limited to 'include/configs') diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index b183e02..0d1f779 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -1,5 +1,5 @@ /* - * Copyright 2006 Freescale Semiconductor. + * Copyright 2006, 2010 Freescale Semiconductor. * * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * @@ -58,8 +58,8 @@ #ifndef CONFIG_RIO /* RIO/PCI are mutually exclusive */ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ -#define CONFIG_PCI1 1 /* PCIE controler 1 (ULI bridge) */ -#define CONFIG_PCI2 1 /* PCIE controler 2 (slot) */ +#define CONFIG_PCIE1 1 /* PCIE controler 1 (ULI bridge) */ +#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot) */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #endif @@ -325,43 +325,43 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * Addresses are mapped 1-1. */ -#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCI1_MEM_PHYS 0x0000000c00000000ULL +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0x0000000c00000000ULL #else -#define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_VIRT -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_VIRT +#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT +#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_VIRT #endif -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 -#define CONFIG_SYS_PCI1_IO_PHYS (CONFIG_SYS_PCI1_IO_VIRT \ +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 +#define CONFIG_SYS_PCIE1_IO_PHYS (CONFIG_SYS_PCIE1_IO_VIRT \ | CONFIG_SYS_PHYS_ADDR_HIGH) -#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64K */ +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */ #ifdef CONFIG_PHYS_64BIT /* - * Use the same PCI bus address on PCI1 and PCI2 if we have PHYS_64BIT. + * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT. * This will increase the amount of PCI address space available for * for mapping RAM. */ -#define CONFIG_SYS_PCI2_MEM_BUS CONFIG_SYS_PCI1_MEM_BUS +#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS #else -#define CONFIG_SYS_PCI2_MEM_BUS (CONFIG_SYS_PCI1_MEM_BUS \ - + CONFIG_SYS_PCI1_MEM_SIZE) +#define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \ + + CONFIG_SYS_PCIE1_MEM_SIZE) #endif -#define CONFIG_SYS_PCI2_MEM_VIRT (CONFIG_SYS_PCI1_MEM_VIRT \ - + CONFIG_SYS_PCI1_MEM_SIZE) -#define CONFIG_SYS_PCI2_MEM_PHYS (CONFIG_SYS_PCI1_MEM_PHYS \ - + CONFIG_SYS_PCI1_MEM_SIZE) -#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCI2_IO_VIRT (CONFIG_SYS_PCI1_IO_VIRT \ - + CONFIG_SYS_PCI1_IO_SIZE) -#define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS \ - + CONFIG_SYS_PCI1_IO_SIZE) -#define CONFIG_SYS_PCI2_IO_SIZE CONFIG_SYS_PCI1_IO_SIZE +#define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \ + + CONFIG_SYS_PCIE1_MEM_SIZE) +#define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \ + + CONFIG_SYS_PCIE1_MEM_SIZE) +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \ + + CONFIG_SYS_PCIE1_IO_SIZE) +#define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \ + + CONFIG_SYS_PCIE1_IO_SIZE) +#define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE #if defined(CONFIG_PCI) @@ -390,10 +390,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 /*PCIE video card used*/ -#define VIDEO_IO_OFFSET CONFIG_SYS_PCI2_IO_VIRT +#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT /*PCI video card used*/ -/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ +/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/ /* video */ #define CONFIG_VIDEO @@ -406,7 +406,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_ATI_RADEON_FB #define CONFIG_VIDEO_LOGO /*#define CONFIG_CONSOLE_CURSOR*/ -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCI2_IO_VIRT +#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT #endif #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ @@ -422,8 +422,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE #endif -#define CONFIG_MPC86XX_PCI2 - #endif /* CONFIG_PCI */ #if defined(CONFIG_TSEC_ENET) @@ -494,17 +492,17 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U /* if CONFIG_PCI: - * BAT2 PCI1 and PCI1 MEM + * BAT2 PCIE1 and PCIE1 MEM * if CONFIG_RIO * BAT2 Rapidio Memory */ #ifdef CONFIG_PCI -#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \ +#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS) \ | BATL_PP_RW | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G \ +#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \ | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \ +#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS) \ | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U #else /* CONFIG_RIO */ @@ -553,14 +551,14 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif /* - * BAT4 PCI1_IO and PCI2_IO + * BAT4 PCIE1_IO and PCIE2_IO */ -#define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \ +#define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS) \ | BATL_PP_RW | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_128K \ +#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \ | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \ +#define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS) \ | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 6662bbe..618513a 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -56,8 +56,8 @@ #define CONFIG_SYS_SCRATCH_VA 0xe8000000 #define CONFIG_PCI 1 /* Enable PCIE */ -#define CONFIG_PCI1 1 /* PCIE controler 1 (slot 1) */ -#define CONFIG_PCI2 1 /* PCIE controler 2 (slot 2) */ +#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ +#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ @@ -304,23 +304,23 @@ * General PCI * Addresses are mapped 1-1. */ -#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS -#define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BUS 0xe2000000 -#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BUS -#define CONFIG_SYS_PCI1_IO_VIRT CONFIG_SYS_PCI1_IO_BUS -#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ - -#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BUS -#define CONFIG_SYS_PCI2_MEM_VIRT CONFIG_SYS_PCI2_MEM_BUS -#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI2_IO_BUS 0xe3000000 -#define CONFIG_SYS_PCI2_IO_PHYS CONFIG_SYS_PCI2_IO_BUS -#define CONFIG_SYS_PCI2_IO_VIRT CONFIG_SYS_PCI2_IO_BUS -#define CONFIG_SYS_PCI2_IO_SIZE 0x1000000 /* 16M */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS +#define CONFIG_SYS_PCIE1_MEM_VIRT CONFIG_SYS_PCIE1_MEM_BUS +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0xe2000000 +#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS +#define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_BUS +#define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */ + +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS +#define CONFIG_SYS_PCIE2_MEM_VIRT CONFIG_SYS_PCIE2_MEM_BUS +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0xe3000000 +#define CONFIG_SYS_PCIE2_IO_PHYS CONFIG_SYS_PCIE2_IO_BUS +#define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_BUS +#define CONFIG_SYS_PCIE2_IO_SIZE 0x1000000 /* 16M */ #if defined(CONFIG_PCI) @@ -406,10 +406,10 @@ * 0xa000_0000 512M PCI-Express 2 Memory * Changed it for operating from 0xd0000000 */ -#define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \ +#define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U /* @@ -449,10 +449,10 @@ * 0xe300_0000 16M PCI-Express 2 I/0 * Note that this is at 0xe0000000 */ -#define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW \ +#define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U /* -- cgit v1.1 From af0250652a775799da656f74719bdefb45fda7d5 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Sat, 22 May 2010 13:21:39 -0500 Subject: powerpc/85xx: Rework MPC8536 SERDES is_serdes_configured support Move serdes init until after we are in ram so we can keep track of a global static protocal map for the particular serdes config we are in. This makes is_serdes_configured() much simplier and not constantly reading registers to determine if a given device is enabled based on the protocol. Signed-off-by: Kumar Gala --- include/configs/MPC8536DS.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/configs') diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 24a75c6..890a6c9 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -65,6 +65,7 @@ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ +#define CONFIG_SYS_HAS_SERDES /* has SERDES */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/ -- cgit v1.1 From 47ec10c5975f0ce8f4a748c7b76c45c0fb60c0ac Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Sun, 11 Jul 2010 12:41:46 -0500 Subject: powerpc/85xx: Rework P1022 SERDES is_serdes_configured support Move serdes init until after we are in ram so we can keep track of a global static protocal map for the particular serdes config we are in. This makes is_serdes_configured() much simplier and not constantly reading registers to determine if a given device is enabled based on the protocol. Signed-off-by: Kumar Gala --- include/configs/P1022DS.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/configs') diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index d31b550..f9d12f5 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -30,6 +30,7 @@ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ +#define CONFIG_SYS_HAS_SERDES /* has SERDES */ #define CONFIG_PHYS_64BIT #define CONFIG_ENABLE_36BIT_PHYS -- cgit v1.1 From 17a684449728ce4c9ce79fa9e7e75b86a5f9b41d Mon Sep 17 00:00:00 2001 From: Rupjyoti Sarmah Date: Wed, 7 Jul 2010 18:14:48 +0530 Subject: ppc4xx/Canyonlands added USB board callbacks Functions added to support board callbacks for USB init. This isolates USB manipulations such that it is only touched if USB is used by U-Boot. Signed-off-by: Dave Mitchell Signed-off-by: Rupjyoti Sarmah Signed-off-by: Stefan Roese --- include/configs/canyonlands.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'include/configs') diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index ac9b3c5..6fe7639 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -77,6 +77,13 @@ #define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000 #define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000 +/* + * BCSR bits as defined in the Canyonlands board user manual. + */ +#define BCSR_USBCTRL_OTG_RST 0x32 +#define BCSR_USBCTRL_HOST_RST 0x01 +#define BCSR_SELECT_PCIE 0x10 + #define CONFIG_SYS_PCIE0_UTLBASE 0xc08010000ULL /* 36bit physical addr */ /* base address of inbound PCIe window */ @@ -417,6 +424,7 @@ #define CONFIG_SYS_USB_OHCI_REGS_BASE (CONFIG_SYS_AHB_BASE | 0xd0000) #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 +#define CONFIG_SYS_USB_OHCI_BOARD_INIT #endif /* -- cgit v1.1 From 5bf39a96c2b236baf8ef5b7a1e78a18f83152f27 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 19 Jul 2010 14:24:22 +0200 Subject: ppc4xx: T3CORP fixes and updates This patch fixes some problems for the T3CORP board. Here the list of the changes: - Add 600-67 and 677 CPU frequency setting to chip_config command - Define CONFIG_DDR_RFDC_FIXED on t3corp: While using the "normal" auto calibration code, sometimes values for RFDC were picked (>= T3) that resulted in a non-working U-Boot (hang upon relocation, while running from SDRAM). With this optimized RFDC value we can force this register and use the auto-calibration code to setup the remaining calibration registers. - Increase sizes of FPGA chips selects - EBC timing updated OEN=3 for 66 MHz EBC speed - Change ext. IRQ2 setup to level-low active - Enable CONFIG_SYS_CFI_FLASH_STATUS_POLL By defining CONFIG_SYS_CFI_FLASH_STATUS_POLL, DQ7 is polled to detect the chip busy status. This is now used instead of the data toggle method which is used historically by default in the common CFI driver. With this change a problem with not written data is solved on this board, where a 32 byte block of data is still erased instead of filled with the correct content after these commands: => erase 0xfc100000 +0x1000000 .................................................................... done Erased 128 sectors => cp.b 0x100000 0xfc100000 0x1000000 Copy to Flash... done => cmp.b 0x100000 0xfc100000 0x1000000 byte at 0x00d0d6c0 (0x00) != byte at 0xfcd0d6c0 (0xff) Total of 12637888 bytes were the same Signed-off-by: Stefan Roese --- include/configs/t3corp.h | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) (limited to 'include/configs') diff --git a/include/configs/t3corp.h b/include/configs/t3corp.h index 0ecc5b1..7b88601 100644 --- a/include/configs/t3corp.h +++ b/include/configs/t3corp.h @@ -74,8 +74,8 @@ #define CONFIG_SYS_FLASH_SIZE (64 << 20) #define CONFIG_SYS_FPGA1_BASE 0xe0000000 -#define CONFIG_SYS_FPGA2_BASE 0xe0100000 -#define CONFIG_SYS_FPGA3_BASE 0xe0200000 +#define CONFIG_SYS_FPGA2_BASE 0xe2000000 +#define CONFIG_SYS_FPGA3_BASE 0xe4000000 #define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space */ #define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4 @@ -84,14 +84,12 @@ (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) \ | (u64)CONFIG_SYS_FLASH_BASE_PHYS_L) -#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 64k */ +#define CONFIG_SYS_OCM_BASE 0xE7000000 /* OCM: 64k */ #define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */ #define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000 #define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal periph. */ -#define CONFIG_SYS_AHB_BASE 0xE2000000 /* int. AHB periph. */ - /* * Initial RAM & stack pointer (placed in OCM) */ @@ -121,6 +119,7 @@ #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD reset cmd */ +#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method */ #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ @@ -144,10 +143,13 @@ /* * DDR2 SDRAM */ +#define CONFIG_SYS_MBYTES_SDRAM 256 +#define CONFIG_DDR_ECC #define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */ #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */ #define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */ #undef CONFIG_PPC4xx_DDR_METHOD_A +#define CONFIG_DDR_RFDC_FIXED 0x000001D7 /* optimal value */ /* DDR1/2 SDRAM Device Control Register Data Values */ /* Memory Queue */ @@ -162,9 +164,6 @@ #define CONFIG_SYS_SDRAM_CONF1HB 0x80001C80 #define CONFIG_SYS_SDRAM_CONFPATHB 0x10a68000 -#define CONFIG_DDR_ECC -#define CONFIG_SYS_MBYTES_SDRAM 256 - #define CAS_LATENCY JEDEC_MA_MR_CL_DDR2_5_0_CLK /* DDR1/2 SDRAM Device Control Register Data Values */ @@ -417,7 +416,7 @@ #define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \ EBC_BXAP_TWT_ENCODE(5) | \ EBC_BXAP_CSN_ENCODE(0) | \ - EBC_BXAP_OEN_ENCODE(4) | \ + EBC_BXAP_OEN_ENCODE(3) | \ EBC_BXAP_WBN_ENCODE(0) | \ EBC_BXAP_WBF_ENCODE(0) | \ EBC_BXAP_TH_ENCODE(1) | \ @@ -426,7 +425,7 @@ EBC_BXAP_BEM_RW | \ EBC_BXAP_PEN_DISABLED) #define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \ - EBC_BXCR_BS_1MB | \ + EBC_BXCR_BS_32MB | \ EBC_BXCR_BU_RW | \ EBC_BXCR_BW_32BIT) @@ -434,7 +433,7 @@ #define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \ EBC_BXAP_TWT_ENCODE(5) | \ EBC_BXAP_CSN_ENCODE(0) | \ - EBC_BXAP_OEN_ENCODE(4) | \ + EBC_BXAP_OEN_ENCODE(3) | \ EBC_BXAP_WBN_ENCODE(0) | \ EBC_BXAP_WBF_ENCODE(0) | \ EBC_BXAP_TH_ENCODE(1) | \ @@ -443,7 +442,7 @@ EBC_BXAP_BEM_RW | \ EBC_BXAP_PEN_DISABLED) #define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA2_BASE) | \ - EBC_BXCR_BS_1MB | \ + EBC_BXCR_BS_16MB | \ EBC_BXCR_BU_RW | \ EBC_BXCR_BW_32BIT) @@ -451,7 +450,7 @@ #define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_DISABLED | \ EBC_BXAP_TWT_ENCODE(5) | \ EBC_BXAP_CSN_ENCODE(0) | \ - EBC_BXAP_OEN_ENCODE(4) | \ + EBC_BXAP_OEN_ENCODE(3) | \ EBC_BXAP_WBN_ENCODE(0) | \ EBC_BXAP_WBF_ENCODE(0) | \ EBC_BXAP_TH_ENCODE(1) | \ @@ -460,7 +459,7 @@ EBC_BXAP_BEM_RW | \ EBC_BXAP_PEN_DISABLED) #define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA3_BASE) | \ - EBC_BXCR_BS_1MB | \ + EBC_BXCR_BS_16MB | \ EBC_BXCR_BU_RW | \ EBC_BXCR_BW_32BIT) -- cgit v1.1 From e37228602592b347a7741f0d2d12755295517584 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 22 Jul 2010 19:06:14 +0200 Subject: ppc4xx: Enable "ecctest" command on katmai Signed-off-by: Stefan Roese --- include/configs/katmai.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/configs') diff --git a/include/configs/katmai.h b/include/configs/katmai.h index fb8ccae..76e9a76 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -202,6 +202,7 @@ */ #define CONFIG_CMD_CHIP_CONFIG #define CONFIG_CMD_DATE +#define CONFIG_CMD_ECCTEST #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT #define CONFIG_CMD_PCI -- cgit v1.1 From 1ffcb86ce06a252ff6f4620691eb347c8ab47b61 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 22 Jul 2010 19:06:27 +0200 Subject: ppc4xx: Enable "ecctest" command on t3corp Signed-off-by: Stefan Roese --- include/configs/t3corp.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/configs') diff --git a/include/configs/t3corp.h b/include/configs/t3corp.h index 7b88601..b38886b 100644 --- a/include/configs/t3corp.h +++ b/include/configs/t3corp.h @@ -359,6 +359,7 @@ * Commands additional to the ones defined in amcc-common.h */ #define CONFIG_CMD_CHIP_CONFIG +#define CONFIG_CMD_ECCTEST #define CONFIG_CMD_PCI #define CONFIG_CMD_SDRAM -- cgit v1.1