From 8a1cdaa9d54c93db300e8565191d60712aa481dc Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 28 Apr 2010 12:54:43 +0200 Subject: QONG: Adapt flash addresses and mtdparts to grown image size Also enable HUSH shell. Signed-off-by: Wolfgang Denk --- include/configs/qong.h | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) (limited to 'include/configs') diff --git a/include/configs/qong.h b/include/configs/qong.h index e41ea91..61acb04 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -127,9 +127,9 @@ " console=ttymxc0,${baudrate}\0" \ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ "addmisc=setenv bootargs ${bootargs}\0" \ - "uboot_addr=a0000000\0" \ - "kernel_addr=a0080000\0" \ - "ramdisk_addr=a0300000\0" \ + "uboot_addr=A0000000\0" \ + "kernel_addr=A00A0000\0" \ + "ramdisk_addr=A0300000\0" \ "u-boot=qong/u-boot.bin\0" \ "kernel_addr_r=80800000\0" \ "hostname=qong\0" \ @@ -172,6 +172,10 @@ #define CONFIG_SYS_HZ 1000 #define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#endif #define CONFIG_MISC_INIT_R 1 /*----------------------------------------------------------------------- @@ -228,7 +232,7 @@ #define CONFIG_FLASH_CFI_MTD #define MTDIDS_DEFAULT "nor0=physmap-flash.0" #define MTDPARTS_DEFAULT \ - "mtdparts=physmap-flash.0:256k(U-Boot),128k(env1)," \ - "128k(env2),2560k(kernel),13m(ramdisk),-(user)" + "mtdparts=physmap-flash.0:384k(U-Boot),128k(env1)," \ + "128k(env2),2432k(kernel),13m(ramdisk),-(user)" #endif /* __CONFIG_H */ -- cgit v1.1 From 029faf3e85e9406f32f133e6f2a114ed26b02fb4 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 27 Apr 2010 11:37:28 +0200 Subject: ppc4xx: Add support for ICON board (PPC440SPe) This patch adds support for the Mosaix Technologies, Inc. ICON board, based on the AppliedMicro (AMCC) PPC440SPe. It's equipped with an SODIMM (512MB standard) and 64MByte of NOR FLASH. Support for the onboard SM502 will be added later. Signed-off-by: Stefan Roese --- include/configs/icon.h | 308 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 308 insertions(+) create mode 100644 include/configs/icon.h (limited to 'include/configs') diff --git a/include/configs/icon.h b/include/configs/icon.h new file mode 100644 index 0000000..3a57d69 --- /dev/null +++ b/include/configs/icon.h @@ -0,0 +1,308 @@ +/* + * (C) Copyright 2009-2010 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * icon.h - configuration for Mosaixtech ICON (440SPe) + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_ICON 1 /* Board is icon */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_440 1 /* ... PPC440 family */ +#define CONFIG_440SPE 1 /* Specifc SPe support */ +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ +#define CONFIG_SYS_4xx_RESET_TYPE 0x2 /* use chip reset on this board */ + +/* + * Include common defines/options for all AMCC eval boards + */ +#define CONFIG_HOSTNAME icon +#include "amcc-common.h" + +#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ +#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */ + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* later mapped to this addr */ +#define CONFIG_SYS_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */ +#define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */ + +#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */ +#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ +#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE + +#define CONFIG_SYS_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */ +#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* incr for PCIe port */ +#define CONFIG_SYS_PCIE_BASE 0xe0000000 /* PCIe UTL regs */ + +#define CONFIG_SYS_PCIE0_CFGBASE 0xc0000000 +#define CONFIG_SYS_PCIE1_CFGBASE 0xc1000000 +#define CONFIG_SYS_PCIE2_CFGBASE 0xc2000000 +#define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000 +#define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000 +#define CONFIG_SYS_PCIE2_XCFGBASE 0xc3002000 + +/* base address of inbound PCIe window */ +#define CONFIG_SYS_PCIE_INBOUND_BASE 0x0000000000000000ULL + +/* System RAM mapped to PCI space */ +#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) + +#define CONFIG_SYS_ACE_BASE 0xfb000000 /* Xilinx ACE CF */ +#define CONFIG_SYS_ACE_BASE_PHYS_H 0x4 +#define CONFIG_SYS_ACE_BASE_PHYS_L 0xfe000000 + +#define CONFIG_SYS_FLASH_SIZE (64 << 20) +#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space */ +#define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4 +#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xEC000000 +#define CONFIG_SYS_FLASH_BASE_PHYS (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) | \ + (u64)CONFIG_SYS_FLASH_BASE_PHYS_L) + +/* + * Initial RAM & stack pointer (placed in internal SRAM) + */ +#define CONFIG_SYS_TEMP_STACK_OCM 1 +#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Init RAM */ +#define CONFIG_SYS_INIT_RAM_END 0x2000 /* end used area */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* sizeof init data */ + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ + CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR + +/* + * Serial Port + */ +#undef CONFIG_UART1_CONSOLE +#undef CONFIG_SYS_EXT_SERIAL_CLOCK + +/* + * DDR2 SDRAM + */ +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ +#define SPD_EEPROM_ADDRESS { 0x51 } /* SPD I2C SPD addresses */ +#define CONFIG_DDR_ECC /* with ECC support */ +#define CONFIG_DDR_RQDC_FIXED 0x80000038 /* fixed value for RQDC */ + +/* + * I2C + */ +#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ + +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_SPD_BUS_NUM 0 /* The I2C bus for SPD */ + +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 + +/* I2C bootstrap EEPROM */ +#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50 +#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 +#define CONFIG_4xx_CONFIG_BLOCKSIZE 8 + +/* I2C RTC */ +#define CONFIG_RTC_M41T11 +#define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux */ + +/* + * Environment + */ +#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment uses flash */ + +/* + * Default environment variables + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ + "kernel_addr=fc000000\0" \ + "fdt_addr=fc1e0000\0" \ + "ramdisk_addr=fc200000\0" \ + "pciconfighost=1\0" \ + "pcie_mode=RP:RP:RP\0" \ + "" + +/* + * Commands additional to the ones defined in amcc-common.h + */ +#define CONFIG_CMD_CHIP_CONFIG +#define CONFIG_CMD_DATE +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_PCI +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_SNTP + +#define CONFIG_IBM_EMAC4_V4 /* 440SPe has this EMAC version */ +#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ +#define CONFIG_HAS_ETH0 +#define CONFIG_PHY_RESET /* reset phy upon startup */ +#define CONFIG_PHY_RESET_DELAY 1000 +#define CONFIG_CIS8201_PHY /* Enable RGMII mode for Cicada phy */ +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex det. */ + +/* + * FLASH related + */ +#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_SYS_FLASH_CFI_AMD_RESET /* Use AMD (Spansion) reset cmd */ +#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method */ + +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors*/ + +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */ +#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector */ + +#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Env Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +/* + * PCI stuff + */ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_PCI_CONFIG_HOST_BRIDGE +#define CONFIG_PCI_BOOTDELAY 1000 /* enable pci bootdelay variable*/ + +/* Board-specific PCI */ +#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */ +#undef CONFIG_SYS_PCI_MASTER_INIT + +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ +#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ + +/* + * Xilinx System ACE support + */ +#define CONFIG_SYSTEMACE /* Enable SystemACE support */ +#define CONFIG_SYS_SYSTEMACE_WIDTH 16 /* Data bus width is 16 */ +#define CONFIG_SYS_SYSTEMACE_BASE CONFIG_SYS_ACE_BASE +#define CONFIG_DOS_PARTITION + +/* + * External Bus Controller (EBC) Setup + */ + +/* Memory Bank 0 (Flash) initialization */ +#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(7) | \ + EBC_BXAP_BCE_DISABLE | \ + EBC_BXAP_BCT_2TRANS | \ + EBC_BXAP_CSN_ENCODE(0) | \ + EBC_BXAP_OEN_ENCODE(0) | \ + EBC_BXAP_WBN_ENCODE(0) | \ + EBC_BXAP_WBF_ENCODE(0) | \ + EBC_BXAP_TH_ENCODE(0) | \ + EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_SOR_DELAYED | \ + EBC_BXAP_BEM_WRITEONLY | \ + EBC_BXAP_PEN_DISABLED) +#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \ + EBC_BXCR_BS_64MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_16BIT) + +/* Memory Bank 1 (Xilinx System ACE controller) initialization */ +#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(4) | \ + EBC_BXAP_BCE_DISABLE | \ + EBC_BXAP_BCT_2TRANS | \ + EBC_BXAP_CSN_ENCODE(0) | \ + EBC_BXAP_OEN_ENCODE(0) | \ + EBC_BXAP_WBN_ENCODE(0) | \ + EBC_BXAP_WBF_ENCODE(0) | \ + EBC_BXAP_TH_ENCODE(0) | \ + EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_SOR_NONDELAYED | \ + EBC_BXAP_BEM_WRITEONLY | \ + EBC_BXAP_PEN_DISABLED) +#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_ACE_BASE_PHYS_L) | \ + EBC_BXCR_BS_1MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_16BIT) + +/* + * Initialize EBC CONFIG - + * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC + * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000 + */ +#define CONFIG_SYS_EBC_CFG (EBC_CFG_LE_UNLOCK | \ + EBC_CFG_PTD_ENABLE | \ + EBC_CFG_RTC_16PERCLK | \ + EBC_CFG_ATC_PREVIOUS | \ + EBC_CFG_DTC_PREVIOUS | \ + EBC_CFG_CTC_PREVIOUS | \ + EBC_CFG_OEO_PREVIOUS | \ + EBC_CFG_EMC_DEFAULT | \ + EBC_CFG_PME_DISABLE | \ + EBC_CFG_PR_16) + +/* + * GPIO Setup + */ +#define CONFIG_SYS_GPIO_PCIE_PRESENT0 17 +#define CONFIG_SYS_GPIO_PCIE_PRESENT1 21 +#define CONFIG_SYS_GPIO_PCIE_PRESENT2 23 +#define CONFIG_SYS_GPIO_RS232_FORCEOFF 30 + +#define CONFIG_SYS_PFC0 (GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0) | \ + GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1) | \ + GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2) | \ + GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)) +#define CONFIG_SYS_GPIO_OR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF) +#define CONFIG_SYS_GPIO_TCR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF) +#define CONFIG_SYS_GPIO_ODR 0 + +#endif /* __CONFIG_H */ -- cgit v1.1 From d3061c692155412aa87e7f4f66b4a2c7b77ee417 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 28 Apr 2010 11:09:59 +0200 Subject: ppc4xx: Fix APC405 build breakage This patch fixes APC405 build, by defining CONFIG_PPC4XX_I2C. This is needed since the move of the PPC4xx I2C driver into the drivers/i2c directory. Signed-off-by: Stefan Roese Cc: Matthias Fuchs --- include/configs/APC405.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/configs') diff --git a/include/configs/APC405.h b/include/configs/APC405.h index 41eaaab..20849bc 100644 --- a/include/configs/APC405.h +++ b/include/configs/APC405.h @@ -304,6 +304,7 @@ extern int flash_banks; * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F -- cgit v1.1 From b88c5988db176a0f9de5598d5167ee2498637d40 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Tue, 13 Apr 2010 21:11:53 -0500 Subject: configs: remove unused CONFIG_COMMAND_HISTORY $ git grep CONFIG_COMMAND_HISTORY CHANGELOG: CONFIG_COMMAND_HISTORY include/configs/AP1000.h:#define CONFIG_COMMAND_HISTORY 1 include/configs/keymile-common.h:#define CONFIG_COMMAND_HISTORY 1 include/configs/manroland/common.h:#define CONFIG_COMMAND_HISTORY 1 $ Signed-off-by: Kim Phillips Acked-by: Heiko Schocher --- include/configs/AP1000.h | 1 - include/configs/keymile-common.h | 1 - include/configs/manroland/common.h | 1 - 3 files changed, 3 deletions(-) (limited to 'include/configs') diff --git a/include/configs/AP1000.h b/include/configs/AP1000.h index ec982bd..ae0a873 100644 --- a/include/configs/AP1000.h +++ b/include/configs/AP1000.h @@ -34,7 +34,6 @@ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_COMMAND_EDIT 1 -#define CONFIG_COMMAND_HISTORY 1 #define CONFIG_COMPLETE_ADDRESSES 1 #define CONFIG_ENV_IS_IN_FLASH 1 diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h index 729d1c0..3a9f790 100644 --- a/include/configs/keymile-common.h +++ b/include/configs/keymile-common.h @@ -68,7 +68,6 @@ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_COMMAND_HISTORY 1 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_HUSH_INIT_VAR 1 diff --git a/include/configs/manroland/common.h b/include/configs/manroland/common.h index c04830b..0224608 100644 --- a/include/configs/manroland/common.h +++ b/include/configs/manroland/common.h @@ -126,7 +126,6 @@ #define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_COMMAND_HISTORY 1 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ /* Enable an alternate, more extensive memory test */ -- cgit v1.1 From ba6adeb48e71f7f1b791b6e98999a5680d919b26 Mon Sep 17 00:00:00 2001 From: Magnus Lilja Date: Fri, 23 Apr 2010 20:30:49 +0200 Subject: i.MX31: Activate NAND support for i.MX31 Litekit board. Signed-off-by: Magnus Lilja --- include/configs/imx31_litekit.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'include/configs') diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h index 6131008..d58ca8a 100644 --- a/include/configs/imx31_litekit.h +++ b/include/configs/imx31_litekit.h @@ -89,6 +89,7 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_SPI #define CONFIG_CMD_DATE +#define CONFIG_CMD_NAND #define CONFIG_BOOTDELAY 3 @@ -174,4 +175,13 @@ #undef CONFIG_CMD_MTDPARTS #define CONFIG_JFFS2_DEV "nor0" +/* + * NAND flash + */ +#define CONFIG_NAND_MXC +#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR +#define CONFIG_MXC_NAND_HWECC + #endif /* __CONFIG_H */ -- cgit v1.1 From dfe5e14fa263eb8f1a9f087f0284788e7559821d Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Fri, 16 Apr 2010 17:11:19 +0200 Subject: MX: RTC13783 uses general function to access PMIC The RTC is part of the Freescale's PMIC controller. Use general function to access to PMIC internal registers. Signed-off-by: Stefano Babic Tested-by: Magnus Lilja --- include/configs/imx31_litekit.h | 9 ++++++--- include/configs/mx31ads.h | 8 +++++--- include/configs/mx31pdk.h | 9 +++++---- 3 files changed, 16 insertions(+), 10 deletions(-) (limited to 'include/configs') diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h index d58ca8a..4904856 100644 --- a/include/configs/imx31_litekit.h +++ b/include/configs/imx31_litekit.h @@ -68,10 +68,13 @@ #define CONFIG_DEFAULT_SPI_BUS 1 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_FSL_PMIC +#define CONFIG_FSL_PMIC_BUS 1 +#define CONFIG_FSL_PMIC_CS 0 +#define CONFIG_FSL_PMIC_CLK 1000000 +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH) + #define CONFIG_RTC_MC13783 1 -/* MC13783 connected to CSPI2 and SS0 */ -#define CONFIG_MC13783_SPI_BUS 1 -#define CONFIG_MC13783_SPI_CS 0 /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h index ec1c905..dedecd7 100644 --- a/include/configs/mx31ads.h +++ b/include/configs/mx31ads.h @@ -65,10 +65,12 @@ #define CONFIG_DEFAULT_SPI_BUS 1 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_FSL_PMIC +#define CONFIG_FSL_PMIC_BUS 1 +#define CONFIG_FSL_PMIC_CS 0 +#define CONFIG_FSL_PMIC_CLK 1000000 +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH) #define CONFIG_RTC_MC13783 1 -/* MC13783 connected to CSPI2 and SS0 */ -#define CONFIG_MC13783_SPI_BUS 1 -#define CONFIG_MC13783_SPI_CS 0 /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index bee2f45..0414cc3 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -69,12 +69,13 @@ #define CONFIG_DEFAULT_SPI_BUS 1 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_FSL_PMIC +#define CONFIG_FSL_PMIC_BUS 1 +#define CONFIG_FSL_PMIC_CS 2 +#define CONFIG_FSL_PMIC_CLK 1000000 +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH) #define CONFIG_RTC_MC13783 1 -/* MC13783 connected to CSPI2 and SS2 */ -#define CONFIG_MC13783_SPI_BUS 1 -#define CONFIG_MC13783_SPI_CS 2 - /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 -- cgit v1.1 From e98ecd71102de9d97bd82be247ed909260fb671b Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Fri, 16 Apr 2010 17:13:54 +0200 Subject: MX31: Add support for PMIC to the QONG module Add support for the PMIC (MC13783) controller and enables charging of the RTC battery. Signed-off-by: Stefano Babic --- include/configs/qong.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'include/configs') diff --git a/include/configs/qong.h b/include/configs/qong.h index 1d63b33..eb4669b 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -54,6 +54,17 @@ #define CONFIG_MX31_GPIO +#define CONFIG_MXC_SPI +#define CONFIG_DEFAULT_SPI_BUS 1 +#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_RTC_MC13783 + +#define CONFIG_FSL_PMIC +#define CONFIG_FSL_PMIC_BUS 1 +#define CONFIG_FSL_PMIC_CS 0 +#define CONFIG_FSL_PMIC_CLK 100000 +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH) + /* FPGA */ #define CONFIG_QONG_FPGA 1 #define CONFIG_FPGA_BASE (CS1_BASE) @@ -98,6 +109,9 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_MII #define CONFIG_CMD_NAND +#define CONFIG_CMD_SPI +#define CONFIG_CMD_DATE +#define BOARD_LATE_INIT /* * You can compile in a MAC address and your custom net settings by using -- cgit v1.1 From b4377e12e9aa0b3bf2dcae0a0f02ec9086338506 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Tue, 16 Mar 2010 17:22:21 +0100 Subject: Add SPI support to mx51evk board The patch adds SPI devices to the mx51evk board. The MC13892 chip (PMIC) is supported. Signed-off-by: Stefano Babic --- include/configs/mx51evk.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'include/configs') diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 3626df7..86a4731 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -54,6 +54,8 @@ /* size in bytes reserved for initial data */ #define CONFIG_SYS_GBL_DATA_SIZE 128 +#define BOARD_LATE_INIT + /* * Hardware drivers */ @@ -61,6 +63,19 @@ #define CONFIG_SYS_MX51_UART1 /* + * SPI Configs + * */ +#define CONFIG_CMD_SPI + +#define CONFIG_MXC_SPI + +#define CONFIG_FSL_PMIC +#define CONFIG_FSL_PMIC_BUS 0 +#define CONFIG_FSL_PMIC_CS 0 +#define CONFIG_FSL_PMIC_CLK 2500000 +#define CONFIG_FSL_PMIC_MODE (SPI_CPOL | SPI_CS_HIGH) + +/* * MMC Configs * */ #define CONFIG_FSL_ESDHC -- cgit v1.1 From bf16500f79fdf2653a286b40bb601cb185ac4675 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sat, 24 Apr 2010 00:05:47 +1000 Subject: x86: Use CONFIG_SERIAL_MULTI Signed-off-by: Graeme Russ --- include/configs/eNET.h | 26 +++++++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-) (limited to 'include/configs') diff --git a/include/configs/eNET.h b/include/configs/eNET.h index 6a68bf4..05d7db8 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -21,6 +21,7 @@ * MA 02111-1307 USA */ +#include /* * board/config.h - configuration options, board specific */ @@ -55,6 +56,26 @@ #undef CONFIG_HW_WATCHDOG /*----------------------------------------------------------------------- + * Serial Configuration + */ +#define CONFIG_SERIAL_MULTI +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK 1843200 +#define CONFIG_BAUDRATE 9600 +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CONFIG_SYS_NS16550_COM1 UART0_BASE +#define CONFIG_SYS_NS16550_COM2 UART1_BASE +#define CONFIG_SYS_NS16550_COM3 (0x1000 + UART0_BASE) +#define CONFIG_SYS_NS16550_COM4 (0x1000 + UART1_BASE) +#define CONFIG_SYS_NS16550_PORT_MAPPED + + /*----------------------------------------------------------------------- * Video Configuration */ #undef CONFIG_VIDEO /* No Video Hardware */ @@ -65,8 +86,6 @@ */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) -#define CONFIG_BAUDRATE 9600 - /*----------------------------------------------------------------------- * Command line configuration. */ @@ -123,9 +142,6 @@ #define CONFIG_SYS_HZ 1024 /* incrementer freq: 1kHz */ - /* valid baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - /*----------------------------------------------------------------------- * SDRAM Configuration */ -- cgit v1.1 From 6fd445c32860bb06e9a68b516845a1bbf7c37889 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sat, 24 Apr 2010 00:05:51 +1000 Subject: eNET: Fix Flash Write Onboard AMD Flash chip does not support buffered writes Signed-off-by: Graeme Russ --- include/configs/eNET.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/eNET.h b/include/configs/eNET.h index 05d7db8..f643f7f 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -198,7 +198,7 @@ CONFIG_SYS_FLASH_BASE_1, \ CONFIG_SYS_FLASH_BASE_2} #define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT #define CONFIG_SYS_FLASH_LEGACY_512Kx8 -- cgit v1.1 From 4f197c30e5cb3005909402b7fc630cb092eef02f Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sat, 24 Apr 2010 00:05:52 +1000 Subject: eNET: Fix CONFIG_SYS_HZ to be 1000 The clock interupt has always been 1kHz as per timer_init() in /arch/i386/cpu/sc520/sc520_timer.c Signed-off-by: Graeme Russ --- include/configs/eNET.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/eNET.h b/include/configs/eNET.h index f643f7f..0bfbd08 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -140,7 +140,7 @@ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_HZ 1024 /* incrementer freq: 1kHz */ +#define CONFIG_SYS_HZ 1000 /* incrementer freq: 1kHz */ /*----------------------------------------------------------------------- * SDRAM Configuration -- cgit v1.1 From 8fd805632f95e5e834f312a51aa969bf1d99c41b Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sat, 24 Apr 2010 00:05:55 +1000 Subject: eNET: Add support for onboard RTL8100B (RTL8139) chips Signed-off-by: Graeme Russ --- include/configs/eNET.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/eNET.h b/include/configs/eNET.h index 0bfbd08..dac3ede 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -105,9 +105,10 @@ #define CONFIG_CMD_LOADS /* loads */ #define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ #define CONFIG_CMD_MISC /* Misc functions like sleep etc*/ -#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ #undef CONFIG_CMD_NFS /* NFS support */ #define CONFIG_CMD_PCI /* PCI support */ +#define CONFIG_CMD_PING /* ICMP echo support */ #define CONFIG_CMD_RUN /* run command in env variable */ #define CONFIG_CMD_SAVEENV /* saveenv */ #define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */ @@ -226,6 +227,12 @@ #define CONFIG_SYS_THIRD_PCI_IRQ 11 #define CONFIG_SYS_FORTH_PCI_IRQ 15 + /* + * Network device (TRL8100B) support + */ +#define CONFIG_NET_MULTI +#define CONFIG_RTL8139 + /*----------------------------------------------------------------------- * Hardware watchdog configuration */ -- cgit v1.1 From f2a55055e9b19f3eba9de97ff454cf8bfef25468 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sat, 24 Apr 2010 00:05:57 +1000 Subject: eNET: Use SC520 MMCR to reset eNET board Signed-off-by: Graeme Russ --- include/configs/eNET.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/eNET.h b/include/configs/eNET.h index dac3ede..6189794 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -160,7 +160,7 @@ * CPU Features */ #define CONFIG_SYS_SC520_HIGH_SPEED 0 /* 100 or 133MHz */ -#undef CONFIG_SYS_SC520_RESET /* use SC520 MMCR's to reset cpu */ +#define CONFIG_SYS_SC520_RESET /* use SC520 MMCR's to reset cpu */ #define CONFIG_SYS_SC520_TIMER /* use SC520 swtimers */ #undef CONFIG_SYS_GENERIC_TIMER /* use the i8254 PIT timers */ #undef CONFIG_SYS_TSC_TIMER /* use the Pentium TSC timers */ -- cgit v1.1 From 880c59e5add3681bd4dca14d2fd20152bee7ad14 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sat, 24 Apr 2010 00:05:58 +1000 Subject: eNET: Implement eNET Watchdog Signed-off-by: Graeme Russ --- include/configs/eNET.h | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) (limited to 'include/configs') diff --git a/include/configs/eNET.h b/include/configs/eNET.h index 6189794..361fe61 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -53,7 +53,7 @@ * bottom (processor) board MUST be removed! */ #undef CONFIG_WATCHDOG -#undef CONFIG_HW_WATCHDOG +#define CONFIG_HW_WATCHDOG /*----------------------------------------------------------------------- * Serial Configuration @@ -234,14 +234,6 @@ #define CONFIG_RTL8139 /*----------------------------------------------------------------------- - * Hardware watchdog configuration - */ -#define CONFIG_SYS_WATCHDOG_PIO_BIT 0x8000 -#define CONFIG_SYS_WATCHDIG_PIO_DATA SC520_PIODATA15_0 -#define CONFIG_SYS_WATCHDIG_PIO_CLR SC520_PIOCLR15_0 -#define CONFIG_SYS_WATCHDIG_PIO_SET SC520_PIOSET15_0 - -/*----------------------------------------------------------------------- * FPGA configuration */ #define CONFIG_SYS_FPGA_PROGRAM_PIO_BIT 0x2000 -- cgit v1.1 From 0738e24e2c1d95bb94455d44485dc5d7b9c9d707 Mon Sep 17 00:00:00 2001 From: Reinhard Arlt Date: Tue, 13 Apr 2010 09:59:09 +0200 Subject: 74xx_7xx: CPCI750: Add ECC support on esd CPCI-CPU/750 board Add ECC support for DDR RAM for MV64360 on esd CPCI-CPU/750 board. This patch also adds the "pldver" command to display the CPLD revision. Signed-off-by: Reinhard Arlt Signed-off-by: Stefan Roese --- include/configs/CPCI750.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h index d516c3c..1c8c68b 100644 --- a/include/configs/CPCI750.h +++ b/include/configs/CPCI750.h @@ -59,7 +59,7 @@ #define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 */ -#undef CONFIG_ECC /* enable ECC support */ +#define CONFIG_MV64360_ECC /* enable ECC support */ #define CONFIG_HIGH_BATS 1 /* High BATs supported */ @@ -628,5 +628,7 @@ #define CONFIG_SYS_BOARD_ASM_INIT 1 #define CPCI750_SLAVE_TEST (((in8(0xf0300000) & 0x80) == 0) ? 0 : 1) +#define CPCI750_ECC_TEST (((in8(0xf0300000) & 0x02) == 0) ? 1 : 0) +#define CONFIG_SYS_PLD_VER 0xf0e00000 #endif /* __CONFIG_H */ -- cgit v1.1 From 3b439792b0781921c599d8af9bed6a771d295b53 Mon Sep 17 00:00:00 2001 From: Ron Madrid Date: Wed, 28 Apr 2010 16:04:43 -0700 Subject: mpc83xx: Add UPMA configuration to SIMPC8313 Added UPM array table, upmconfig, and Local Bus configuration support for SIMPC8313 Signed-off-by: Ron Madrid Signed-off-by: Kim Phillips --- include/configs/SIMPC8313.h | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'include/configs') diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h index 84af8df..1a17323 100644 --- a/include/configs/SIMPC8313.h +++ b/include/configs/SIMPC8313.h @@ -126,6 +126,7 @@ #else #define CONFIG_SYS_NAND_BASE 0xE2800000 #endif +#define CONFIG_SYS_FPGA_BASE 0xFF000000 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define NAND_MAX_CHIPS 1 @@ -184,6 +185,16 @@ #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR0_PRELIM +#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_FPGA_BASE \ + | BR_PS_16 \ + | BR_MS_UPMA \ + | BR_V ) +#define CONFIG_SYS_OR1_PRELIM ( OR_AM_2MB \ + | OR_UPM_BCTLD) + +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_2MB) + /* * JFFS2 configuration */ -- cgit v1.1 From fd194f82d1c30802f0597a3e359fdc03ed397367 Mon Sep 17 00:00:00 2001 From: Andre Schwarz Date: Mon, 3 May 2010 13:22:31 +0200 Subject: mpc83xx/mvBLM7: add usb commands and cleanup. Add USB commands. Rename autoscript to bootscript. Add automatic bootscript image generation to makefile. Signed-off-by: Andre Schwarz Signed-off-by: Kim Phillips --- include/configs/MVBLM7.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include/configs') diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index 26897c6..c28eb64 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -234,7 +234,11 @@ #define CONFIG_BOOTP_SEND_HOSTNAME /* USB */ +#define CONFIG_SYS_USB_HOST +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL #define CONFIG_HAS_FSL_DR_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* * Environment @@ -267,6 +271,8 @@ #define CONFIG_CMD_PCI #define CONFIG_CMD_I2C #define CONFIG_CMD_FPGA +#define CONFIG_CMD_USB +#define CONFIG_DOS_PARTITION #undef CONFIG_WATCHDOG -- cgit v1.1 From b1e1a42bb1ea2f0ddaaea7f4c9d67c98ab38709e Mon Sep 17 00:00:00 2001 From: Ron Madrid Date: Fri, 14 May 2010 16:27:48 -0700 Subject: Fix SICRL setting in SIMPC8313 This patch sets the SICRL_LBC bits in SICRL to change the function of the associated pins to GPIO functionality. Signed-off-by: Ron Madrid --- include/configs/SIMPC8313.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h index 1a17323..9104f1a 100644 --- a/include/configs/SIMPC8313.h +++ b/include/configs/SIMPC8313.h @@ -418,7 +418,8 @@ | SICRH_ETSEC2_G \ | SICRH_TSOBI1 \ | SICRH_TSOBI2 ) -#define CONFIG_SYS_SICRL (SICRL_USBDR \ +#define CONFIG_SYS_SICRL ( SICRL_LBC \ + | SICRL_USBDR \ | SICRL_ETSEC2_A ) #define CONFIG_SYS_HID0_INIT 0x000000000 -- cgit v1.1 From 03af5abd85637d27e96fb999ce6e3992293570b0 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Thu, 13 May 2010 10:26:40 +0200 Subject: MX31: Added support for the Casio COM57H5M10XRC to QONG The patch adds setup to connect a CASIO COM57H5M10XRC (640x480 TFT display) to the QONG module. Signed-off-by: Stefano Babic --- include/configs/qong.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/qong.h b/include/configs/qong.h index eb4669b..100fa3f 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -84,7 +84,7 @@ #define CONFIG_SPLASH_SCREEN #define CONFIG_CMD_BMP #define CONFIG_BMP_16BPP -#define CONFIG_DISPLAY_VBEST_VGG322403 +#define CONFIG_DISPLAY_COM57H5M10XRC /* * Reducing the ARP timeout from default 5 seconds to 200ms we speed up the -- cgit v1.1