From 5f723a3b98c630bde33de74351f2121691fdef14 Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Fri, 20 Jun 2008 10:41:05 +0200 Subject: avr32: Enable SPI flash support on ATNGW100 The ATNGW100 has 8MB DataFlash on board. Give users access to it through the new SPI flash framework. Signed-off-by: Haavard Skinnemoen --- include/configs/atngw100.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include/configs') diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h index 3fc9975..7ac51b5 100644 --- a/include/configs/atngw100.h +++ b/include/configs/atngw100.h @@ -114,6 +114,8 @@ #define CONFIG_CMD_FAT #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_MMC +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI #undef CONFIG_CMD_AUTOSCRIPT #undef CONFIG_CMD_FPGA @@ -126,6 +128,10 @@ #define CFG_NR_PIOS 5 #define CFG_HSDRAMC 1 #define CONFIG_MMC 1 +#define CONFIG_ATMEL_SPI 1 + +#define CONFIG_SPI_FLASH 1 +#define CONFIG_SPI_FLASH_ATMEL 1 #define CFG_DCACHE_LINESZ 32 #define CFG_ICACHE_LINESZ 32 -- cgit v1.1 From 6a19c46cae43c16c528eddefae3db97134f1915d Mon Sep 17 00:00:00 2001 From: Andre Schwarz Date: Mon, 23 Jun 2008 13:25:34 +0200 Subject: fix non-working mvBL-M7 Add missing #define CONFIG_HIGH_BATS in mvBL-M7 board config file. Signed-off-by: Andre Schwarz Signed-off-by: Kim Phillips --- include/configs/MVBLM7.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/configs') diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index 349ca14..021b72d 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -336,6 +336,7 @@ #define CFG_HID0_FINAL CFG_HID0_INIT #define CFG_HID2 HID2_HBE +#define CONFIG_HIGH_BATS 1 /* DDR */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -- cgit v1.1 From c7f879ec2b389c4f2bf726b293bd516f4c692e03 Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Wed, 21 May 2008 13:58:41 -0400 Subject: ARM: Add support for Lyrtech SFF-SDR board (ARM926EJS) This patch adds support for the Lyrtech SFF-SDR board, based on the TI DaVinci architecture (ARM926EJS). Signed-off-by: Hugo Villeneuve Signed-off-by: Philip Balister Signed-off-by: Wolfgang Denk --- include/configs/davinci_sffsdr.h | 177 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 177 insertions(+) create mode 100644 include/configs/davinci_sffsdr.h (limited to 'include/configs') diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h new file mode 100644 index 0000000..41a6763 --- /dev/null +++ b/include/configs/davinci_sffsdr.h @@ -0,0 +1,177 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +#include + +/*=======*/ +/* Board */ +/*=======*/ +#define SFFSDR +#define CFG_NAND_LARGEPAGE +#define CFG_USE_NAND +/*===================*/ +/* SoC Configuration */ +/*===================*/ +#define CONFIG_ARM926EJS /* arm926ejs CPU core */ +#define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */ +#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */ +#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */ +#define CFG_HZ 1000 +/*==================================================*/ +/* EEPROM definitions for Atmel 24LC64 EEPROM chip */ +/*==================================================*/ +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_I2C_EEPROM_ADDR 0x50 +#define CFG_EEPROM_PAGE_WRITE_BITS 5 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 +/*=============*/ +/* Memory Info */ +/*=============*/ +#define CFG_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */ +#define CFG_GBL_DATA_SIZE 128 /* reserved for initial data */ +#define CFG_MEMTEST_START 0x80000000 /* memtest start address */ +#define CFG_MEMTEST_END 0x81000000 /* 16MB RAM test */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define CONFIG_STACKSIZE (256*1024) /* regular stack */ +#define PHYS_SDRAM_1 0x80000000 /* DDR Start */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ +#define DDR_4BANKS /* 4-bank DDR2 (128MB) */ +/*====================*/ +/* Serial Driver info */ +/*====================*/ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 4 /* NS16550 register size */ +#define CFG_NS16550_COM1 0x01c20000 /* Base address of UART0 */ +#define CFG_NS16550_CLK 27000000 /* Input clock to NS16550 */ +#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +/*===================*/ +/* I2C Configuration */ +/*===================*/ +#define CONFIG_HARD_I2C +#define CONFIG_DRIVER_DAVINCI_I2C +#define CFG_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ +#define CFG_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ +/*==================================*/ +/* Network & Ethernet Configuration */ +/*==================================*/ +#define CONFIG_DRIVER_TI_EMAC +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_OVERWRITE_ETHADDR_ONCE +/*=====================*/ +/* Flash & Environment */ +/*=====================*/ +#undef CFG_ENV_IS_IN_FLASH +#define CFG_NO_FLASH +#define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ +#define CFG_ENV_SECT_SIZE 2048 /* Env sector Size */ +#define CFG_ENV_SIZE SZ_128K +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ +#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ +#define CFG_NAND_BASE 0x02000000 +#define CFG_NAND_HW_ECC +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_MAX_CHIPS 1 +#define CFG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ +/*=====================*/ +/* Board related stuff */ +/*=====================*/ +/*==========================================*/ +/* I2C switch definitions for PCA9543 chip */ +/* on Lyrtech SFF SDR board. */ +/* This chip has a single register. */ +/*==========================================*/ +#define CFG_I2C_PCA9543_ADDR 0x70 +#define CFG_I2C_PCA9543_ADDR_LEN 0 +#define CFG_I2C_PCA9543_ENABLE_CH0 0x01 /* Enable channel 0. */ +/*==============================*/ +/* U-Boot general configuration */ +/*==============================*/ +#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ +#define CONFIG_MISC_INIT_R +#undef CONFIG_BOOTDELAY +#define CONFIG_BOOTFILE "uImage" /* Boot file name */ +#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +/* Print buffer size */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x80700000 /* Default Linux kernel + * load address. */ +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, + * may be later */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING +#define CFG_LONGHELP +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC +/* + * Define this to load an Integrity kernel. + * +#define CONFIG_CMD_ELF + */ + +/*===================*/ +/* Linux Information */ +/*===================*/ +#define LINUX_BOOT_PARAM_ADDR 0x80000100 +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTARGS \ + "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp" +#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot" + +/*=================*/ +/* U-Boot commands */ +/*=================*/ +#include +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_NAND +#define CONFIG_CMD_EEPROM +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_IMLS +/*=======================*/ +/* KGDB support (if any) */ +/*=======================*/ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ -- cgit v1.1 From e093a247628228100f405b6d7f6b1bfc16141938 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sat, 28 Jun 2008 23:34:37 +0200 Subject: Coding Style Cleanup Signed-off-by: Wolfgang Denk --- include/configs/MVBLM7.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index 349ca14..0b238bd 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -262,7 +262,7 @@ #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SIZE) #define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE -#define CONFIG_LOADS_ECHO +#define CONFIG_LOADS_ECHO #define CFG_LOADS_BAUD_CHANGE /* -- cgit v1.1 From f8cc312bbee69257d741dc9f4062f4a0f5adf609 Mon Sep 17 00:00:00 2001 From: Ben Warren Date: Sun, 8 Jun 2008 23:28:33 -0700 Subject: Move conditional compilation of MPC8XXX SPI driver to Makefile Signed-off-by: Ben Warren --- include/configs/MPC8349EMDS.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 37e3ca4..8705838 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -355,7 +355,6 @@ /* SPI */ #define CONFIG_MPC8XXX_SPI -#define CONFIG_HARD_SPI /* SPI with hardware support */ #undef CONFIG_SOFT_SPI /* SPI bit-banged */ /* GPIOs. Used as SPI chip selects */ -- cgit v1.1 From ced209c50e80c25f13c083099b05044048d21f4f Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Thu, 3 Jul 2008 22:39:21 +0200 Subject: sacsng board: fix warnings "suggest explicit braces to avoid ambiguous 'else'" Signed-off-by: Wolfgang Denk --- include/configs/sacsng.h | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'include/configs') diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h index 4974fb4..2a398e8 100644 --- a/include/configs/sacsng.h +++ b/include/configs/sacsng.h @@ -272,10 +272,14 @@ #undef SPI_INIT /* no port initialization needed */ #define SPI_READ ((immr->im_ioport.iop_pdatd & I2C_MISO) != 0) -#define SPI_SDA(bit) if(bit) immr->im_ioport.iop_pdatd |= I2C_MOSI; \ - else immr->im_ioport.iop_pdatd &= ~I2C_MOSI -#define SPI_SCL(bit) if(bit) immr->im_ioport.iop_pdatd |= I2C_SCLK; \ - else immr->im_ioport.iop_pdatd &= ~I2C_SCLK +#define SPI_SDA(bit) do { \ + if(bit) immr->im_ioport.iop_pdatd |= I2C_MOSI; \ + else immr->im_ioport.iop_pdatd &= ~I2C_MOSI; \ + } while (0) +#define SPI_SCL(bit) do { \ + if(bit) immr->im_ioport.iop_pdatd |= I2C_SCLK; \ + else immr->im_ioport.iop_pdatd &= ~I2C_SCLK; \ + } while (0) #define SPI_DELAY /* No delay is needed */ #endif /* CONFIG_SOFT_SPI */ -- cgit v1.1 From f16ed51702cb9fb6fa2e019bbc0fcd1466b57c3b Mon Sep 17 00:00:00 2001 From: Andre Schwarz Date: Wed, 2 Jul 2008 18:54:08 +0200 Subject: update mvBL-M7 board config update mvBL-M7 config file to use UBOOT_VERSION. Signed-off-by: Andre Schwarz Signed-off-by: Kim Phillips --- include/configs/MVBLM7.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include/configs') diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index 021b72d..50e188f 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -27,7 +27,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define MV_VERSION "v1.0.1" +#include /* * High Level Configuration Options @@ -447,7 +447,7 @@ "mv_dtb_addr=" MV_DTB_ADDR "\0" \ "mv_dtb_addr_ram=" MV_DTB_ADDR_RAM "\0" \ "dtb_name=" MV_DTB_NAME "\0" \ - "mv_version=" MV_VERSION "\0" \ + "mv_version=" U_BOOT_VERSION "\0" \ "dhcp_client_id=" MV_CI "\0" \ "dhcp_vendor-class-identifier=" MV_VCI "\0" \ "netretry=no\0" \ -- cgit v1.1 From 9fea65a6c469b1b474b27446feb58738baba2d31 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 24 Jun 2008 09:54:09 +0200 Subject: ppc4xx: Rename CONFIG_XILINX_ML300 to CONFIG_XILINX_405 This change helps with better handling with others Xilinx based platform. Signed-off-by: Michal Simek Acked-by: Stefan Roese --- include/configs/ml300.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/configs') diff --git a/include/configs/ml300.h b/include/configs/ml300.h index 1945918..319923a 100644 --- a/include/configs/ml300.h +++ b/include/configs/ml300.h @@ -54,6 +54,7 @@ #define CONFIG_405 1 /* This is a PPC405 CPU */ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_XILINX_405 1 #define CONFIG_XILINX_ML300 1 /* ...on a Xilinx ML300 board */ #define CONFIG_SYSTEMACE 1 -- cgit v1.1 From f9599eca7cb5ebe40e5305c8006dced6ecc5cd9e Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 17 Jun 2008 16:27:52 +0900 Subject: sh: Update Hitachi MS7722SE board Remove network setting from config file. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- include/configs/ms7722se.h | 4 ---- 1 file changed, 4 deletions(-) (limited to 'include/configs') diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h index 8d92a13..7298e55 100644 --- a/include/configs/ms7722se.h +++ b/include/configs/ms7722se.h @@ -40,10 +40,6 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01" -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.0.22 -#define CONFIG_SERVERIP 192.168.0.1 -#define CONFIG_GATEWAYIP 192.168.0.1 #define CONFIG_VERSION_VARIABLE #undef CONFIG_SHOW_BOOT_PROGRESS -- cgit v1.1 From c001cd604e9f133743effbddb1c215b48e761c5a Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 17 Jun 2008 16:27:56 +0900 Subject: sh: Update Renesas Migo-R board Remove network setting from config file. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- include/configs/MigoR.h | 4 ---- 1 file changed, 4 deletions(-) (limited to 'include/configs') diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h index 99e1179..fa0e5db 100644 --- a/include/configs/MigoR.h +++ b/include/configs/MigoR.h @@ -45,10 +45,6 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01" -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.10.100 -#define CONFIG_SERVERIP 192.168.10.77 -#define CONFIG_GATEWAYIP 192.168.10.77 #define CONFIG_VERSION_VARIABLE #undef CONFIG_SHOW_BOOT_PROGRESS -- cgit v1.1 From ec39d479d2003f15e86e23ebc4e02a1c9a3a181c Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 17 Jun 2008 16:28:01 +0900 Subject: sh: Update Renesas R7780MP board New NOR Flash board support and remove network setting from config file. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- include/configs/r7780mp.h | 41 +++++++++++++++++++++++------------------ 1 file changed, 23 insertions(+), 18 deletions(-) (limited to 'include/configs') diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h index 4e89580..4c82c5a 100644 --- a/include/configs/r7780mp.h +++ b/include/configs/r7780mp.h @@ -1,7 +1,7 @@ /* * Configuation settings for the Renesas R7780MP board * - * Copyright (C) 2007 Nobuhiro Iwamatsu + * Copyright (C) 2007,2008 Nobuhiro Iwamatsu * Copyright (C) 2008 Yusuke Goda * * See file CREDITS for list of people who contributed to this @@ -31,7 +31,8 @@ #define CONFIG_SH4A 1 #define CONFIG_CPU_SH7780 1 #define CONFIG_R7780MP 1 -#define __LITTLE_ENDIAN 1 +#define CFG_R7780MP_OLD_FLASH 1 +#define __LITTLE_ENDIAN__ 1 /* * Command line configuration. @@ -59,12 +60,6 @@ /* check for keypress on bootdelay==0 */ /*#define CONFIG_ZERO_BOOTDELAY_CHECK*/ -/* Network setting */ -#define CONFIG_NETMASK 255.0.0.0 -#define CONFIG_IPADDR 10.0.192.82 -#define CONFIG_SERVERIP 10.0.0.1 -#define CONFIG_GATEWAYIP 10.0.0.1 - #define CFG_SDRAM_BASE (0x08000000) #define CFG_SDRAM_SIZE (128 * 1024 * 1024) @@ -80,22 +75,30 @@ #define CFG_MEMTEST_START (CFG_SDRAM_BASE) #define CFG_MEMTEST_END (TEXT_BASE - 0x100000) -/* NOR Flash (S29PL127J60TFI130) */ +/* Flash board support */ #define CFG_FLASH_BASE (0xA0000000) -#define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT -#define CFG_MAX_FLASH_BANKS (2) -#define CFG_MAX_FLASH_SECT 270 -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE,\ +#ifdef CFG_R7780MP_OLD_FLASH +/* NOR Flash (S29PL127J60TFI130) */ +# define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT +# define CFG_MAX_FLASH_BANKS (2) +# define CFG_MAX_FLASH_SECT 270 +# define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE,\ CFG_FLASH_BASE + 0x100000,\ CFG_FLASH_BASE + 0x400000,\ CFG_FLASH_BASE + 0x700000, } +#else /* CFG_R7780MP_OLD_FLASH */ +/* NOR Flash (Spantion S29GL256P) */ +# define CFG_MAX_FLASH_BANKS (1) +# define CFG_MAX_FLASH_SECT 256 +# define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#endif /* CFG_R7780MP_OLD_FLASH */ #define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 4 * 1024 * 1024) /* Address of u-boot image in Flash */ #define CFG_MONITOR_BASE (CFG_FLASH_BASE) -#define CFG_MONITOR_LEN (112 * 1024) +#define CFG_MONITOR_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */ -#define CFG_MALLOC_LEN (256 * 1024) +#define CFG_MALLOC_LEN (1204 * 1024) /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_SIZE (256) @@ -110,7 +113,7 @@ #define CFG_FLASH_EMPTY_INFO #define CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE (16 * 1024) +#define CFG_ENV_SECT_SIZE (256 * 1024) #define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE) #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) #define CFG_FLASH_ERASE_TOUT 120000 @@ -141,8 +144,10 @@ #endif /* CONFIG_CMD_PCI */ #if defined(CONFIG_CMD_NET) -/* #define CONFIG_NET_MULTI - #define CONFIG_RTL8169 */ +/* +#define CONFIG_NET_MULTI +#define CONFIG_RTL8169 +*/ /* AX88696L Support(NE2000 base chip) */ #define CONFIG_DRIVER_NE2000 #define CONFIG_DRIVER_AX88796L -- cgit v1.1 From 873d97aabc0b1c8822ed1d87e8c5c8ae0a7e4ae9 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 17 Jun 2008 16:28:05 +0900 Subject: sh: Update Renesas R2DPlus board New NOR Flash board support and remove old type flash board config. And Remove network setting from config file. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- include/configs/r2dplus.h | 42 +++++++++--------------------------------- 1 file changed, 9 insertions(+), 33 deletions(-) (limited to 'include/configs') diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h index c20baca..e269336 100644 --- a/include/configs/r2dplus.h +++ b/include/configs/r2dplus.h @@ -35,12 +35,6 @@ #define CONFIG_BOOTARGS "console=ttySC0,115200" #define CONFIG_ENV_OVERWRITE 1 -/* Network setting */ -#define CONFIG_NETMASK 255.0.0.0 -#define CONFIG_IPADDR 10.0.192.51 -#define CONFIG_SERVERIP 10.0.0.1 -#define CONFIG_GATEWAYIP 10.0.0.1 - /* SDRAM */ #define CFG_SDRAM_BASE (0x8C000000) #define CFG_SDRAM_SIZE (0x04000000) @@ -60,45 +54,27 @@ #define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 32 * 1024 * 1024) /* Address of u-boot image in Flash */ #define CFG_MONITOR_BASE (CFG_FLASH_BASE) -#define CFG_MONITOR_LEN (128 * 1024) +#define CFG_MONITOR_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */ -#define CFG_MALLOC_LEN (256 * 1024) +#define CFG_MALLOC_LEN (1024 * 1024) /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_SIZE (256) #define CFG_BOOTMAPSZ (8 * 1024 * 1024) /* - * NOR Flash + * NOR Flash ( Spantion S29GL256P ) */ #define CFG_FLASH_CFI #define CFG_FLASH_CFI_DRIVER - -#if defined(CONFIG_R2DPLUS_OLD) -#define CFG_FLASH_BASE (0xA0000000) -#define CFG_MAX_FLASH_BANKS (1) /* Max number of - * Flash memory banks - */ -#define CFG_MAX_FLASH_SECT 142 -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } - -#else /* CONFIG_R2DPLUS_OLD */ - #define CFG_FLASH_BASE (0xA0000000) -#define CFG_FLASH_CFI_WIDTH 0x04 /* 32bit */ -#define CFG_MAX_FLASH_BANKS (2) -#define CFG_MAX_FLASH_SECT 270 -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE,\ - CFG_FLASH_BASE + 0x100000,\ - CFG_FLASH_BASE + 0x400000,\ - CFG_FLASH_BASE + 0x700000, } -#endif /* CONFIG_R2DPLUS_OLD */ +#define CFG_MAX_FLASH_BANKS (1) +#define CFG_MAX_FLASH_SECT 256 +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } #define CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x20000 -#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE) -#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) -#define CFG_FLASH_ERASE_TOUT 120000 -#define CFG_FLASH_WRITE_TOUT 500 +#define CFG_ENV_SECT_SIZE 0x40000 +#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE) +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) /* * SuperH Clock setting -- cgit v1.1 From 689c1b30caacba3fbca0b1813facb3ab70b6cd63 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Mon, 7 Jul 2008 11:22:37 +0900 Subject: sh: Fix compile error sh7763rdp board Disable SH ether driver. Signed-off-by: Nobuhiro Iwamatsu --- include/configs/sh7763rdp.h | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'include/configs') diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h index d537071..7713eaa 100644 --- a/include/configs/sh7763rdp.h +++ b/include/configs/sh7763rdp.h @@ -38,11 +38,7 @@ #define CONFIG_CMD_SDRAM #define CONFIG_CMD_FLASH #define CONFIG_CMD_MEMORY -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING #define CONFIG_CMD_ENV -#define CONFIG_CMD_NFS -#define CONFIG_CMD_JFFS2 #define CONFIG_BOOTDELAY -1 #define CONFIG_BOOTARGS "console=ttySC2,115200 root=1f01" @@ -66,12 +62,6 @@ #define CFG_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */ -/* Ethernet */ -#define CONFIG_SH_ETHER 1 -#define CONFIG_SH_ETHER_USE_PORT (1) -#define CONFIG_SH_ETHER_PHY_ADDR (0x01) -#define CFG_RX_ETH_BUFFER (8) - /* SDRAM */ #define CFG_SDRAM_BASE (0x8C000000) #define CFG_SDRAM_SIZE (64 * 1024 * 1024) -- cgit v1.1 From 0e6989b9faf1588e8723535539e88a0df3c71356 Mon Sep 17 00:00:00 2001 From: Matvejchikov Ilya Date: Sun, 6 Jul 2008 13:57:00 +0400 Subject: FDT memory and pci node fixes for MPC8260ADS Signed-off-by: Matvejchikov Ilya --- include/configs/MPC8260ADS.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'include/configs') diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h index 23508f9..59d0bdb 100644 --- a/include/configs/MPC8260ADS.h +++ b/include/configs/MPC8260ADS.h @@ -197,6 +197,13 @@ #define CONFIG_BAUDRATE 115200 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#if defined(CONFIG_OF_LIBFDT) +#define OF_CPU "cpu@0" +#define OF_TBCLK (bd->bi_busfreq / 4) +#endif + /* * BOOTP options */ -- cgit v1.1 From d2d54ea449639f3d1a6007e333ab9fcc609a18f0 Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Thu, 12 Jun 2008 19:27:57 +0200 Subject: avr32: Use CONFIG_ATMEL_MCI to select the atmel_mci driver After we move the atmel_mci driver into drivers/mmc, we can't select it with CONFIG_MMC anymore. Introduce a new symbol specifically for this driver so that there's no ambiguity. Signed-off-by: Haavard Skinnemoen Acked-by: Jean-Chritophe PLAGNIOL-VILLARD --- include/configs/atngw100.h | 1 + include/configs/atstk1002.h | 1 + include/configs/atstk1003.h | 1 + include/configs/atstk1004.h | 1 + include/configs/atstk1006.h | 1 + 5 files changed, 5 insertions(+) (limited to 'include/configs') diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h index 7ac51b5..84d235e 100644 --- a/include/configs/atngw100.h +++ b/include/configs/atngw100.h @@ -128,6 +128,7 @@ #define CFG_NR_PIOS 5 #define CFG_HSDRAMC 1 #define CONFIG_MMC 1 +#define CONFIG_ATMEL_MCI 1 #define CONFIG_ATMEL_SPI 1 #define CONFIG_SPI_FLASH 1 diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index ba18eb6..90910bb 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -153,6 +153,7 @@ #define CFG_NR_PIOS 5 #define CFG_HSDRAMC 1 #define CONFIG_MMC 1 +#define CONFIG_ATMEL_MCI 1 #define CFG_DCACHE_LINESZ 32 #define CFG_ICACHE_LINESZ 32 diff --git a/include/configs/atstk1003.h b/include/configs/atstk1003.h index a528ddf..03472a8 100644 --- a/include/configs/atstk1003.h +++ b/include/configs/atstk1003.h @@ -136,6 +136,7 @@ #define CONFIG_PIO2 1 #define CFG_HSDRAMC 1 #define CONFIG_MMC 1 +#define CONFIG_ATMEL_MCI 1 #define CFG_DCACHE_LINESZ 32 #define CFG_ICACHE_LINESZ 32 diff --git a/include/configs/atstk1004.h b/include/configs/atstk1004.h index fc9585e..07add82 100644 --- a/include/configs/atstk1004.h +++ b/include/configs/atstk1004.h @@ -136,6 +136,7 @@ #define CONFIG_PIO2 1 #define CFG_HSDRAMC 1 #define CONFIG_MMC 1 +#define CONFIG_ATMEL_MCI 1 #define CFG_DCACHE_LINESZ 32 #define CFG_ICACHE_LINESZ 32 diff --git a/include/configs/atstk1006.h b/include/configs/atstk1006.h index 9fd49a5..f9af675 100644 --- a/include/configs/atstk1006.h +++ b/include/configs/atstk1006.h @@ -153,6 +153,7 @@ #define CFG_NR_PIOS 5 #define CFG_HSDRAMC 1 #define CONFIG_MMC 1 +#define CONFIG_ATMEL_MCI 1 #define CFG_DCACHE_LINESZ 32 #define CFG_ICACHE_LINESZ 32 -- cgit v1.1 From 2b1fa9d383cbbb7d347c1583bd6ca4e181ba8e9e Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Tue, 8 Jul 2008 11:02:05 -0400 Subject: ARM: Fix for wrong patch version applied for Lyrtech SFF-SDR board (ARM926EJS) ARM: Fix for incorrect version of patch applied when adding support for the Lyrtech SFF-SDR board. Signed-off-by: Hugo Villeneuve Signed-off-by: Philip Balister, OpenSDR --- include/configs/davinci_sffsdr.h | 69 ++++++++++++---------------------------- 1 file changed, 21 insertions(+), 48 deletions(-) (limited to 'include/configs') diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h index 41a6763..0e49e6c 100644 --- a/include/configs/davinci_sffsdr.h +++ b/include/configs/davinci_sffsdr.h @@ -1,6 +1,9 @@ /* * Copyright (C) 2007 Sergey Kubushyn * + * Copyright (C) 2008 Lyrtech + * Copyright (C) 2008 Philip Balister, OpenSDR + * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of @@ -21,30 +24,24 @@ #define __CONFIG_H #include -/*=======*/ /* Board */ -/*=======*/ #define SFFSDR #define CFG_NAND_LARGEPAGE #define CFG_USE_NAND -/*===================*/ +#define CFG_USE_DSPLINK /* This is to prevent U-Boot from + * powering ON the DSP. */ /* SoC Configuration */ -/*===================*/ #define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */ #define CFG_TIMERBASE 0x01c21400 /* use timer 0 */ #define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */ #define CFG_HZ 1000 -/*==================================================*/ -/* EEPROM definitions for Atmel 24LC64 EEPROM chip */ -/*==================================================*/ +/* EEPROM definitions for Atmel 24LC64 EEPROM chip */ #define CFG_I2C_EEPROM_ADDR_LEN 2 #define CFG_I2C_EEPROM_ADDR 0x50 #define CFG_EEPROM_PAGE_WRITE_BITS 5 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 -/*=============*/ /* Memory Info */ -/*=============*/ #define CFG_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */ #define CFG_GBL_DATA_SIZE 128 /* reserved for initial data */ #define CFG_MEMTEST_START 0x80000000 /* memtest start address */ @@ -54,9 +51,7 @@ #define PHYS_SDRAM_1 0x80000000 /* DDR Start */ #define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ #define DDR_4BANKS /* 4-bank DDR2 (128MB) */ -/*====================*/ /* Serial Driver info */ -/*====================*/ #define CFG_NS16550 #define CFG_NS16550_SERIAL #define CFG_NS16550_REG_SIZE 4 /* NS16550 register size */ @@ -65,16 +60,12 @@ #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ #define CONFIG_BAUDRATE 115200 /* Default baud rate */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -/*===================*/ /* I2C Configuration */ -/*===================*/ #define CONFIG_HARD_I2C #define CONFIG_DRIVER_DAVINCI_I2C #define CFG_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ #define CFG_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ -/*==================================*/ /* Network & Ethernet Configuration */ -/*==================================*/ #define CONFIG_DRIVER_TI_EMAC #define CONFIG_MII #define CONFIG_BOOTP_DEFAULT @@ -83,9 +74,7 @@ #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 10 #define CONFIG_OVERWRITE_ETHADDR_ONCE -/*=====================*/ /* Flash & Environment */ -/*=====================*/ #undef CFG_ENV_IS_IN_FLASH #define CFG_NO_FLASH #define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ @@ -98,28 +87,19 @@ #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define NAND_MAX_CHIPS 1 #define CFG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ -/*=====================*/ -/* Board related stuff */ -/*=====================*/ -/*==========================================*/ -/* I2C switch definitions for PCA9543 chip */ -/* on Lyrtech SFF SDR board. */ -/* This chip has a single register. */ -/*==========================================*/ +/* I2C switch definitions for PCA9543 chip */ #define CFG_I2C_PCA9543_ADDR 0x70 -#define CFG_I2C_PCA9543_ADDR_LEN 0 +#define CFG_I2C_PCA9543_ADDR_LEN 0 /* Single register. */ #define CFG_I2C_PCA9543_ENABLE_CH0 0x01 /* Enable channel 0. */ -/*==============================*/ /* U-Boot general configuration */ -/*==============================*/ -#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ +#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ #define CONFIG_MISC_INIT_R -#undef CONFIG_BOOTDELAY +#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds. */ #define CONFIG_BOOTFILE "uImage" /* Boot file name */ #define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -/* Print buffer size */ -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_PBSIZE \ + (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print buffer size */ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_LOAD_ADDR 0x80700000 /* Default Linux kernel @@ -133,25 +113,20 @@ #define CFG_LONGHELP #define CONFIG_CRC32_VERIFY #define CONFIG_MX_CYCLIC -/* - * Define this to load an Integrity kernel. - * -#define CONFIG_CMD_ELF - */ - -/*===================*/ /* Linux Information */ -/*===================*/ #define LINUX_BOOT_PARAM_ADDR 0x80000100 #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_BOOTARGS \ - "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp" -#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot" - -/*=================*/ +#define CONFIG_BOOTARGS \ + "mem=56M " \ + "console=ttyS0,115200n8 " \ + "root=/dev/nfs rw noinitrd ip=dhcp " \ + "nfsroot=${serverip}:/nfsroot/sffsdr " \ + "eth0=${ethaddr}" +#define CONFIG_BOOTCOMMAND \ + "nand read 87A00000 100000 300000;" \ + "bootelf 87A00000" /* U-Boot commands */ -/*=================*/ #include #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DHCP @@ -167,9 +142,7 @@ #undef CONFIG_CMD_SETGETDCR #undef CONFIG_CMD_FLASH #undef CONFIG_CMD_IMLS -/*=======================*/ /* KGDB support (if any) */ -/*=======================*/ #ifdef CONFIG_CMD_KGDB #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ -- cgit v1.1 From 47ce4a28ccfcfb803aa68d3d4505a8de056a8a5e Mon Sep 17 00:00:00 2001 From: Larry Johnson Date: Sat, 14 Jun 2008 16:53:02 -0400 Subject: ppc4xx: Update and add FDT to Korat board support Signed-off-by: Larry Johnson Signed-off-by: Stefan Roese --- include/configs/korat.h | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'include/configs') diff --git a/include/configs/korat.h b/include/configs/korat.h index 7655666..e2610be 100644 --- a/include/configs/korat.h +++ b/include/configs/korat.h @@ -129,7 +129,7 @@ #define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_FLASH1_TOP - CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE) @@ -185,7 +185,7 @@ #define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0" /* Note: kernel_addr and ramdisk_addr assume that FLASH1 is 64 MiB. */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CONFIG_EXTRA_ENV_SETTINGS \ CFG_BOOTFILE \ CFG_ROOTPATH \ "netdev=eth0\0" \ @@ -216,7 +216,7 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_IBM_EMAC4_V4 1 #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 2 /* PHY address, See schematics */ #define CONFIG_PHY_DYNAMIC_ANEG 1 @@ -548,4 +548,8 @@ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif +/* Pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + #endif /* __CONFIG_H */ -- cgit v1.1 From cf1c2ed91df26903b956948f37f82de9e1158a89 Mon Sep 17 00:00:00 2001 From: Larry Johnson Date: Sat, 14 Jun 2008 17:02:49 -0400 Subject: ppc4xx: Remove implementation of testdram() from Korat board support Signed-off-by: Larry Johnson Signed-off-by: Stefan Roese --- include/configs/korat.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/korat.h b/include/configs/korat.h index e2610be..4ca4ed0 100644 --- a/include/configs/korat.h +++ b/include/configs/korat.h @@ -145,7 +145,6 @@ #define CONFIG_DDR_ECC /* Use ECC when available */ #define SPD_EEPROM_ADDRESS {0x50} #define CONFIG_PROG_SDRAM_TLB -#define CFG_DRAM_TEST #define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ /* 440EPx errata CHIP 11 */ -- cgit v1.1 From 5d812b8b4ad9667c77a5bf92b4ba81699abc9fc3 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 9 Jul 2008 17:33:57 +0200 Subject: ppc4xx: Enable support for > 2GB SDRAM on AMCC Katmai Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM. To support such configurations, we "only" map the first 2GB via the TLB's. We need some free virtual address space for the remaining peripherals like, SoC devices, FLASH etc. Note that ECC is currently not supported on configurations with more than 2GB SDRAM. This is because we only map the first 2GB on such systems, and therefore the ECC parity byte of the remaining area can't be written. Signed-off-by: Stefan Roese --- include/configs/katmai.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'include/configs') diff --git a/include/configs/katmai.h b/include/configs/katmai.h index d3789bd..f07e470 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -41,6 +41,13 @@ #define CFG_4xx_RESET_TYPE 0x2 /* use chip reset on this board */ /* + * Enable this board for more than 2GB of SDRAM + */ +#define CONFIG_PHYS_64BIT +#define CONFIG_VERY_BIG_RAM +#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) + +/* * Include common defines/options for all AMCC eval boards */ #define CONFIG_HOSTNAME katmai -- cgit v1.1