From 7a577fda2243cc55b7b942310259f7d1341f0011 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 12 Jan 2011 02:48:53 -0600 Subject: powerpc/85xx: Move RESET_VECTOR_ADDRESS into config.h Rather than defining it config.mk we can set it in config.h and remove config.mk from several boards that don't need it. We mimic what 4xx does and introduce CONFIG_RESET_VECTOR_ADDRESS for config.h to set. Signed-off-by: Kumar Gala Acked-by: Wolfgang Denk --- include/configs/MPC8536DS.h | 6 ++++++ include/configs/MPC8572DS.h | 4 ++++ include/configs/P1022DS.h | 4 ++++ include/configs/P1_P2_RDB.h | 6 ++++++ include/configs/P2020DS.h | 4 ++++ include/configs/corenet_ds.h | 4 ++++ 6 files changed, 28 insertions(+) (limited to 'include/configs') diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index d1ae35d..11ee650 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -47,17 +47,23 @@ #ifdef CONFIG_SDCARD #define CONFIG_RAMBOOT_SDCARD 1 #define CONFIG_SYS_TEXT_BASE 0xf8f80000 +#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc #endif #ifdef CONFIG_SPIFLASH #define CONFIG_RAMBOOT_SPIFLASH 1 #define CONFIG_SYS_TEXT_BASE 0xf8f80000 +#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc #endif #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xeff80000 #endif +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + #ifndef CONFIG_SYS_MONITOR_BASE #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #endif diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index ea15831..e6b60cf 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -48,6 +48,10 @@ #define CONFIG_SYS_TEXT_BASE 0xeff80000 #endif +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + #ifndef CONFIG_SYS_MONITOR_BASE #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #endif diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 2b8fc7d..f310768 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -26,6 +26,10 @@ #define CONFIG_SYS_TEXT_BASE 0xeff80000 #endif +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ #define CONFIG_PCI /* Enable PCI/PCIE */ #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 80b0b40..d18d2f6 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -57,17 +57,23 @@ #ifdef CONFIG_SDCARD #define CONFIG_RAMBOOT_SDCARD 1 #define CONFIG_SYS_TEXT_BASE 0xf8f80000 +#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc #endif #ifdef CONFIG_SPIFLASH #define CONFIG_RAMBOOT_SPIFLASH 1 #define CONFIG_SYS_TEXT_BASE 0xf8f80000 +#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc #endif #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xeff80000 #endif +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + #ifndef CONFIG_SYS_MONITOR_BASE #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #endif diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index b6e3260..b32a997 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -45,6 +45,10 @@ #define CONFIG_SYS_TEXT_BASE 0xeff80000 #endif +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 23bbd42..fa05baa 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -41,6 +41,10 @@ #define CONFIG_SYS_TEXT_BASE 0xeff80000 #endif +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ -- cgit v1.1 From 243be8e296c53343eb21a6224f5329ff94778a4f Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 19 Jan 2011 03:05:26 -0600 Subject: powerpc/8xxx: Introduce 85xx, 86xx, QorIQ config headers Add new headers that capture common defines for a given SoC/processor rather than duplicating that information in board config.h and random other places. Eventually this should be handled by Kconfig & defconfigs Signed-off-by: Kumar Gala Acked-by: Wolfgang Denk --- include/configs/P4080DS.h | 16 ---------------- include/configs/corenet_ds.h | 2 -- 2 files changed, 18 deletions(-) (limited to 'include/configs') diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h index 5c818c9..49f7c53 100644 --- a/include/configs/P4080DS.h +++ b/include/configs/P4080DS.h @@ -26,23 +26,7 @@ #define CONFIG_P4080DS #define CONFIG_PHYS_64BIT #define CONFIG_PPC_P4080 -#define CONFIG_SYS_NUM_FMAN 2 -#define CONFIG_SYS_NUM_FM1_DTSEC 4 -#define CONFIG_SYS_NUM_FM2_DTSEC 4 -#define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_NUM_FM2_10GEC 1 -#define CONFIG_NUM_DDR_CONTROLLERS 2 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 ref clk freq */ -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 -#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 -#define CONFIG_SYS_FSL_ERRATUM_ESDHC136 - -#define CONFIG_SYS_P4080_ERRATUM_CPU22 -#define CONFIG_SYS_FSL_ERRATUM_CPC_A002 -#define CONFIG_SYS_FSL_ERRATUM_CPC_A003 -#define CONFIG_SYS_P4080_ERRATUM_SERDES8 -#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 - #include "corenet_ds.h" diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index fa05baa..5e9de90 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -446,13 +446,11 @@ #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 -#if (CONFIG_SYS_NUM_FMAN == 2) #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 -#endif #define CONFIG_SYS_TBIPA_VALUE 8 #define CONFIG_MII /* MII PHY management */ -- cgit v1.1 From 8ed20f2c178aa44c8e1a35703579fd63350e9f42 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 10 Jan 2011 12:02:58 +0000 Subject: corenet_ds: Enable ECC for corenet_ds ECC can be turned on/off by hwconfig without recompiling. So enable it by default. Signed-off-by: York Sun Signed-off-by: Kumar Gala --- include/configs/corenet_ds.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 5e9de90..bff212e 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -80,7 +80,7 @@ #define CONFIG_BACKSIDE_L2_CACHE #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E #define CONFIG_BTB /* toggle branch predition */ -/*#define CONFIG_DDR_ECC*/ +#define CONFIG_DDR_ECC #ifdef CONFIG_DDR_ECC #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef -- cgit v1.1 From b7070904327d10eb789ccafa4622659ffaa6645c Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Wed, 19 Jan 2011 10:52:04 +0530 Subject: ppc/85xx: Fix compile err when PCI disabled on P1_P2_RDB u-boot cannot be compiled after disabling CONFIG_PCI. Place PCI related codes under #ifdef CONFIG_PCI Signed-off-by: Prabhakar Kushwaha Signed-off-by: Kumar Gala --- include/configs/P1_P2_RDB.h | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) (limited to 'include/configs') diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index d18d2f6..bf34740 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -83,17 +83,23 @@ #define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/P1020/P2020,etc*/ #define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */ + #define CONFIG_PCI 1 /* Enable PCI/PCIE */ +#if defined(CONFIG_PCI) #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ +#endif /* #if defined(CONFIG_PCI) */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE +#if defined(CONFIG_PCI) #define CONFIG_E1000 1 /* E1000 pci Ethernet card*/ +#endif + #ifndef __ASSEMBLY__ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif @@ -364,6 +370,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); */ /* controller 2, Slot 2, tgtid 2, Base address 9000 */ +#if defined(CONFIG_PCI) #define CONFIG_SYS_PCIE2_NAME "Slot 1" #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 @@ -385,8 +392,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc30000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ -#if defined(CONFIG_PCI) -#define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ #undef CONFIG_EEPRO100 @@ -405,11 +410,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif /* CONFIG_PCI */ -#if defined(CONFIG_TSEC_ENET) -#ifndef CONFIG_NET_MULTI #define CONFIG_NET_MULTI 1 -#endif +#if defined(CONFIG_TSEC_ENET) #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ #define CONFIG_TSEC1 1 -- cgit v1.1