From 32556443840f127170e4baa8bdd5b567039f6c36 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Sat, 21 Apr 2007 21:07:22 +0200
Subject: [PATCH] SystemACE support for Microblaze

---
 include/configs/ml401.h  | 26 +++++++++++++++++---------
 include/configs/xupv2p.h | 14 ++++++++------
 2 files changed, 25 insertions(+), 15 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/ml401.h b/include/configs/ml401.h
index f4a8a1f..15c2fe7 100644
--- a/include/configs/ml401.h
+++ b/include/configs/ml401.h
@@ -36,7 +36,7 @@
 #define	CFG_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }
 
 /* setting reset address */
-#define	CFG_RESET_ADDRESS	TEXT_BASE
+//#define	CFG_RESET_ADDRESS	TEXT_BASE
 
 /* ethernet */
 #define CONFIG_EMACLITE		1
@@ -66,7 +66,7 @@
  *
  * CFG_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000
  * CFG_MONITOR_BASE = 0x13FF_F000 - 0x40000 = 0x13FB_F000
- * CFG_MALLOC_BASE = 0x13FB_F000 - 0x40000 = 0x13F7_F000 
+ * CFG_MALLOC_BASE = 0x13FB_F000 - 0x40000 = 0x13F7_F000
  *
  * 0x1000_0000	CFG_SDRAM_BASE
  *					FREE
@@ -93,7 +93,8 @@
 
 /* global pointer */
 #define	CFG_GBL_DATA_SIZE	0x1000	/* size of global data */
-#define	CFG_GBL_DATA_OFFSET     (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) /* start of global data */
+/* start of global data */
+#define	CFG_GBL_DATA_OFFSET     (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) 
 
 /* monitor code */
 #define	SIZE			0x40000
@@ -152,6 +153,8 @@
 				CFG_CMD_IMI |\
 				CFG_CMD_NET |\
 				CFG_CMD_CACHE |\
+				CFG_CMD_FAT |\
+				CFG_CMD_EXT2 |\
 				CFG_CMD_IMLS |\
 				CFG_CMD_FLASH |\
 				CFG_CMD_PING \
@@ -174,6 +177,8 @@
 				CFG_CMD_FLASH |\
 				CFG_CMD_PING |\
 				CFG_CMD_ENV |\
+				CFG_CMD_FAT |\
+				CFG_CMD_EXT2 |\
 				CFG_CMD_SAVES \
 				)
 
@@ -189,6 +194,8 @@
 				CFG_CMD_BDI |\
 				CFG_CMD_RUN |\
 				CFG_CMD_LOADS |\
+				CFG_CMD_FAT |\
+				CFG_CMD_EXT2 |\
 				CFG_CMD_LOADB |\
 				CFG_CMD_IMI |\
 				CFG_CMD_NET |\
@@ -221,10 +228,11 @@
 #define CFG_HZ	1000
 
 /* system ace */
-/*#define CONFIG_SYSTEMACE
-#define DEBUG_SYSTEMACE
-#define CFG_SYSTEMACE_BASE	XILINX_SYSACE_BASEADDR
-#define CFG_SYSTEMACE_WIDTH	XILINX_SYSACE_MEM_WIDTH
-#define CONFIG_DOS_PARTITION
-*/
+#define	CONFIG_SYSTEMACE
+/* #define DEBUG_SYSTEMACE */
+#define	SYSTEMACE_CONFIG_FPGA
+#define	CFG_SYSTEMACE_BASE	XILINX_SYSACE_BASEADDR
+#define	CFG_SYSTEMACE_WIDTH	XILINX_SYSACE_MEM_WIDTH
+#define	CONFIG_DOS_PARTITION
+
 #endif	/* __CONFIG_H */
diff --git a/include/configs/xupv2p.h b/include/configs/xupv2p.h
index 224db5c..c89ef7c 100644
--- a/include/configs/xupv2p.h
+++ b/include/configs/xupv2p.h
@@ -132,6 +132,8 @@
 			CFG_CMD_LOADS |\
 			CFG_CMD_LOADB |\
 			CFG_CMD_MISC |\
+			CFG_CMD_FAT |\
+			CFG_CMD_EXT2 |\
 			CFG_CMD_PING \
 			)
 
@@ -163,12 +165,12 @@
 	"base 0;" \
 	"echo"
 
-
 /* system ace */
-/*#define	CONFIG_SYSTEMACE
-#define	DEBUG_SYSTEMACE
-#define	CFG_SYSTEMACE_BASE	0xCF000000
-#define	CFG_SYSTEMACE_WIDTH	16
-#define	CONFIG_DOS_PARTITION*/
+#define	CONFIG_SYSTEMACE
+/* #define DEBUG_SYSTEMACE */
+#define	SYSTEMACE_CONFIG_FPGA
+#define	CFG_SYSTEMACE_BASE	XILINX_SYSACE_BASEADDR
+#define	CFG_SYSTEMACE_WIDTH	XILINX_SYSACE_MEM_WIDTH
+#define	CONFIG_DOS_PARTITION
 
 #endif	/* __CONFIG_H */
-- 
cgit v1.1


From 96b8a05432f346f36493535c85320b70ec9c7c1b Mon Sep 17 00:00:00 2001
From: Scott Wood <scottwood@freescale.com>
Date: Mon, 16 Apr 2007 14:54:15 -0500
Subject: mpc83xx: Add MPC8313ERDB support.

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
 include/configs/MPC8313ERDB.h | 569 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 569 insertions(+)
 create mode 100644 include/configs/MPC8313ERDB.h

(limited to 'include/configs')

diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
new file mode 100644
index 0000000..2519c6b
--- /dev/null
+++ b/include/configs/MPC8313ERDB.h
@@ -0,0 +1,569 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * History
+ * 20061201: Wilson Lo (Wilson.Lo@freescale.com)
+ *           Initialized
+ * 20061210: Tanya Jiang (tanya.jiang@freescale.com)
+ *           Code Cleanup
+ * 20070410: Scott Wood <scottwood@freescale.com>
+ *           More cleanup
+ */
+/*
+ * mpc8313epb board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1
+#define CONFIG_MPC83XX		1
+#define CONFIG_MPC831X		1
+#define CONFIG_MPC8313		1
+#define CONFIG_MPC8313ERDB	1
+
+#define CONFIG_PCI
+#define CONFIG_83XX_GENERIC_PCI
+
+#ifdef CFG_66MHZ
+#define CONFIG_83XX_CLKIN	66000000	/* in Hz */
+#elif defined(CFG_33MHZ)
+#define CONFIG_83XX_CLKIN	33000000	/* in Hz */
+#else
+#error Unknown oscillator frequency.
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
+
+#define CONFIG_BOARD_EARLY_INIT_F		/* call board_pre_init */
+
+#define CFG_IMMR		0xE0000000
+
+#define CFG_MEMTEST_START	0x00001000
+#define CFG_MEMTEST_END		0x07f00000
+
+/* Early revs of this board will lock up hard when attempting
+ * to access the PMC registers, unless a JTAG debugger is
+ * connected, or some resistor modifications are made.
+ */
+#define CFG_8313ERDB_BROKEN_PMC 1
+
+#define CFG_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
+#define CFG_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_BASE		0x00000000	/* DDR is system memory*/
+#define CFG_SDRAM_BASE		CFG_DDR_BASE
+#define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
+
+/*
+ * Manually set up DDR parameters, as this board does not
+ * seem to have the SPD connected to I2C.
+ */
+#define CFG_DDR_SIZE		128		/* MB */
+#define CFG_DDR_CONFIG		( CSCONFIG_EN | CSCONFIG_AP \
+				| 0x00040000 /* TODO */ \
+				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
+				/* 0x80840102 */
+
+#define CFG_DDR_TIMING_3	0x00000000
+#define CFG_DDR_TIMING_0	( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
+				| ( 0 << TIMING_CFG0_WRT_SHIFT ) \
+				| ( 0 << TIMING_CFG0_RRT_SHIFT ) \
+				| ( 0 << TIMING_CFG0_WWT_SHIFT ) \
+				| ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
+				| ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
+				| ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
+				| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
+				/* 0x00220802 */
+#define CFG_DDR_TIMING_1	( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
+				| ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
+				| ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
+				| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
+				| (13 << TIMING_CFG1_REFREC_SHIFT ) \
+				| ( 3 << TIMING_CFG1_WRREC_SHIFT ) \
+				| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
+				| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
+				/* 0x3935d322 */
+#define CFG_DDR_TIMING_2	( ( 0 << TIMING_CFG2_ADD_LAT_SHIFT ) \
+				| (31 << TIMING_CFG2_CPO_SHIFT ) \
+				| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
+				| ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
+				| ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
+				| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
+				| (10 << TIMING_CFG2_FOUR_ACT_SHIFT) )
+				/* 0x0f9048ca */ /* P9-45,may need tuning */
+#define CFG_DDR_INTERVAL	( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \
+				| ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
+				/* 0x03200064 */
+#if defined(CONFIG_DDR_2T_TIMING)
+#define CFG_SDRAM_CFG		( SDRAM_CFG_SREN \
+				| 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
+				| SDRAM_CFG_2T_EN \
+				| SDRAM_CFG_DBW_32 )
+#else
+#define CFG_SDRAM_CFG		( SDRAM_CFG_SREN \
+				| 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
+				| SDRAM_CFG_32_BE )
+				/* 0x43080000 */
+#endif
+#define CFG_SDRAM_CFG2		0x00401000;
+/* set burst length to 8 for 32-bit data path */
+#define CFG_DDR_MODE		( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \
+				| ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
+				/* 0x44400232 */
+#define CFG_DDR_MODE_2		0x8000C000;
+
+#define CFG_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+				/*0x02000000*/
+#define CFG_DDRCDR_VALUE	( DDRCDR_EN \
+				| DDRCDR_PZ_NOMZ \
+				| DDRCDR_NZ_NOMZ \
+				| DDRCDR_M_ODR )
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CFG_FLASH_CFI				/* use the Common Flash Interface */
+#define CFG_FLASH_CFI_DRIVER			/* use the CFI driver */
+#define CFG_FLASH_BASE		0xFE000000	/* start of FLASH   */
+#define CFG_FLASH_SIZE		8		/* flash size in MB */
+#define CFG_FLASH_EMPTY_INFO			/* display empty sectors */
+#define CFG_FLASH_USE_BUFFER_WRITE		/* buffer up multiple bytes */
+
+#define CFG_BR0_PRELIM		(CFG_FLASH_BASE |    /* flash Base address */ \
+				(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
+				BR_V)		     /* valid */
+#define CFG_OR0_PRELIM		( 0xFF000000         /* 16 MByte */ \
+				| OR_GPCM_XACS \
+				| OR_GPCM_SCY_9 \
+				| OR_GPCM_EHTR \
+				| OR_GPCM_EAD )
+				/* 0xFF006FF7	TODO SLOW 16 MB flash size */
+#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE	/* window base at flash base */
+#define CFG_LBLAWAR0_PRELIM	0x80000017	/* 16 MB window size */
+
+#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
+#define CFG_MAX_FLASH_SECT	135		/* sectors per device */
+
+#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#endif
+
+#define CFG_INIT_RAM_LOCK	1
+#define CFG_INIT_RAM_ADDR	0xFD000000	/* Initial RAM address */
+#define CFG_INIT_RAM_END	0x1000		/* End of used area in RAM*/
+
+#define CFG_GBL_DATA_SIZE	0x100		/* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN		(512 * 1024)	/* Reserved for malloc */
+
+/*
+ * Local Bus LCRR and LBCR regs
+ */
+#define CFG_LCRR	LCRR_EADC_1 | LCRR_CLKDIV_2	/* 0x00010002 */
+#define CFG_LBC_LBCR	( 0x00040000 /* TODO */ \
+			| (0xFF << LBCR_BMT_SHIFT) \
+			| 0xF )	/* 0x0004ff0f */
+
+#define CFG_LBC_MRTPR	0x20000000  /*TODO */  /* LB refresh timer prescal, 266MHz/32 */
+
+/* drivers/nand/nand.c */
+#define CFG_NAND_BASE		0xE2800000 /* 0xF0000000 */
+#define CFG_MAX_NAND_DEVICE	1
+#define NAND_MAX_CHIPS		1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+
+#define CFG_BR1_PRELIM		( CFG_NAND_BASE \
+				| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
+				| BR_PS_8            /* Port Size = 8 bit */ \
+				| BR_MS_FCM          /* MSEL = FCM */ \
+				| BR_V )             /* valid */
+#define CFG_OR1_PRELIM		( 0xFFFF8000	/* length 32K */ \
+				| OR_FCM_CSCT \
+				| OR_FCM_CST \
+				| OR_FCM_CHT \
+				| OR_FCM_SCY_1 \
+				| OR_FCM_TRLX \
+				| OR_FCM_EHTR )
+				/* 0xFFFF8396 */
+#define CFG_LBLAWBAR1_PRELIM	CFG_NAND_BASE
+#define CFG_LBLAWAR1_PRELIM	0x8000000E	/* 32KB  */
+
+#define CFG_VSC7385_BASE	0xF0000000
+
+#define CONFIG_VSC7385_ENET			/* VSC7385 ethernet support */
+#define CFG_BR2_PRELIM		0xf0000801	/* VSC7385 Base address */
+#define CFG_OR2_PRELIM		0xfffe09ff	/* VSC7385, 128K bytes*/
+#define CFG_LBLAWBAR2_PRELIM	CFG_VSC7385_BASE/* Access window base at VSC7385 base */
+#define CFG_LBLAWAR2_PRELIM	0x80000010	/* Access window size 128K */
+
+/* local bus read write buffer mapping */
+#define CFG_BR3_PRELIM		0xFA000801	/* map at 0xFA000000 */
+#define CFG_OR3_PRELIM		0xFFFF8FF7	/* 32kB */
+#define CFG_LBLAWBAR3_PRELIM	0xFA000000
+#define CFG_LBLAWAR3_PRELIM	0x8000000E	/* 32KB  */
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE	8192
+
+#define OF_CPU			"PowerPC,8313@0"
+#define OF_SOC			"soc8313@e0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH		"/soc8313@e0000000/serial@4500"
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	1
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CFG_NS16550_COM1	(CFG_IMMR+0x4500)
+#define CFG_NS16550_COM2	(CFG_IMMR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+
+/* I2C */
+#define CONFIG_HARD_I2C			/* I2C with hardware support*/
+#define CONFIG_FSL_I2C
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
+#define CFG_I2C_OFFSET		0x3000
+#define CFG_I2C2_OFFSET		0x3100
+
+/* TSEC */
+#define CFG_TSEC1_OFFSET	0x24000
+#define CFG_TSEC1		(CFG_IMMR+CFG_TSEC1_OFFSET)
+#define CFG_TSEC2_OFFSET	0x25000
+#define CFG_TSEC2		(CFG_IMMR+CFG_TSEC2_OFFSET)
+#define CONFIG_NET_MULTI
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE	0x80000000
+#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CFG_PCI1_MMIO_BASE	0x90000000
+#define CFG_PCI1_MMIO_PHYS	CFG_PCI1_MMIO_BASE
+#define CFG_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CFG_PCI1_IO_BASE	0x00000000
+#define CFG_PCI1_IO_PHYS	0xE2000000
+#define CFG_PCI1_IO_SIZE	0x00100000	/* 1M */
+
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+#define CFG_PCI_SUBSYS_VENDORID 0x1057	/* Motorola */
+
+/*
+ * TSEC configuration
+ */
+#define CONFIG_TSEC_ENET		/* TSEC ethernet support */
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI		1
+#endif
+
+#define CONFIG_GMII			1	/* MII PHY management */
+#define CONFIG_MPC83XX_TSEC1		1
+
+#define CONFIG_MPC83XX_TSEC1_NAME	"TSEC0"
+#define CONFIG_MPC83XX_TSEC2		1
+#define CONFIG_MPC83XX_TSEC2_NAME	"TSEC1"
+#define TSEC1_PHY_ADDR			0x1c
+#define TSEC2_PHY_ADDR			4
+#define TSEC1_PHYIDX			0
+#define TSEC2_PHYIDX			0
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME			"TSEC1"
+
+/*
+ * Configure on-board RTC
+ */
+#define CONFIG_RTC_DS1337
+#define CFG_I2C_RTC_ADDR		0x68
+
+/*
+ * Environment
+ */
+#ifndef CFG_RAMBOOT
+	#define CFG_ENV_IS_IN_FLASH	1
+	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+	#define CFG_ENV_SECT_SIZE	0x10000	/* 64K(one sector) for env */
+	#define CFG_ENV_SIZE		0x2000
+
+/* Address and size of Redundant Environment Sector */
+#else
+	#define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+	#define CFG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+#define CFG_BASE_COMMANDS	( CONFIG_CMD_DFL	\
+				| CFG_CMD_PING		\
+				| CFG_CMD_DHCP		\
+				| CFG_CMD_I2C		\
+				| CFG_CMD_MII		\
+				| CFG_CMD_DATE		\
+				| CFG_CMD_PCI)
+
+#define CONFIG_CMDLINE_EDITING 1
+
+#define CFG_RAMBOOT_COMMANDS	(CFG_BASE_COMMANDS & \
+				 ~(CFG_CMD_ENV | CFG_CMD_LOADS))
+
+#if defined(CFG_RAMBOOT)
+#define CONFIG_COMMANDS CFG_RAMBOOT_COMMANDS
+#else
+#define CONFIG_COMMANDS CFG_BASE_COMMANDS
+#endif
+
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory */
+#define CFG_LOAD_ADDR	0x2000000	/* default load address */
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE		16384
+#define CFG_CACHELINE_SIZE	32
+#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
+
+#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
+
+#ifdef CFG_66MHZ
+
+/* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
+/* 0x62040000 */
+#define CFG_HRCW_LOW (\
+	0x20000000 /* reserved, must be set */ |\
+	HRCWL_DDRCM |\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_2X1 |\
+	HRCWL_CSB_TO_CLKIN_2X1 |\
+	HRCWL_CORE_TO_CSB_2X1)
+
+#elif defined(CFG_33MHZ)
+
+/* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
+/* 0x65040000 */
+#define CFG_HRCW_LOW (\
+	0x20000000 /* reserved, must be set */ |\
+	HRCWL_DDRCM |\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_2X1 |\
+	HRCWL_CSB_TO_CLKIN_5X1 |\
+	HRCWL_CORE_TO_CSB_2X1)
+
+#endif
+
+/* 0xa0606c00 */
+#define CFG_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_RL_EXT_LEGACY |\
+	HRCWH_TSEC1M_IN_RGMII |\
+	HRCWH_TSEC2M_IN_RGMII |\
+	HRCWH_BIG_ENDIAN |\
+	HRCWH_LALE_NORMAL)
+
+/* System IO Config */
+#define CFG_SICRH	(SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
+#define CFG_SICRL	SICRL_USBDR /* Enable Internal USB Phy  */
+
+#define CFG_HID0_INIT	0x000000000
+#define CFG_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
+                         HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
+
+#define CFG_HID2 HID2_HBE
+
+/* DDR @ 0x00000000 */
+#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10)
+#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* PCI @ 0x80000000 */
+#define CFG_IBAT1L	(CFG_PCI1_MEM_BASE | BATL_PP_10)
+#define CFG_IBAT1U	(CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT2L	(CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT2U	(CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* PCI2 not supported on 8313 */
+#define CFG_IBAT3L	(0)
+#define CFG_IBAT3U	(0)
+#define CFG_IBAT4L	(0)
+#define CFG_IBAT4U	(0)
+
+/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
+#define CFG_IBAT5L	(CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT5U	(CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
+#define CFG_IBAT6L	(0xF0000000 | BATL_PP_10)
+#define CFG_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT7L	(0)
+#define CFG_IBAT7U	(0)
+
+#define CFG_DBAT0L	CFG_IBAT0L
+#define CFG_DBAT0U	CFG_IBAT0U
+#define CFG_DBAT1L	CFG_IBAT1L
+#define CFG_DBAT1U	CFG_IBAT1U
+#define CFG_DBAT2L	CFG_IBAT2L
+#define CFG_DBAT2U	CFG_IBAT2U
+#define CFG_DBAT3L	CFG_IBAT3L
+#define CFG_DBAT3U	CFG_IBAT3U
+#define CFG_DBAT4L	CFG_IBAT4L
+#define CFG_DBAT4U	CFG_IBAT4U
+#define CFG_DBAT5L	CFG_IBAT5L
+#define CFG_DBAT5U	CFG_IBAT5U
+#define CFG_DBAT6L	CFG_IBAT6L
+#define CFG_DBAT6U	CFG_IBAT6U
+#define CFG_DBAT7L	CFG_IBAT7L
+#define CFG_DBAT7U	CFG_IBAT7U
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02	/* Software reboot */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ETHADDR		00:E0:0C:00:95:01
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR		00:E0:0C:00:95:02
+
+#define CONFIG_IPADDR		10.0.0.2
+#define CONFIG_SERVERIP		10.0.0.1
+#define CONFIG_GATEWAYIP	10.0.0.1
+#define CONFIG_NETMASK		255.0.0.0
+#define CONFIG_NETDEV		eth1
+
+#define CONFIG_HOSTNAME		mpc8313erdb
+#define CONFIG_ROOTPATH		/nfs/root/path
+#define CONFIG_BOOTFILE		uImage
+#define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
+#define CONFIG_FDTFILE		mpc8313erdb.dtb
+
+#define CONFIG_LOADADDR		200000	/* default location for tftp and bootm */
+#define CONFIG_BOOTDELAY	-1	/* -1 disables auto-boot */
+#define CONFIG_BAUDRATE		115200
+
+#define XMK_STR(x)	#x
+#define MK_STR(x)	XMK_STR(x)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"netdev=" MK_STR(CONFIG_NETDEV) "\0" 				\
+	"ethprime=TSEC1\0"						\
+	"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" 				\
+	"tftpflash=tftpboot $loadaddr $uboot; " 			\
+		"protect off " MK_STR(TEXT_BASE) " +$filesize; " 	\
+		"erase " MK_STR(TEXT_BASE) " +$filesize; " 		\
+		"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " 	\
+		"protect on " MK_STR(TEXT_BASE) " +$filesize; " 	\
+		"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" 	\
+	"fdtaddr=400000\0"						\
+	"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"				\
+	"console=ttyS0\0"						\
+	"setbootargs=setenv bootargs "					\
+		"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
+	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv rootdev /dev/nfs;"					\
+	"run setbootargs;"							\
+	"run setipargs;"							\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv rootdev /dev/ram;"					\
+	"run setbootargs;"						\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#undef MK_STR
+#undef XMK_STR
+
+#endif	/* __CONFIG_H */
-- 
cgit v1.1


From 144876a380f5756f57412caf74c1d6dc201dd796 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Tue, 24 Apr 2007 23:01:02 +0200
Subject: [PATCH] MTD partition support, JFFS2 support

---
 include/configs/ml401.h | 29 +++++++++++++++++++++++++++--
 1 file changed, 27 insertions(+), 2 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/ml401.h b/include/configs/ml401.h
index 15c2fe7..acaa1e4 100644
--- a/include/configs/ml401.h
+++ b/include/configs/ml401.h
@@ -40,7 +40,7 @@
 
 /* ethernet */
 #define CONFIG_EMACLITE		1
-#define XPAR_EMAC_0_DEVICE_ID	XPAR_XEMAC_NUM_INSTANCES
+#define XPAR_EMAC_0_DEVICE_ID	XPAR_OPB_ETHERNET_0_DEVICE_ID
 
 /* gpio */
 #define	CFG_GPIO_0		1
@@ -118,6 +118,7 @@
 	#define	CFG_FLASH_EMPTY_INFO	1	/* ?empty sector */
 	#define	CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
 	#define	CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
+	#define	CFG_FLASH_PROTECTION		/* hardware flash protection */
 
 	#ifdef	RAMENV
 		#define	CFG_ENV_IS_NOWHERE	1
@@ -136,6 +137,7 @@
 	#define	CFG_ENV_IS_NOWHERE	1
 	#define	CFG_ENV_SIZE		0x1000
 	#define	CFG_ENV_ADDR		(CFG_MONITOR_BASE - CFG_ENV_SIZE)
+	#define	CFG_FLASH_PROTECTION		/* hardware flash protection */
 #endif /* !FLASH */
 
 #ifdef	FLASH
@@ -155,6 +157,8 @@
 				CFG_CMD_CACHE |\
 				CFG_CMD_FAT |\
 				CFG_CMD_EXT2 |\
+				CFG_CMD_JFFS2 |\
+				CFG_CMD_ECHO |\
 				CFG_CMD_IMLS |\
 				CFG_CMD_FLASH |\
 				CFG_CMD_PING \
@@ -179,6 +183,8 @@
 				CFG_CMD_ENV |\
 				CFG_CMD_FAT |\
 				CFG_CMD_EXT2 |\
+				CFG_CMD_JFFS2 |\
+				CFG_CMD_ECHO |\
 				CFG_CMD_SAVES \
 				)
 
@@ -206,6 +212,17 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+/* JFFS2 partitions */
+#define CONFIG_JFFS2_CMDLINE	/* mtdparts command line support */
+#define MTDIDS_DEFAULT		"nor0=ml401-0"
+
+/* default mtd partition table */
+#define MTDPARTS_DEFAULT	"mtdparts=ml401-0:256k(u-boot),"\
+				"256k(env),3m(kernel),1m(romfs),"\
+				"1m(cramfs),-(jffs2)"
+#endif
+
 /* Miscellaneous configurable options */
 #define	CFG_PROMPT	"U-Boot-mONStR> "
 #define	CFG_CBSIZE	512	/* size of console buffer */
@@ -214,7 +231,7 @@
 #define	CFG_LONGHELP
 #define	CFG_LOAD_ADDR	0x12000000 /* default load address */
 
-#define	CONFIG_BOOTDELAY 	30
+#define	CONFIG_BOOTDELAY	30
 #define	CONFIG_BOOTARGS		"root=romfs"
 #define	CONFIG_HOSTNAME		"ml401"
 #define	CONFIG_BOOTCOMMAND 	"base 0;tftp 11000000 image.img;bootm"
@@ -235,4 +252,12 @@
 #define	CFG_SYSTEMACE_WIDTH	XILINX_SYSACE_MEM_WIDTH
 #define	CONFIG_DOS_PARTITION
 
+#define	CONFIG_PREBOOT		"echo U-BOOT for ML401;setenv preboot;echo"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS	"unlock=yes\0" /* hardware flash protection */\
+					"nor0=ml401-0\0"\
+					"mtdparts=mtdparts=ml401-0:"\
+					"256k(u-boot),256k(env),3m(kernel),"\
+					"1m(romfs),1m(cramfs),-(jffs2)\0"
+
 #endif	/* __CONFIG_H */
-- 
cgit v1.1


From 5c5d3242935cf3543af01142627494434834cf98 Mon Sep 17 00:00:00 2001
From: Kim Phillips <kim.phillips@freescale.com>
Date: Wed, 25 Apr 2007 12:34:38 -0500
Subject: mpc83xx: minor fixups for 8313rdb introduction

---
 include/configs/MPC8313ERDB.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 2519c6b..11858bf 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -47,9 +47,9 @@
 #define CONFIG_83XX_GENERIC_PCI
 
 #ifdef CFG_66MHZ
-#define CONFIG_83XX_CLKIN	66000000	/* in Hz */
+#define CONFIG_83XX_CLKIN	66666667	/* in Hz */
 #elif defined(CFG_33MHZ)
-#define CONFIG_83XX_CLKIN	33000000	/* in Hz */
+#define CONFIG_83XX_CLKIN	33333333	/* in Hz */
 #else
 #error Unknown oscillator frequency.
 #endif
-- 
cgit v1.1


From f64702b7fc8f8df39d31add770df6e372f9e9ce3 Mon Sep 17 00:00:00 2001
From: Timur Tabi <timur@freescale.com>
Date: Mon, 30 Apr 2007 13:59:50 -0500
Subject: Fix memory initialization on MPC8349E-mITX

Define CFG_DDR_SDRAM_CLK_CNTL for the MPC8349E-mITX and MPC8349E-mITX-GP.
This allows ddr->sdram_clk_cntl to be properly initialized.  This is necessary
on some ITX boards, notably those with a revision 3.1 CPU.

Also change spd_sdram() in cpu/mpc83xx/spd_sdram.c to not write anything into
ddr->sdram_clk_cntl if CFG_DDR_SDRAM_CLK_CNTL is not defined.

Signed-off-by: Timur Tabi <timur@freescale.com>
Acked-by: Michael Benedict <MBenedict@twacs.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
 include/configs/MPC8349ITX.h | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'include/configs')

diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 37bbfb3..906339e 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -154,6 +154,9 @@
 #define CFG_MEMTEST_START	0x1000		/* memtest region */
 #define CFG_MEMTEST_END		0x2000
 
+#define CFG_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
+				DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+
 #ifdef CONFIG_HARD_I2C
 #define CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR setup*/
 #endif
-- 
cgit v1.1


From ffc50f9bb194343c6303517a517708457a5eb6b8 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Sat, 5 May 2007 18:54:42 +0200
Subject: new: FSL and MSR support #2

---
 include/configs/ml401.h | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'include/configs')

diff --git a/include/configs/ml401.h b/include/configs/ml401.h
index acaa1e4..f3ef962 100644
--- a/include/configs/ml401.h
+++ b/include/configs/ml401.h
@@ -161,6 +161,7 @@
 				CFG_CMD_ECHO |\
 				CFG_CMD_IMLS |\
 				CFG_CMD_FLASH |\
+				CFG_CMD_MFSL |\
 				CFG_CMD_PING \
 				)
 	#else	/* !RAMENV */
@@ -185,6 +186,7 @@
 				CFG_CMD_EXT2 |\
 				CFG_CMD_JFFS2 |\
 				CFG_CMD_ECHO |\
+				CFG_CMD_MFSL |\
 				CFG_CMD_SAVES \
 				)
 
@@ -206,6 +208,7 @@
 				CFG_CMD_IMI |\
 				CFG_CMD_NET |\
 				CFG_CMD_CACHE |\
+				CFG_CMD_MFSL |\
 				CFG_CMD_PING \
 				)
 #endif	/* !FLASH */
-- 
cgit v1.1


From 19bf1fbad7f19d5a120be9b1daf136e052fcab39 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Mon, 7 May 2007 19:33:51 +0200
Subject: new: fsl interrupt support FSL_Has_data is connected to INTC.

---
 include/configs/ml401.h | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'include/configs')

diff --git a/include/configs/ml401.h b/include/configs/ml401.h
index f3ef962..327d31c 100644
--- a/include/configs/ml401.h
+++ b/include/configs/ml401.h
@@ -58,6 +58,10 @@
 #define	FREQUENCE		XILINX_CLOCK_FREQ
 #define	CFG_TIMER_0_PRELOAD	( FREQUENCE/1000 )
 
+/* FSL */
+#define	CFG_FSL_2
+#define	FSL_INTR_2	1
+
 /*
  * memory layout - Example
  * TEXT_BASE = 0x1200_0000;
-- 
cgit v1.1


From 193b4a3bb3acaddf798da8de0da05d94ba8774ee Mon Sep 17 00:00:00 2001
From: Jeffrey Mann <mannj@embeddedplanet.com>
Date: Mon, 7 May 2007 19:42:49 +0200
Subject: [PATCH] ppc4xx: Fix CONFIG_SYS_CLK_FREQ definition in Sequoia config
 file

A '3' got cut off in the formatting of the last patch to automatically
change the clock speed of the system clock on sequoia board.

Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
 include/configs/sequoia.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'include/configs')

diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index b7f79c2..e1572ba 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -40,7 +40,7 @@
 #define CONFIG_4xx		1		/* ... PPC4xx family	*/
 /* Detect Sequoia PLL input clock automatically via CPLD bit		*/
 #define CONFIG_SYS_CLK_FREQ    ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \
-				3333333 : 33000000)
+				33333333 : 33000000)
 
 #define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */
 #define CONFIG_MISC_INIT_R	1		/* Call misc_init_r	*/
-- 
cgit v1.1


From abca901869c3760b6c5fecb825db6c1d91a78a93 Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@denx.de>
Date: Mon, 7 May 2007 22:10:36 +0200
Subject: Get rid of duplicated file (see include/configs/sbc8560.h instead)

Signed-off-by: Wolfgang Denk <wd@denx.de>
---
 include/configs/SBC8560.h | 410 ----------------------------------------------
 1 file changed, 410 deletions(-)
 delete mode 100644 include/configs/SBC8560.h

(limited to 'include/configs')

diff --git a/include/configs/SBC8560.h b/include/configs/SBC8560.h
deleted file mode 100644
index 8b46a17..0000000
--- a/include/configs/SBC8560.h
+++ /dev/null
@@ -1,410 +0,0 @@
-/*
- * (C) Copyright 2002,2003 Motorola,Inc.
- * Xianghua Xiao <X.Xiao@motorola.com>
- *
- * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
- * Added support for Wind River SBC8560 board
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* mpc8560ads board configuration file */
-/* please refer to doc/README.mpc85xx for more info */
-/* make sure you change the MAC address and other network params first,
- * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#if XXX
-#define DEBUG		      /* General debug */
-#define ET_DEBUG
-#endif
-#define TSEC_DEBUG
-
-/* High Level Configuration Options */
-#define CONFIG_BOOKE		1	/* BOOKE			*/
-#define CONFIG_E500		1	/* BOOKE e500 family		*/
-#define CONFIG_MPC85xx		1	/* MPC8540/MPC8560		*/
-#define CONFIG_MPC85xx_REV1	1	/* MPC85xx Rev 1.0 chip		*/
-
-
-#define CONFIG_CPM2		1	/* has CPM2 */
-#define CONFIG_SBC8560      	1   	/* configuration for SBC8560 board */
-
-#define CONFIG_MPC8560ADS	1	/* MPC8560ADS board specific (supplement)	*/
-
-#define CONFIG_TSEC_ENET		/* tsec ethernet support	*/
-#undef	CONFIG_PCI			/* pci ethernet support		*/
-#undef  CONFIG_ETHER_ON_FCC		/* cpm FCC ethernet support	*/
-
-
-#define CONFIG_ENV_OVERWRITE
-
-/* Using Localbus SDRAM to emulate flash before we can program the flash,
- * normally you need a flash-boot image(u-boot.bin), if so undef this.
- */
-#undef CONFIG_RAM_AS_FLASH
-
-#if defined(CONFIG_PCI_66)		/* some PCI card is 33Mhz only	*/
-  #define CONFIG_SYS_CLK_FREQ	66000000/* sysclk for MPC85xx		*/
-#else
-  #define CONFIG_SYS_CLK_FREQ	33000000/* most pci cards are 33Mhz	*/
-#endif
-
-/* below can be toggled for performance analysis. otherwise use default */
-#define CONFIG_L2_CACHE			    /* toggle L2 cache		*/
-#undef	CONFIG_BTB			    /* toggle branch predition	*/
-#undef	CONFIG_ADDR_STREAMING		    /* toggle addr streaming	*/
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
-
-#undef	CFG_DRAM_TEST			    /* memory test, takes time	*/
-#define CFG_MEMTEST_START	0x00200000  /* memtest region */
-#define CFG_MEMTEST_END		0x00400000
-
-#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
-     defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
-     defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
-#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
-#endif
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default	*/
-
-#if XXX
-  #define CFG_CCSRBAR		0xfdf00000	/* relocated CCSRBAR	*/
-#else
-  #define CFG_CCSRBAR		0xff700000	/* default CCSRBAR	*/
-#endif
-#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
-
-#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory	 */
-#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
-#define CFG_SDRAM_SIZE		512		/* DDR is 512MB */
-#define SPD_EEPROM_ADDRESS	0x55		/*  DDR DIMM */
-
-#undef  CONFIG_DDR_ECC				/* only for ECC DDR module	*/
-#undef  CONFIG_SPD_EEPROM			/* Use SPD EEPROM for DDR setup */
-
-#if defined(CONFIG_MPC85xx_REV1)
-  #define CONFIG_DDR_DLL			/* possible DLL fix needed	*/
-#endif
-
-#undef CONFIG_CLOCKS_IN_MHZ
-
-#if defined(CONFIG_RAM_AS_FLASH)
-  #define CFG_LBC_SDRAM_BASE	0xfc000000	/* Localbus SDRAM */
-  #define CFG_FLASH_BASE	0xf8000000      /* start of FLASH 8M  */
-  #define CFG_BR0_PRELIM	0xf8000801      /* port size 8bit */
-  #define CFG_OR0_PRELIM	0xf8000ff7	/* 8MB Flash		*/
-#else /* Boot from real Flash */
-  #define CFG_LBC_SDRAM_BASE	0xf8000000	/* Localbus SDRAM */
-  #define CFG_FLASH_BASE	0xff800000      /* start of FLASH 8M    */
-  #define CFG_BR0_PRELIM	0xff800801      /* port size 8bit      */
-  #define CFG_OR0_PRELIM	0xff800ff7	/* 8MB Flash		*/
-#endif
-#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB	*/
-
-/* local bus definitions */
-#define CFG_BR1_PRELIM		0xe4001801	/* 64M, 32-bit flash */
-#define CFG_OR1_PRELIM		0xfc000ff7
-
-#define CFG_BR2_PRELIM		0x00000000	/* CS2 not used */
-#define CFG_OR2_PRELIM		0x00000000
-
-#define CFG_BR3_PRELIM		0xf0001861	/* 64MB localbus SDRAM	*/
-#define CFG_OR3_PRELIM		0xfc000cc1
-
-#if defined(CONFIG_RAM_AS_FLASH)
-  #define CFG_BR4_PRELIM	0xf4001861	/* 64M localbus SDRAM */
-#else
-  #define CFG_BR4_PRELIM	0xf8001861	/* 64M localbus SDRAM */
-#endif
-#define CFG_OR4_PRELIM		0xfc000cc1
-
-#define CFG_BR5_PRELIM		0xfc000801	/* 16M CS5 misc devices */
-#if 1
-  #define CFG_OR5_PRELIM	0xff000ff7
-#else
-  #define CFG_OR5_PRELIM	0xff0000f0
-#endif
-
-#define CFG_BR6_PRELIM		0xe0001801	/* 64M, 32-bit flash */
-#define CFG_OR6_PRELIM		0xfc000ff7
-#define CFG_LBC_LCRR		0x00030002	/* local bus freq	*/
-#define CFG_LBC_LBCR		0x00000000
-#define CFG_LBC_LSRT		0x20000000
-#define CFG_LBC_MRTPR		0x20000000
-#define CFG_LBC_LSDMR_1		0x2861b723
-#define CFG_LBC_LSDMR_2		0x0861b723
-#define CFG_LBC_LSDMR_3		0x0861b723
-#define CFG_LBC_LSDMR_4		0x1861b723
-#define CFG_LBC_LSDMR_5		0x4061b723
-
-/* just hijack the MOT BCSR def for SBC8560 misc devices */
-#define CFG_BCSR		((CFG_BR5_PRELIM & 0xff000000)|0x00400000)
-/* the size of CS5 needs to be >= 16M for TLB and LAW setups */
-
-#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK	1
-#define CFG_INIT_RAM_ADDR	0x70000000	/* Initial RAM address	*/
-#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */
-
-#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
-
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
-
-/* Serial Port */
-#undef  CONFIG_CONS_ON_SCC			/* define if console on SCC */
-#undef	CONFIG_CONS_NONE			/* define if console on something else */
-
-#define CONFIG_CONS_INDEX     1
-#undef	CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	1
-#define CFG_NS16550_CLK		1843200 /* get_bus_freq(0) */
-#define CONFIG_BAUDRATE		9600
-
-#define CFG_BAUDRATE_TABLE  \
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CFG_NS16550_COM1	((CFG_BR5_PRELIM & 0xff000000)+0x00700000)
-#define CFG_NS16550_COM2	((CFG_BR5_PRELIM & 0xff000000)+0x00800000)
-
-/* Use the HUSH parser */
-#define CFG_HUSH_PARSER
-#ifdef	CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
-#endif
-
-/* I2C */
-#define	 CONFIG_HARD_I2C		/* I2C with hardware support*/
-#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
-
-#define CFG_PCI_MEM_BASE	0xC0000000
-#define CFG_PCI_MEM_PHYS	0xC0000000
-#define CFG_PCI_MEM_SIZE	0x10000000
-
-#if defined(CONFIG_TSEC_ENET)		/* TSEC Ethernet port */
-
-#  define CONFIG_NET_MULTI	1
-#  define CONFIG_MII		1	/* MII PHY management		*/
-#  define CONFIG_MPC85xx_TSEC1
-#  define CONFIG_MPC85xx_TSEC1_NAME	"TSEC0"
-#  define TSEC1_PHY_ADDR	25
-#  define TSEC1_PHYIDX		0
-/* Options are: TSEC0 */
-#  define CONFIG_ETHPRIME		"TSEC0"
-
-
-#elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */
-
-  #undef  CONFIG_ETHER_NONE		/* define if ether on something else */
-  #define CONFIG_ETHER_ON_FCC2		/* cpm FCC ethernet support	*/
-  #define CONFIG_ETHER_INDEX	2	/* which channel for ether  */
-
-  #if (CONFIG_ETHER_INDEX == 2)
-    /*
-     * - Rx-CLK is CLK13
-     * - Tx-CLK is CLK14
-     * - Select bus for bd/buffers
-     * - Full duplex
-     */
-    #define CFG_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
-    #define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
-    #define CFG_CPMFCR_RAMTYPE	0
-    #define CFG_FCC_PSMR	(FCC_PSMR_FDE)
-
-  #elif (CONFIG_ETHER_INDEX == 3)
-    /* need more definitions here for FE3 */
-  #endif				/* CONFIG_ETHER_INDEX */
-
-  #define CONFIG_MII			/* MII PHY management */
-  #define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
-  /*
-   * GPIO pins used for bit-banged MII communications
-   */
-  #define MDIO_PORT	2		/* Port C */
-  #define MDIO_ACTIVE	(iop->pdir |=  0x00400000)
-  #define MDIO_TRISTATE	(iop->pdir &= ~0x00400000)
-  #define MDIO_READ	((iop->pdat &  0x00400000) != 0)
-
-  #define MDIO(bit)	if(bit) iop->pdat |=  0x00400000; \
-			else	iop->pdat &= ~0x00400000
-
-  #define MDC(bit)	if(bit) iop->pdat |=  0x00200000; \
-			else	iop->pdat &= ~0x00200000
-
-  #define MIIDELAY	udelay(1)
-
-#endif
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant		*/
-#define CFG_FLASH_CFI_DRIVER	1	/* Use the common driver		*/
-#if 0
-#define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)     */
-#define CFG_FLASH_PROTECTION		/* use hardware protection		*/
-#endif
-#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-
-#undef	CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT	200000		/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	50000		/* Timeout for Flash Write (in ms)	*/
-
-#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor	*/
-
-#if 0
-/* XXX This doesn't work and I don't want to fix it */
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-  #define CFG_RAMBOOT
-#else
-  #undef  CFG_RAMBOOT
-#endif
-#endif
-
-/* Environment */
-#if !defined(CFG_RAMBOOT)
-  #if defined(CONFIG_RAM_AS_FLASH)
-    #define CFG_ENV_IS_NOWHERE
-    #define CFG_ENV_ADDR	(CFG_FLASH_BASE + 0x100000)
-    #define CFG_ENV_SIZE	0x2000
-  #else
-    #define CFG_ENV_IS_IN_FLASH	1
-    #define CFG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
-    #define CFG_ENV_ADDR	(CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
-    #define CFG_ENV_SIZE	0x2000 /* CFG_ENV_SECT_SIZE */
-  #endif
-#else
-  #define CFG_NO_FLASH		1	/* Flash is not usable now	*/
-  #define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only	*/
-  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
-  #define CFG_ENV_SIZE		0x2000
-#endif
-
-#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600"
-/*#define CONFIG_BOOTARGS      "root=/dev/ram rw console=ttyS0,115200"*/
-#define CONFIG_BOOTCOMMAND	"bootm 0xff800000 0xffa00000"
-#define CONFIG_BOOTDELAY	5	/* -1 disable autoboot */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
-  #if defined(CONFIG_PCI)
-    #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL | CFG_CMD_PCI | \
-				CFG_CMD_PING | CFG_CMD_I2C) & \
-				 ~(CFG_CMD_ENV | \
-				  CFG_CMD_LOADS ))
-  #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC))
-    #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL | CFG_CMD_MII | \
-				CFG_CMD_PING | CFG_CMD_I2C) & \
-				~(CFG_CMD_ENV))
-  #endif
-#else
-  #if defined(CONFIG_PCI)
-    #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_PCI | \
-				CFG_CMD_PING | CFG_CMD_I2C)
-  #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC))
-    #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_MII | \
-				CFG_CMD_PING | CFG_CMD_I2C)
-  #endif
-#endif
-
-#include <cmd_confdefs.h>
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"SBC8560=> " /* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-  #define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-  #define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CFG_LOAD_ADDR	0x1000000	/* default load address */
-#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
-
-/* Cache Configuration */
-#define CFG_DCACHE_SIZE		32768
-#define CFG_CACHELINE_SIZE	32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-  #define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM	0x02		/* Software reboot		*/
-
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-  #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-  #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
-#endif
-
-/*Note: change below for your network setting!!! */
-#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
-#  define CONFIG_ETHADDR	00:vv:ww:xx:yy:8a
-#  define CONFIG_HAS_ETH1
-#  define CONFIG_ETH1ADDR	00:vv:ww:xx:yy:8b
-#  define CONFIG_HAS_ETH2
-#  define CONFIG_ETH2ADDR	00:vv:ww:xx:yy:8c
-#endif
-
-#define CONFIG_SERVERIP		YourServerIP
-#define CONFIG_IPADDR		YourTargetIP
-#define CONFIG_GATEWAYIP	YourGatewayIP
-#define CONFIG_NETMASK		255.255.255.0
-#define CONFIG_HOSTNAME		SBC8560
-#define CONFIG_ROOTPATH		YourRootPath
-#define CONFIG_BOOTFILE		YourImageName
-
-#endif	/* __CONFIG_H */
-- 
cgit v1.1


From 1f1369c34b629be94702684d41d3fddf0f6193e7 Mon Sep 17 00:00:00 2001
From: Bartlomiej Sieka <tur@semihalf.com>
Date: Tue, 8 May 2007 09:21:57 +0200
Subject: [Motion-PRO] Enable Flat Device Tree support and modify default
 environment to allow booting of FDT-expecting kernels.

---
 include/configs/motionpro.h | 49 +++++++++++++++++++++++++++------------------
 1 file changed, 30 insertions(+), 19 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index 5328e8d..b1edde8 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -26,7 +26,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-
 /*
  * High Level Configuration Options
  */
@@ -94,42 +93,44 @@
  * Default environment settings
  */
 #define CONFIG_EXTRA_ENV_SETTINGS					\
-	"sdram_test=0\0"						\
 	"netdev=eth0\0"							\
 	"hostname=motionpro\0"						\
 	"netmask=255.255.0.0\0"						\
 	"ipaddr=192.168.160.22\0"					\
 	"serverip=192.168.1.1\0"					\
 	"gatewayip=192.168.1.1\0"					\
-	"kernel_addr=200000\0"						\
+	"console=ttyPSC0,115200\0"					\
 	"u-boot_addr=100000\0"						\
-	"kernel_sector=20\0"						\
-	"kernel_size=1000\0"						\
-	"console=ttyS0,115200\0"					\
+	"kernel_addr=200000\0"						\
+	"fdt_addr=400000\0"						\
+	"ramdisk_addr=500000\0"						\
 	"rootpath=/opt/eldk-4.1/ppc_6xx\0"				\
-	"bootfile=/tftpboot/motionpro/uImage\0"				\
 	"u-boot=/tftpboot/motionpro/u-boot.bin\0"			\
+	"bootfile=/tftpboot/motionpro/uImage\0"				\
+	"fdt_file=/tftpboot/motionpro/motionpro.dtb\0"			\
+	"ramdisk_file=/tftpboot/motionpro/uRamdisk\0"			\
 	"load=tftp $(u-boot_addr) $(u-boot)\0"				\
 	"update=prot off fff00000 fff3ffff; era fff00000 fff3ffff; "	\
 		"cp.b $(u-boot_addr) fff00000 $(filesize);"		\
 		"prot on fff00000 fff3ffff\0"				\
 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs $(bootargs) console=$(console) "		\
-		"ip=$(ipaddr):$(serverip):$(gatewayip):"		\
-		"$(netmask):$(hostname):$(netdev):off panic=1\0"	\
-	"flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0"		\
-	"flash_self=run ramargs addip;bootm $(kernel_addr) "		\
-		"$(ramdisk_addr)\0"					\
-	"net_nfs=tftp $(kernel_addr) $(bootfile); run nfsargs addip; "	\
-		"bootm $(kernel_addr)\0"				\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 		"nfsroot=$(serverip):$(rootpath)\0"			\
-	"fstype=ext3\0"							\
-	"fatargs=setenv bootargs init=/linuxrc rw\0"			\
+	"addip=setenv bootargs $(bootargs) "				\
+		"ip=$(ipaddr):$(serverip):$(gatewayip):"		\
+		"$(netmask):$(hostname):$(netdev):off panic=1 "		\
+		"console=$(console)\0"					\
+	"net_nfs=tftp $(kernel_addr) $(bootfile); "			\
+		"tftp $(fdt_addr) $(fdt_file); run nfsargs addip; "	\
+		"bootm $(kernel_addr) - $(fdt_addr)\0"			\
+	"net_self=tftp $(kernel_addr) $(bootfile); "			\
+		"tftp $(fdt_addr) $(fdt_file); "			\
+		"tftp $(ramdisk_addr) $(ramdisk_file); "		\
+		"run ramargs addip; "					\
+		"bootm $(kernel_addr) $(ramdisk_addr) $(fdt_addr)\0"	\
 	""
 #define CONFIG_BOOTCOMMAND	"run net_nfs"
 
-
 /*
  * do board-specific init
  */
@@ -146,7 +147,6 @@
  */
 #define CFG_MPC5XXX_CLKIN	25000000
 
-
 /*
  * Memory map
  */
@@ -302,4 +302,15 @@
 /* Not needed for MPC 5xxx U-Boot, but used by tools/updater */
 #define CFG_RESET_ADDRESS	0xfff00100
 
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE	8192
+#define OF_CPU			"PowerPC,5200@0"
+#define OF_SOC			"soc5200@f0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#define OF_STDOUT_PAT		"/soc5200@f0000000/serial@2000"
+
 #endif /* __CONFIG_H */
-- 
cgit v1.1


From 06241d50a3ab1b20a0b08baeeaffcaa23ae4b839 Mon Sep 17 00:00:00 2001
From: Bartlomiej Sieka <tur@semihalf.com>
Date: Tue, 8 May 2007 09:39:12 +0200
Subject: [Motion-PRO] Change IPB clock frequency from 50MHz to 100MHz. This
 eliminates networking problems in Linux (timeouts).

---
 include/configs/motionpro.h | 7 +++++++
 1 file changed, 7 insertions(+)

(limited to 'include/configs')

diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index b1edde8..74ba800 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -147,6 +147,13 @@
  */
 #define CFG_MPC5XXX_CLKIN	25000000
 
+
+/*
+ * Set IPB speed to 100MHz (yes, the #define is misnamed)
+ */
+#define CFG_IPBSPEED_133
+
+
 /*
  * Memory map
  */
-- 
cgit v1.1


From fa5c2ba123b1bf88455bfc21db5e786ca045029d Mon Sep 17 00:00:00 2001
From: Bartlomiej Sieka <tur@semihalf.com>
Date: Tue, 8 May 2007 10:23:56 +0200
Subject: [Motion-PRO] Add ATA support. Add CF-booting commands to the default
 environment.

---
 include/configs/motionpro.h | 25 +++++++++++++++++++++++--
 1 file changed, 23 insertions(+), 2 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index 74ba800..989a534 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -30,7 +30,6 @@
  * High Level Configuration Options
  */
 
-
 /* CPU and board */
 #define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
 #define CONFIG_MPC5200		1	/* More exactly a MPC5200 */
@@ -49,7 +48,9 @@
 				CFG_CMD_MII	| \
 				CFG_CMD_BEDBUG	| \
 				CFG_CMD_NET	| \
-				CFG_CMD_PING)
+				CFG_CMD_PING	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_FAT)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
@@ -104,11 +105,13 @@
 	"kernel_addr=200000\0"						\
 	"fdt_addr=400000\0"						\
 	"ramdisk_addr=500000\0"						\
+	"multi_image_addr=800000\0"					\
 	"rootpath=/opt/eldk-4.1/ppc_6xx\0"				\
 	"u-boot=/tftpboot/motionpro/u-boot.bin\0"			\
 	"bootfile=/tftpboot/motionpro/uImage\0"				\
 	"fdt_file=/tftpboot/motionpro/motionpro.dtb\0"			\
 	"ramdisk_file=/tftpboot/motionpro/uRamdisk\0"			\
+	"multi_image_file=kernel+initrd+dtb.img\0"			\
 	"load=tftp $(u-boot_addr) $(u-boot)\0"				\
 	"update=prot off fff00000 fff3ffff; era fff00000 fff3ffff; "	\
 		"cp.b $(u-boot_addr) fff00000 $(filesize);"		\
@@ -116,6 +119,7 @@
 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 		"nfsroot=$(serverip):$(rootpath)\0"			\
+	"fat_args=setenv bootargs rw\0"					\
 	"addip=setenv bootargs $(bootargs) "				\
 		"ip=$(ipaddr):$(serverip):$(gatewayip):"		\
 		"$(netmask):$(hostname):$(netdev):off panic=1 "		\
@@ -128,6 +132,9 @@
 		"tftp $(ramdisk_addr) $(ramdisk_file); "		\
 		"run ramargs addip; "					\
 		"bootm $(kernel_addr) $(ramdisk_addr) $(fdt_addr)\0"	\
+	"fat_multi=run fat_args addip; fatload ide 0:1 "		\
+		"${multi_image_addr} ${multi_image_file}; "		\
+		"bootm ${multi_image_addr}\0"				\
 	""
 #define CONFIG_BOOTCOMMAND	"run net_nfs"
 
@@ -252,6 +259,20 @@
 
 
 /*
+ * IDE/ATA configuration
+ */
+#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+#define CFG_IDE_MAXBUS		1
+#define CFG_IDE_MAXDEVICE	1
+#define CONFIG_IDE_PREINIT
+
+#define CFG_ATA_DATA_OFFSET	0x0060
+#define CFG_ATA_REG_OFFSET	CFG_ATA_DATA_OFFSET
+#define CFG_ATA_STRIDE		4
+#define CONFIG_DOS_PARTITION
+
+
+/*
  * Environment settings
  */
 #define CFG_ENV_IS_IN_FLASH	1
-- 
cgit v1.1


From de1de02a7cbf05e6b63e0d8ffc624f12493f6ba3 Mon Sep 17 00:00:00 2001
From: Piotr Kruszynski <ppk@semihalf.com>
Date: Tue, 8 May 2007 13:05:44 +0200
Subject: [Motion-PRO] Add support for I2C, EEPROM and RTC.

---
 include/configs/motionpro.h | 30 +++++++++++++++++++++++++++++-
 1 file changed, 29 insertions(+), 1 deletion(-)

(limited to 'include/configs')

diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index 989a534..f1f7e2b 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -50,7 +50,10 @@
 				CFG_CMD_NET	| \
 				CFG_CMD_PING	| \
 				CFG_CMD_IDE	| \
-				CFG_CMD_FAT)
+				CFG_CMD_FAT	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_EEPROM)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
@@ -273,6 +276,31 @@
 
 
 /*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CFG_I2C_MODULE		2	/* select I2C module #2 */
+#define CFG_I2C_SPEED		100000	/* 100 kHz */
+#define CFG_I2C_SLAVE		0x7F
+
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR_LEN		1
+#define CFG_EEPROM_PAGE_WRITE_BITS	3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70
+#define CFG_I2C_MULTI_EEPROMS		1	/* 2 EEPROMs (addr:50,52) */
+
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_DS1337	1
+#define CFG_I2C_RTC_ADDR	0x68
+
+
+/*
  * Environment settings
  */
 #define CFG_ENV_IS_IN_FLASH	1
-- 
cgit v1.1


From 1a50f164beb065f360fbddb76029607d6b099698 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Tue, 8 May 2007 14:52:52 +0200
Subject: add: Microblaze V5 exception handling

---
 include/configs/ml401.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'include/configs')

diff --git a/include/configs/ml401.h b/include/configs/ml401.h
index 327d31c..4cfe802 100644
--- a/include/configs/ml401.h
+++ b/include/configs/ml401.h
@@ -28,6 +28,7 @@
 #include "../board/xilinx/ml401/xparameters.h"
 
 #define	CONFIG_MICROBLAZE	1	/* MicroBlaze CPU */
+#define	MICROBLAZE_V5		1
 #define	CONFIG_ML401		1	/* ML401 Board */
 
 /* uart */
-- 
cgit v1.1


From 7d98ba770a7eaefa29ce927f31a0956df85bf650 Mon Sep 17 00:00:00 2001
From: Piotr Kruszynski <ppk@semihalf.com>
Date: Thu, 10 May 2007 16:55:52 +0200
Subject: [Motion-PRO] Add MTD and JFFS2 support, also add default partition
 definition.

---
 include/configs/motionpro.h | 9 +++++++++
 1 file changed, 9 insertions(+)

(limited to 'include/configs')

diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index f1f7e2b..e6e0eb1 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -51,6 +51,7 @@
 				CFG_CMD_PING	| \
 				CFG_CMD_IDE	| \
 				CFG_CMD_FAT	| \
+				CFG_CMD_JFFS2	| \
 				CFG_CMD_I2C	| \
 				CFG_CMD_DATE	| \
 				CFG_CMD_EEPROM)
@@ -260,6 +261,14 @@
 #define CFG_MAX_FLASH_SECT	256	/* max num of sects on one chip */
 #define CONFIG_FLASH_16BIT		/* Flash is 16-bit */
 
+/*
+ * MTD configuration
+ */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=motionpro-0"
+#define MTDPARTS_DEFAULT	"mtdparts=motionpro-0:"			  \
+					"13m(fs),2m(kernel),256k(uboot)," \
+					"64k(env),64k(dtb),-(user_data)"
 
 /*
  * IDE/ATA configuration
-- 
cgit v1.1


From d62f64cc23a940eafe712c776b3249e4160753d1 Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@denx.de>
Date: Wed, 16 May 2007 00:13:33 +0200
Subject: Coding Style Cleanup, new CHANGELOG

---
 include/configs/ml401.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/ml401.h b/include/configs/ml401.h
index 4cfe802..3db2877 100644
--- a/include/configs/ml401.h
+++ b/include/configs/ml401.h
@@ -37,7 +37,7 @@
 #define	CFG_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }
 
 /* setting reset address */
-//#define	CFG_RESET_ADDRESS	TEXT_BASE
+/*#define	CFG_RESET_ADDRESS	TEXT_BASE*/
 
 /* ethernet */
 #define CONFIG_EMACLITE		1
@@ -99,7 +99,7 @@
 /* global pointer */
 #define	CFG_GBL_DATA_SIZE	0x1000	/* size of global data */
 /* start of global data */
-#define	CFG_GBL_DATA_OFFSET     (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) 
+#define	CFG_GBL_DATA_OFFSET     (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE)
 
 /* monitor code */
 #define	SIZE			0x40000
-- 
cgit v1.1


From a7676ea7732f3c596805079fed7e5c9fac652cfc Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@denx.de>
Date: Wed, 16 May 2007 01:16:53 +0200
Subject: Minor Coding Style cleanup, update CHANGELOG.

Signed-off-by: Wolfgang Denk <wd@denx.de>
---
 include/configs/MPC8313ERDB.h | 40 ++++++++++++++++------------------------
 1 file changed, 16 insertions(+), 24 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 11858bf..6976313 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -18,14 +18,6 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
- *
- * History
- * 20061201: Wilson Lo (Wilson.Lo@freescale.com)
- *           Initialized
- * 20061210: Tanya Jiang (tanya.jiang@freescale.com)
- *           Code Cleanup
- * 20070410: Scott Wood <scottwood@freescale.com>
- *           More cleanup
  */
 /*
  * mpc8313epb board configuration file
@@ -154,10 +146,10 @@
 #define CFG_FLASH_EMPTY_INFO			/* display empty sectors */
 #define CFG_FLASH_USE_BUFFER_WRITE		/* buffer up multiple bytes */
 
-#define CFG_BR0_PRELIM		(CFG_FLASH_BASE |    /* flash Base address */ \
-				(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
-				BR_V)		     /* valid */
-#define CFG_OR0_PRELIM		( 0xFF000000         /* 16 MByte */ \
+#define CFG_BR0_PRELIM		(CFG_FLASH_BASE |	/* flash Base address */ \
+				(2 << BR_PS_SHIFT) |	/* 16 bit port size */ \
+				BR_V)			/* valid */
+#define CFG_OR0_PRELIM		( 0xFF000000		/* 16 MByte */ \
 				| OR_GPCM_XACS \
 				| OR_GPCM_SCY_9 \
 				| OR_GPCM_EHTR \
@@ -197,20 +189,20 @@
 			| (0xFF << LBCR_BMT_SHIFT) \
 			| 0xF )	/* 0x0004ff0f */
 
-#define CFG_LBC_MRTPR	0x20000000  /*TODO */  /* LB refresh timer prescal, 266MHz/32 */
+#define CFG_LBC_MRTPR	0x20000000  /*TODO */ 	/* LB refresh timer prescal, 266MHz/32 */
 
 /* drivers/nand/nand.c */
-#define CFG_NAND_BASE		0xE2800000 /* 0xF0000000 */
+#define CFG_NAND_BASE		0xE2800000	/* 0xF0000000 */
 #define CFG_MAX_NAND_DEVICE	1
 #define NAND_MAX_CHIPS		1
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 
 #define CFG_BR1_PRELIM		( CFG_NAND_BASE \
-				| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
-				| BR_PS_8            /* Port Size = 8 bit */ \
-				| BR_MS_FCM          /* MSEL = FCM */ \
-				| BR_V )             /* valid */
-#define CFG_OR1_PRELIM		( 0xFFFF8000	/* length 32K */ \
+				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
+				| BR_PS_8		/* Port Size = 8 bit */ \
+				| BR_MS_FCM		/* MSEL = FCM */ \
+				| BR_V )		/* valid */
+#define CFG_OR1_PRELIM		( 0xFFFF8000		/* length 32K */ \
 				| OR_FCM_CSCT \
 				| OR_FCM_CST \
 				| OR_FCM_CHT \
@@ -378,7 +370,7 @@
 #define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
 #define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
 
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
 #define CFG_MAXARGS	16		/* max number of command args */
 #define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
 #define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
@@ -395,7 +387,7 @@
 #define CFG_CACHELINE_SIZE	32
 #define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
 
-#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
+#define CFG_RCWH_PCIHOST 0x80000000	/* PCIHOST  */
 
 #ifdef CFG_66MHZ
 
@@ -439,12 +431,12 @@
 	HRCWH_LALE_NORMAL)
 
 /* System IO Config */
-#define CFG_SICRH	(SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
-#define CFG_SICRL	SICRL_USBDR /* Enable Internal USB Phy  */
+#define CFG_SICRH	(SICRH_TSOBI1 | SICRH_TSOBI2)	/* RGMII */
+#define CFG_SICRL	SICRL_USBDR			/* Enable Internal USB Phy  */
 
 #define CFG_HID0_INIT	0x000000000
 #define CFG_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
-                         HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
+			 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 
 #define CFG_HID2 HID2_HBE
 
-- 
cgit v1.1


From 5d4a179013d59a76446462e1eb0a969fba63eb81 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Thu, 24 May 2007 08:22:09 +0200
Subject: ppc4xx: Update AMCC Acadia support for board revision 1.1

This patch updates the Acadia (405EZ) support for the new 1.1 board
revision. It also adds support for NAND FLASH via the 4xx NDFC.

Please note that the jumper J7 must be in position 2-3 for this
NAND support. Position 1-2 is for NAND booting only. NAND booting
support will follow later.

Signed-off-by: Stefan Roese <sr@denx.de>
---
 include/configs/acadia.h | 27 +++++++++------------------
 1 file changed, 9 insertions(+), 18 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/acadia.h b/include/configs/acadia.h
index 35b6a51..c72d933 100644
--- a/include/configs/acadia.h
+++ b/include/configs/acadia.h
@@ -34,7 +34,9 @@
 #define CONFIG_ACADIA		1		/* Board is Acadia	*/
 #define CONFIG_4xx		1		/* ... PPC4xx family	*/
 #define CONFIG_405EZ		1		/* Specifc 405EZ support*/
-#define CONFIG_SYS_CLK_FREQ	66666666	/* external freq to pll	*/
+/* Detect Acadia PLL input clock automatically via CPLD bit		*/
+#define CONFIG_SYS_CLK_FREQ    ((in8(CFG_CPLD_BASE + 0) == 0x0c) ? \
+				66666666 : 33333000)
 
 #define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */
 #define CONFIG_MISC_INIT_F	1		/* Call misc_init_f	*/
@@ -224,16 +226,6 @@
 #define CONFIG_USB_OHCI
 #define CONFIG_USB_STORAGE
 
-#if 0 /* test-only */
-#define TEST_ONLY_NAND
-#endif
-
-#ifdef TEST_ONLY_NAND
-#define CMD_NAND		CFG_CMD_NAND
-#else
-#define CMD_NAND		0
-#endif
-
 /* Partitions */
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
@@ -252,7 +244,7 @@
 			       CFG_CMD_I2C	|	\
 			       CFG_CMD_IRQ	|	\
 			       CFG_CMD_MII	|	\
-			       CMD_NAND		|	\
+			       CFG_CMD_NAND	|	\
 			       CFG_CMD_NET	|	\
 			       CFG_CMD_NFS	|	\
 			       CFG_CMD_PCI	|	\
@@ -300,7 +292,6 @@
  */
 #define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
-#ifdef TEST_ONLY_NAND
 /*-----------------------------------------------------------------------
  * NAND FLASH
  *----------------------------------------------------------------------*/
@@ -308,7 +299,6 @@
 #define NAND_MAX_CHIPS		1
 #define CFG_NAND_BASE		(CFG_NAND_ADDR + CFG_NAND_CS)
 #define CFG_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips	*/
-#endif
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
@@ -322,7 +312,7 @@
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  *----------------------------------------------------------------------*/
-#define CFG_NAND_CS		0		/* NAND chip connected to CSx	*/
+#define CFG_NAND_CS		3		/* NAND chip connected to CSx	*/
 
 /* Memory Bank 0 (Flash) initialization						*/
 #define CFG_EBC_PB0AP		0x03337200
@@ -358,7 +348,8 @@
 /*-----------------------------------------------------------------------
  * Definitions for GPIO_0 setup (PPC405EZ specific)
  *
- * GPIO0[0-3]	- External Bus Controller CS_4 - CS_7 Outputs
+ * GPIO0[0-2]	- External Bus Controller CS_4 - CS_6 Outputs
+ * GPIO0[3]	- NAND FLASH Controller CE3 (NFCE3) Output
  * GPIO0[4]	- External Bus Controller Hold Input
  * GPIO0[5]	- External Bus Controller Priority Input
  * GPIO0[6]	- External Bus Controller HLDA Output
@@ -376,10 +367,10 @@
  */
 #define CFG_GPIO0_TCR		0xC0000000
 #define CFG_GPIO0_OSRL		0x50000000
-#define CFG_GPIO0_OSRH		0x00000055
+#define CFG_GPIO0_OSRH		0x02000055
 #define CFG_GPIO0_ISR1L		0x00000000
 #define CFG_GPIO0_ISR1H		0x00000055
-#define CFG_GPIO0_TSRL		0x00000000
+#define CFG_GPIO0_TSRL		0x02000000
 #define CFG_GPIO0_TSRH		0x00000055
 
 /*-----------------------------------------------------------------------
-- 
cgit v1.1


From a11c0b85dc3664bb3c1e781137118730c8f619ab Mon Sep 17 00:00:00 2001
From: Bartlomiej Sieka <tur@semihalf.com>
Date: Sun, 27 May 2007 16:51:48 +0200
Subject: Motion-PRO: Add LED support.

Signed-off-by: Jan Wrobel <wrr@semihalf.com>
Signed-off-by: Marian Balakowicz <m8@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
---
 include/configs/motionpro.h | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

(limited to 'include/configs')

diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index e6e0eb1..5c2b1cd 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -310,6 +310,28 @@
 
 
 /*
+ * Status LED configuration
+ */
+#define CONFIG_STATUS_LED		/* Status LED enabled */
+#define CONFIG_BOARD_SPECIFIC_LED
+
+#define ENABLE_GPIO_OUT		0x00000024
+#define LED_ON			0x00000010
+
+#ifndef __ASSEMBLY__
+/*
+ * In case of Motion-PRO, a LED is identified by its corresponding
+ * GPT Enable and Mode Select Register.
+ */
+typedef volatile unsigned long * led_id_t;
+
+extern void __led_init(led_id_t id, int state);
+extern void __led_toggle(led_id_t id);
+extern void __led_set(led_id_t id, int state);
+#endif /* __ASSEMBLY__ */
+
+
+/*
  * Environment settings
  */
 #define CFG_ENV_IS_IN_FLASH	1
-- 
cgit v1.1


From c99512d6bd3973f01ca2fc4896d829b46e68f150 Mon Sep 17 00:00:00 2001
From: Bartlomiej Sieka <tur@semihalf.com>
Date: Sun, 27 May 2007 16:53:43 +0200
Subject: MPC5xxx: Change names of defines related to IPB and PCI clocks.

Both CFG_PCISPEED_66 and CFG_IPBSPEED_133 are misnamed, as defining
them does not cause PCI or IPB clocks to run at the specified speed.
Instead, they configure divisors used to calculate said clocks. This
patch renames the defines according to their real function.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
---
 include/configs/BC3450.h    | 12 ++++++------
 include/configs/IceCube.h   |  4 ++--
 include/configs/PM520.h     |  2 +-
 include/configs/TB5200.h    | 12 ++++++------
 include/configs/TOP5200.h   |  2 +-
 include/configs/TQM5200.h   | 12 ++++++------
 include/configs/Total5200.h |  2 +-
 include/configs/aev.h       | 12 ++++++------
 include/configs/canmb.h     |  2 +-
 include/configs/cpci5200.h  |  2 +-
 include/configs/hmi1001.h   |  2 +-
 include/configs/inka4x0.h   |  2 +-
 include/configs/mcc200.h    |  2 +-
 include/configs/motionpro.h |  4 ++--
 include/configs/o2dnt.h     | 12 ++++++------
 include/configs/pf5200.h    |  2 +-
 include/configs/smmaco4.h   | 12 ++++++------
 include/configs/spieval.h   | 12 ++++++------
 include/configs/uc101.h     |  2 +-
 include/configs/v38b.h      |  2 +-
 20 files changed, 57 insertions(+), 57 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h
index 5b54f30..bc30977 100644
--- a/include/configs/BC3450.h
+++ b/include/configs/BC3450.h
@@ -282,17 +282,17 @@
 /*
  * IPB Bus clocking configuration.
  */
-#define CFG_IPBSPEED_133		/* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
 /*
  * PCI Bus clocking configuration
  *
  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet
- * hasn't been tested with a IPB Bus Clock of 66 MHz.
+ * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
+ *  of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
  */
-#if defined(CFG_IPBSPEED_133)
-# define CFG_PCISPEED_66			/* define for 66MHz speed */
+#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
+# define CFG_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
 #endif
 
 /*
@@ -488,7 +488,7 @@
 
 #define CFG_BOOTCS_START	CFG_FLASH_BASE
 #define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#ifdef CFG_PCISPEED_66
+#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
 # define CFG_BOOTCS_CFG		0x0008DF30	/* for pci_clk	= 66 MHz */
 #else
 # define CFG_BOOTCS_CFG		0x0004DF30	/* for pci_clk = 33 MHz	 */
diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h
index 0d38254..09f8d20 100644
--- a/include/configs/IceCube.h
+++ b/include/configs/IceCube.h
@@ -167,9 +167,9 @@
  * IPB Bus clocking configuration.
  */
 #if defined(CONFIG_LITE5200B)
-#define CFG_IPBSPEED_133 	/* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK 	/* define for 133MHz speed */
 #else
-#undef CFG_IPBSPEED_133   	/* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK   	/* define for 133MHz speed */
 #endif
 #endif /* CONFIG_MPC5200 */
 
diff --git a/include/configs/PM520.h b/include/configs/PM520.h
index 9c241e6..7d91a01 100644
--- a/include/configs/PM520.h
+++ b/include/configs/PM520.h
@@ -160,7 +160,7 @@
 /*
  * IPB Bus clocking configuration.
  */
-#undef CFG_IPBSPEED_133   		/* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK   		/* define for 133MHz speed */
 #endif
 /*
  * I2C configuration
diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h
index 8a6e5a6..b42cfb6 100644
--- a/include/configs/TB5200.h
+++ b/include/configs/TB5200.h
@@ -200,17 +200,17 @@
 /*
  * IPB Bus clocking configuration.
  */
-#define CFG_IPBSPEED_133		/* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
-#if defined(CFG_IPBSPEED_133)
+#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
 /*
  * PCI Bus clocking configuration
  *
  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
- * been tested with a IPB Bus Clock of 66 MHz.
+ * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock 
+ * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
  */
-#define CFG_PCISPEED_66			/* define for 66MHz speed */
+#define CFG_PCICLK_EQUALS_IPBCLK_DIV2		/* define for 66MHz speed */
 #endif
 
 /*
@@ -432,7 +432,7 @@
 
 #define CFG_BOOTCS_START	CFG_FLASH_BASE
 #define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#ifdef CFG_PCISPEED_66
+#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
 #define CFG_BOOTCS_CFG		0x0008DF30 /* for pci_clk  = 66 MHz */
 #else
 #define CFG_BOOTCS_CFG		0x0004DF30 /* for pci_clk = 33 MHz */
diff --git a/include/configs/TOP5200.h b/include/configs/TOP5200.h
index f41dbd0..1cc9ce9 100644
--- a/include/configs/TOP5200.h
+++ b/include/configs/TOP5200.h
@@ -186,7 +186,7 @@
 /*
  * IPB Bus clocking configuration.
  */
-#undef CFG_IPBSPEED_133   		/* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK   		/* define for 133MHz speed */
 
 /*
  * I2C configuration
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index 7069b35..7935593 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -269,17 +269,17 @@
 /*
  * IPB Bus clocking configuration.
  */
-#define CFG_IPBSPEED_133		/* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
-#if defined(CFG_IPBSPEED_133) && !defined(CONFIG_CAM5200)
+#if defined(CFG_IPBCLK_EQUALS_XLBCLK) && !defined(CONFIG_CAM5200)
 /*
  * PCI Bus clocking configuration
  *
  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
- * been tested with a IPB Bus Clock of 66 MHz.
+ * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock of
+ * 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
  */
-#define CFG_PCISPEED_66			/* define for 66MHz speed */
+#define CFG_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
 #endif
 
 /*
@@ -594,7 +594,7 @@
 
 #define CFG_BOOTCS_START	CFG_FLASH_BASE
 #define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#ifdef CFG_PCISPEED_66
+#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
 #define CFG_BOOTCS_CFG		0x0008DF30 /* for pci_clk  = 66 MHz */
 #else
 #define CFG_BOOTCS_CFG		0x0004DF30 /* for pci_clk = 33 MHz */
diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h
index 8175703..d8686dd 100644
--- a/include/configs/Total5200.h
+++ b/include/configs/Total5200.h
@@ -183,7 +183,7 @@
 /*
  * IPB Bus clocking configuration.
  */
-#undef CFG_IPBSPEED_133   		/* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK   		/* define for 133MHz speed */
 #endif
 
 /*
diff --git a/include/configs/aev.h b/include/configs/aev.h
index 8d9f0a1..6c2a360 100644
--- a/include/configs/aev.h
+++ b/include/configs/aev.h
@@ -166,17 +166,17 @@
 /*
  * IPB Bus clocking configuration.
  */
-#define CFG_IPBSPEED_133		/* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
-#if defined(CFG_IPBSPEED_133)
+#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
 /*
  * PCI Bus clocking configuration
  *
  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
- * been tested with a IPB Bus Clock of 66 MHz.
+ * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock 
+ * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
  */
-#define CFG_PCISPEED_66			/* define for 66MHz speed */
+#define CFG_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
 #endif
 
 /*
@@ -362,7 +362,7 @@
 
 #define CFG_BOOTCS_START	CFG_FLASH_BASE
 #define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#ifdef CFG_PCISPEED_66
+#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
 #define CFG_BOOTCS_CFG		0x0008DF30 /* for pci_clk  = 66 MHz */
 #else
 #define CFG_BOOTCS_CFG		0x0004DF30 /* for pci_clk = 33 MHz */
diff --git a/include/configs/canmb.h b/include/configs/canmb.h
index 2c160a4..ec6d57e 100644
--- a/include/configs/canmb.h
+++ b/include/configs/canmb.h
@@ -111,7 +111,7 @@
 /*
  * IPB Bus clocking configuration.
  */
-#undef CFG_IPBSPEED_133   		/* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK   		/* define for 133MHz speed */
 
 /*
  * Flash configuration, expect one 16 Megabyte Bank at most
diff --git a/include/configs/cpci5200.h b/include/configs/cpci5200.h
index f9586fb..f5efcd9 100644
--- a/include/configs/cpci5200.h
+++ b/include/configs/cpci5200.h
@@ -179,7 +179,7 @@
 /*
  * IPB Bus clocking configuration.
  */
-#undef CFG_IPBSPEED_133		/* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 #endif
 /*
  * I2C configuration
diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h
index cfaf153..45a28c7 100644
--- a/include/configs/hmi1001.h
+++ b/include/configs/hmi1001.h
@@ -110,7 +110,7 @@
 /*
  * IPB Bus clocking configuration.
  */
-#undef CFG_IPBSPEED_133		/* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
 /*
  * I2C configuration
diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h
index 773d5d2..ad3cf06 100644
--- a/include/configs/inka4x0.h
+++ b/include/configs/inka4x0.h
@@ -147,7 +147,7 @@
 /*
  * IPB Bus clocking configuration.
  */
-#define CFG_IPBSPEED_133		/* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
 /*
  * Flash configuration
diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h
index f60973b..00d2e07 100644
--- a/include/configs/mcc200.h
+++ b/include/configs/mcc200.h
@@ -169,7 +169,7 @@
 /*
  * IPB Bus clocking configuration.
  */
-#define CFG_IPBSPEED_133		/* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
 /*
  * I2C configuration
diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index 5c2b1cd..358c380 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -160,9 +160,9 @@
 
 
 /*
- * Set IPB speed to 100MHz (yes, the #define is misnamed)
+ * Set IPB speed to 100MHz
  */
-#define CFG_IPBSPEED_133
+#define CFG_IPBCLK_EQUALS_XLBCLK
 
 
 /*
diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h
index 5c05a74..63d0da7 100644
--- a/include/configs/o2dnt.h
+++ b/include/configs/o2dnt.h
@@ -137,17 +137,17 @@
 /*
  * IPB Bus clocking configuration.
  */
-#define CFG_IPBSPEED_133		/* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
-#if defined(CFG_IPBSPEED_133)
+#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
 /*
  * PCI Bus clocking configuration
  *
  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
- * been tested with a IPB Bus Clock of 66 MHz.
+ * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
+ *  of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
  */
-#define CFG_PCISPEED_66			/* define for 66MHz speed */
+#define CFG_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
 #endif
 #endif
 
@@ -276,7 +276,7 @@
 #define CFG_BOOTCS_START	CFG_FLASH_BASE
 #define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
 
-#ifdef CFG_PCISPEED_66
+#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
 /*
  * For 66 MHz PCI clock additional Wait State is needed for CS0 (flash).
  */
diff --git a/include/configs/pf5200.h b/include/configs/pf5200.h
index fefdb3c..7151a9e 100644
--- a/include/configs/pf5200.h
+++ b/include/configs/pf5200.h
@@ -171,7 +171,7 @@
 /*
  * IPB Bus clocking configuration.
  */
-#undef CFG_IPBSPEED_133		/* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 #endif
 /*
  * I2C configuration
diff --git a/include/configs/smmaco4.h b/include/configs/smmaco4.h
index e106b3b..185c2d4 100644
--- a/include/configs/smmaco4.h
+++ b/include/configs/smmaco4.h
@@ -138,17 +138,17 @@
 /*
  * IPB Bus clocking configuration.
  */
-#define CFG_IPBSPEED_133		/* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
-#if defined(CFG_IPBSPEED_133)
+#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
 /*
  * PCI Bus clocking configuration
  *
  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
- * been tested with a IPB Bus Clock of 66 MHz.
+ * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
+ * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
  */
-#define CFG_PCISPEED_66			/* define for 66MHz speed */
+#define CFG_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
 #endif
 
 /*
@@ -357,7 +357,7 @@
 
 #define CFG_BOOTCS_START	CFG_FLASH_BASE
 #define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#ifdef CFG_PCISPEED_66
+#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
 #define CFG_BOOTCS_CFG		0x0008DF30 /* for pci_clk  = 66 MHz */
 #else
 #define CFG_BOOTCS_CFG		0x0004DF30 /* for pci_clk = 33 MHz */
diff --git a/include/configs/spieval.h b/include/configs/spieval.h
index f40dde2..fd138a5 100644
--- a/include/configs/spieval.h
+++ b/include/configs/spieval.h
@@ -219,17 +219,17 @@
 /*
  * IPB Bus clocking configuration.
  */
-#define CFG_IPBSPEED_133		/* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
-#if defined(CFG_IPBSPEED_133)
+#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
 /*
  * PCI Bus clocking configuration
  *
  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
- * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
- * been tested with a IPB Bus Clock of 66 MHz.
+ * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock 
+ * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
  */
-#define CFG_PCISPEED_66			/* define for 66MHz speed */
+#define CFG_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
 #endif
 
 /*
@@ -444,7 +444,7 @@
 
 #define CFG_BOOTCS_START	CFG_FLASH_BASE
 #define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#ifdef CFG_PCISPEED_66
+#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
 #define CFG_BOOTCS_CFG		0x0008DF30 /* for pci_clk  = 66 MHz */
 #else
 #define CFG_BOOTCS_CFG		0x0004DF30 /* for pci_clk = 33 MHz */
diff --git a/include/configs/uc101.h b/include/configs/uc101.h
index 8cd8e9b..ff061ee 100644
--- a/include/configs/uc101.h
+++ b/include/configs/uc101.h
@@ -114,7 +114,7 @@
 /*
  * IPB Bus clocking configuration.
  */
-#define CFG_IPBSPEED_133		/* define for 133MHz speed */
+#define CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
 /*
  * I2C configuration
diff --git a/include/configs/v38b.h b/include/configs/v38b.h
index e19591d..0b7b19e 100644
--- a/include/configs/v38b.h
+++ b/include/configs/v38b.h
@@ -167,7 +167,7 @@
 /*
  * IPB Bus clocking configuration.
  */
-#undef CFG_IPBSPEED_133			/* define for 133MHz speed */
+#undef CFG_IPBCLK_EQUALS_XLBCLK			/* define for 133MHz speed */
 #endif
 
 /*
-- 
cgit v1.1


From c75e639630cc132dc19cd1ecda5922c0db0bfbba Mon Sep 17 00:00:00 2001
From: Bartlomiej Sieka <tur@semihalf.com>
Date: Sun, 27 May 2007 16:55:23 +0200
Subject: Motion-PRO: Add displaying of CPLD revision information during boot.

Signed-off-by: Jan Wrobel <wrr@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
---
 include/configs/motionpro.h | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'include/configs')

diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index 358c380..8ffcc4c 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -357,6 +357,12 @@ extern void __led_set(led_id_t id, int state);
 
 
 /*
+ * Motion-PRO's CPLD revision control register
+ */
+#define CPLD_REV_REGISTER	(CFG_CS2_START + 0x06)
+
+
+/*
  * Miscellaneous configurable options
  */
 #define CFG_LONGHELP			/* undef to save memory    */
-- 
cgit v1.1


From 93b78f534a6e708b4cf1a4ffb4d8438c67a007db Mon Sep 17 00:00:00 2001
From: Bartlomiej Sieka <tur@semihalf.com>
Date: Sun, 27 May 2007 16:57:15 +0200
Subject: Motion-PRO: Add support for the temperature sensor.

Signed-off-by: Piotr Kruszynski <ppk@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
---
 include/configs/motionpro.h | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

(limited to 'include/configs')

diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index 8ffcc4c..a4df64a 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -54,7 +54,8 @@
 				CFG_CMD_JFFS2	| \
 				CFG_CMD_I2C	| \
 				CFG_CMD_DATE	| \
-				CFG_CMD_EEPROM)
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_DTT)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
@@ -297,6 +298,7 @@
  * EEPROM configuration
  */
 #define CFG_I2C_EEPROM_ADDR_LEN		1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE	1	/* DTT driver needs this */
 #define CFG_EEPROM_PAGE_WRITE_BITS	3
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70
 #define CFG_I2C_MULTI_EEPROMS		1	/* 2 EEPROMs (addr:50,52) */
@@ -332,6 +334,13 @@ extern void __led_set(led_id_t id, int state);
 
 
 /*
+ * Temperature sensor
+ */
+#define CONFIG_DTT_LM75		1
+#define CONFIG_DTT_SENSORS	{ 0x49 }
+
+
+/*
  * Environment settings
  */
 #define CFG_ENV_IS_IN_FLASH	1
-- 
cgit v1.1


From c00125e07c1ebc125bab40e1e18bceed8be0c162 Mon Sep 17 00:00:00 2001
From: Bartlomiej Sieka <tur@semihalf.com>
Date: Sun, 27 May 2007 16:58:45 +0200
Subject: MPC5XXX, Motion-PRO: Fix PHY initialization problem.

After being reset in mpc5xxx_fec_init_phy(), PHY goes into FX mode, in which
networking does not function. This commit switches PHY to TX mode by clearing
the FX_SEL bit of Mode Control Register. It also reverses commit
008861a2f3ef2c062744d733787c7e530a1b8761, i.e., a temporary workaround.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
---
 include/configs/motionpro.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'include/configs')

diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index a4df64a..a7021b0 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -76,7 +76,7 @@
 #define CONFIG_MPC5xxx_FEC	1
 #define CONFIG_PHY_ADDR		0x2
 #define CONFIG_PHY_TYPE		0x79c874
-
+#define CONFIG_RESET_PHY_R	1
 
 /*
  * Autobooting
-- 
cgit v1.1


From 630ec84aef7228fc1dbfb38dec78541403a786cd Mon Sep 17 00:00:00 2001
From: Bartlomiej Sieka <tur@semihalf.com>
Date: Sun, 27 May 2007 17:03:37 +0200
Subject: Motion-PRO: Update EEPROM's page write bits and write delay.

Change EEPROM configuration according to the datasheet: "The 24C01A and 24C02A
have a page write capability of two bytes", and "This device offers fast (1ms)
byte write". Add 3ms of extra delay.

Signed-off-by: Piotr Kruszynski <ppk@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
---
 include/configs/motionpro.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index a7021b0..2c405b5 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -299,8 +299,8 @@
  */
 #define CFG_I2C_EEPROM_ADDR_LEN		1
 #define CFG_EEPROM_PAGE_WRITE_ENABLE	1	/* DTT driver needs this */
-#define CFG_EEPROM_PAGE_WRITE_BITS	3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70
+#define CFG_EEPROM_PAGE_WRITE_BITS	1	/* 2 bytes per write cycle */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	5	/* 2ms/cycle + 3ms extra */
 #define CFG_I2C_MULTI_EEPROMS		1	/* 2 EEPROMs (addr:50,52) */
 
 
-- 
cgit v1.1


From a26eabeec31746f06d309103690892805696e344 Mon Sep 17 00:00:00 2001
From: Bartlomiej Sieka <tur@semihalf.com>
Date: Sun, 27 May 2007 17:05:11 +0200
Subject: Motion-PRO: Change maximum console buffer size from 256 to 1024
 bytes.

Allow passing longer command line to the kernel - useful especially
for passing MTD partition layout.

Signed-off-by: Piotr Kruszynski <ppk@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
---
 include/configs/motionpro.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'include/configs')

diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index 2c405b5..bbd823a 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -376,7 +376,7 @@ extern void __led_set(led_id_t id, int state);
  */
 #define CFG_LONGHELP			/* undef to save memory    */
 #define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size */
 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
 #define CFG_MAXARGS		16		/* max number of command args */
 #define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
-- 
cgit v1.1


From 4520fd4d2c450da49637216aa0e53739b61c60ac Mon Sep 17 00:00:00 2001
From: Bartlomiej Sieka <tur@semihalf.com>
Date: Sun, 27 May 2007 17:06:36 +0200
Subject: Motion-PRO: Add support for redundant environment.

Enable redundant environment, add a MTD partition for it; also add env.
variable command for passing MTD partitions to the kernel command line.

Signed-off-by: Piotr Kruszynski <ppk@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
---
 include/configs/motionpro.h | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

(limited to 'include/configs')

diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index bbd823a..8170ccb 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -125,6 +125,7 @@
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 		"nfsroot=$(serverip):$(rootpath)\0"			\
 	"fat_args=setenv bootargs rw\0"					\
+	"addmtd=setenv bootargs $(bootargs) $(mtdparts)\0"		\
 	"addip=setenv bootargs $(bootargs) "				\
 		"ip=$(ipaddr):$(serverip):$(gatewayip):"		\
 		"$(netmask):$(hostname):$(netdev):off panic=1 "		\
@@ -269,7 +270,8 @@
 #define MTDIDS_DEFAULT		"nor0=motionpro-0"
 #define MTDPARTS_DEFAULT	"mtdparts=motionpro-0:"			  \
 					"13m(fs),2m(kernel),256k(uboot)," \
-					"64k(env),64k(dtb),-(user_data)"
+					"64k(env),64k(redund_env),64k(dtb)," \
+					"-(user_data)"
 
 /*
  * IDE/ATA configuration
@@ -349,6 +351,9 @@ extern void __led_set(led_id_t id, int state);
 #define CFG_ENV_SIZE		0x1000
 #define CFG_ENV_SECT_SIZE	0x10000
 
+/* Configuration of redundant environment */
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
 
 /*
  * Pin multiplexing configuration
-- 
cgit v1.1


From 7049288fb1f16f1b317140226cdebd07bd416395 Mon Sep 17 00:00:00 2001
From: Bartlomiej Sieka <tur@semihalf.com>
Date: Sun, 27 May 2007 17:26:46 +0200
Subject: Motion-PRO: Code cleanup, fix of a typo in OF_STDOUT_PATH.

Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
---
 include/configs/motionpro.h | 32 ++++++++++++++++----------------
 1 file changed, 16 insertions(+), 16 deletions(-)

(limited to 'include/configs')

diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index 8170ccb..e3899a5 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -117,27 +117,27 @@
 	"fdt_file=/tftpboot/motionpro/motionpro.dtb\0"			\
 	"ramdisk_file=/tftpboot/motionpro/uRamdisk\0"			\
 	"multi_image_file=kernel+initrd+dtb.img\0"			\
-	"load=tftp $(u-boot_addr) $(u-boot)\0"				\
+	"load=tftp ${u-boot_addr} ${u-boot}\0"				\
 	"update=prot off fff00000 fff3ffff; era fff00000 fff3ffff; "	\
-		"cp.b $(u-boot_addr) fff00000 $(filesize);"		\
+		"cp.b ${u-boot_addr} fff00000 ${filesize};"		\
 		"prot on fff00000 fff3ffff\0"				\
 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=$(serverip):$(rootpath)\0"			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
 	"fat_args=setenv bootargs rw\0"					\
-	"addmtd=setenv bootargs $(bootargs) $(mtdparts)\0"		\
-	"addip=setenv bootargs $(bootargs) "				\
-		"ip=$(ipaddr):$(serverip):$(gatewayip):"		\
-		"$(netmask):$(hostname):$(netdev):off panic=1 "		\
-		"console=$(console)\0"					\
-	"net_nfs=tftp $(kernel_addr) $(bootfile); "			\
-		"tftp $(fdt_addr) $(fdt_file); run nfsargs addip; "	\
-		"bootm $(kernel_addr) - $(fdt_addr)\0"			\
-	"net_self=tftp $(kernel_addr) $(bootfile); "			\
-		"tftp $(fdt_addr) $(fdt_file); "			\
-		"tftp $(ramdisk_addr) $(ramdisk_file); "		\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:"		\
+		"${netmask}:${hostname}:${netdev}:off panic=1 "		\
+		"console=${console}\0"					\
+	"net_nfs=tftp ${kernel_addr} ${bootfile}; "			\
+		"tftp ${fdt_addr} ${fdt_file}; run nfsargs addip; "	\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
+	"net_self=tftp ${kernel_addr} ${bootfile}; "			\
+		"tftp ${fdt_addr} ${fdt_file}; "			\
+		"tftp ${ramdisk_addr} ${ramdisk_file}; "		\
 		"run ramargs addip; "					\
-		"bootm $(kernel_addr) $(ramdisk_addr) $(fdt_addr)\0"	\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
 	"fat_multi=run fat_args addip; fatload ide 0:1 "		\
 		"${multi_image_addr} ${multi_image_file}; "		\
 		"bootm ${multi_image_addr}\0"				\
@@ -418,6 +418,6 @@ extern void __led_set(led_id_t id, int state);
 #define OF_CPU			"PowerPC,5200@0"
 #define OF_SOC			"soc5200@f0000000"
 #define OF_TBCLK		(bd->bi_busfreq / 4)
-#define OF_STDOUT_PAT		"/soc5200@f0000000/serial@2000"
+#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"
 
 #endif /* __CONFIG_H */
-- 
cgit v1.1