From 4b6067ae9ddd2113df18735e4f10d8d40fcb1c1e Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Fri, 5 Jun 2015 15:29:02 +0530 Subject: powerpc/T104xD4RDB: Add T104xD4RDB boards support T1040D4RDB is a Freescale reference board that hosts the T1040 SoC. T1040D4RDB is re-designed T1040RDB board with following changes : - Support of DDR4 memory - Support of 0x66 serdes protocol which can support following interfaces - 2 RGMII's on DTSEC4, DTSEC5 - 1 SGMII on DTSEC3 - Support of QE-TDM Similarily T1042D4RDB is a Freescale reference board that hosts the T1040 SoC. T1042D4RDB is re-designed T1042RDB board with following changes : - Support of DDR4 memory - Support for 0x86 serdes protocol which can support following interfaces - 2 RGMII's on DTSEC4, DTSEC5 - 3 SGMII on DTSEC1, DTSEC2 & DTSEC3 - Support of DIU Signed-off-by: Priyanka Jain Signed-off-by: Codrin Ciubotariu Signed-off-by: Wang Dongsheng Reviewed-by: York Sun --- include/configs/T104xRDB.h | 64 ++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 54 insertions(+), 10 deletions(-) (limited to 'include/configs') diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 16d2e0e..e88cad6 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -29,6 +29,14 @@ #ifdef CONFIG_T1042RDB #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg #endif +#ifdef CONFIG_T1040D4RDB +#define CONFIG_SYS_FSL_PBL_RCW \ +$(SRCTREE)/board/freescale/t104xrdb/t1040d4_rcw.cfg +#endif +#ifdef CONFIG_T1042D4RDB +#define CONFIG_SYS_FSL_PBL_RCW \ +$(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg +#endif #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT #define CONFIG_SPL_ENV_SUPPORT @@ -220,7 +228,9 @@ #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_DDR_SPD +#ifndef CONFIG_SYS_FSL_DDR4 #define CONFIG_SYS_FSL_DDR3 +#endif #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x51 @@ -278,8 +288,23 @@ #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ #define CPLD_LBMAP_RESET 0xFF #define CPLD_LBMAP_SHIFT 0x03 -#ifdef CONFIG_T1042RDB_PI + +#if defined(CONFIG_T1042RDB_PI) #define CPLD_DIU_SEL_DFP 0x80 +#elif defined(CONFIG_T1042D4RDB) +#define CPLD_DIU_SEL_DFP 0xc0 +#endif + +#if defined(CONFIG_T1040D4RDB) +#define CPLD_INT_MASK_ALL 0xFF +#define CPLD_INT_MASK_THERM 0x80 +#define CPLD_INT_MASK_DVI_DFP 0x40 +#define CPLD_INT_MASK_QSGMII1 0x20 +#define CPLD_INT_MASK_QSGMII2 0x10 +#define CPLD_INT_MASK_SGMI1 0x08 +#define CPLD_INT_MASK_SGMI2 0x04 +#define CPLD_INT_MASK_TDMR1 0x02 +#define CPLD_INT_MASK_TDMR2 0x01 #endif #define CONFIG_SYS_CPLD_BASE 0xffdf0000 @@ -447,7 +472,7 @@ #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#ifdef CONFIG_T1042RDB_PI +#if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T1042D4RDB) /* Video */ #define CONFIG_FSL_DIU_FB @@ -492,11 +517,11 @@ /* I2C bus multiplexer */ #define I2C_MUX_PCA_ADDR 0x70 -#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) +#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) #define I2C_MUX_CH_DEFAULT 0x8 #endif -#ifdef CONFIG_T1042RDB_PI +#if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XD4RDB) /* LDI/DVI Encoder for display */ #define CONFIG_SYS_I2C_LDI_ADDR 0x38 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 @@ -664,7 +689,7 @@ #define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_PME -#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) +#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) #define CONFIG_QE #define CONFIG_U_QE #endif @@ -693,7 +718,7 @@ #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #endif -#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) +#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) #if defined(CONFIG_SPIFLASH) #define CONFIG_SYS_QE_FW_ADDR 0x130000 #elif defined(CONFIG_SDCARD) @@ -718,17 +743,32 @@ #ifdef CONFIG_FMAN_ENET #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) -#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 +#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 +#elif defined(CONFIG_T1040D4RDB) || defined(CONFIG_T1042D4RDB) +#define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 +#define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 +#define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 +#endif + +#ifdef CONFIG_T104XD4RDB +#define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 +#define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 +#else +#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 +#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 #endif -#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 -#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 /* Enable VSC9953 L2 Switch driver on T1040 SoC */ -#ifdef CONFIG_T1040RDB +#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB) #define CONFIG_VSC9953 #define CONFIG_VSC9953_CMD +#ifdef CONFIG_T1040RDB #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 +#else +#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 +#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c +#endif #endif #define CONFIG_MII /* MII PHY management */ @@ -836,6 +876,10 @@ #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" #elif defined(CONFIG_T1042RDB) #define FDTFILE "t1042rdb/t1042rdb.dtb" +#elif defined(CONFIG_T1040D4RDB) +#define FDTFILE "t1042rdb/t1040d4rdb.dtb" +#elif defined(CONFIG_T1042D4RDB) +#define FDTFILE "t1042rdb/t1042d4rdb.dtb" #endif #ifdef CONFIG_FSL_DIU_FB -- cgit v1.1