From da419027afe8336284f5db9867a880dfb3b3ab26 Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Fri, 31 Oct 2014 13:43:44 +0800 Subject: arm: ls102xa: Update PCIe dts node status The patch changes PCIe dts node status to 'disabled' if the corresponding controller is disabled according to serdes protocol. Signed-off-by: Minghuan Lian Reviewed-by: York Sun --- include/configs/ls1021aqds.h | 8 ++++++++ include/configs/ls1021atwr.h | 7 +++++++ 2 files changed, 15 insertions(+) (limited to 'include/configs') diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 48e10ec..a8383f1 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -341,6 +341,14 @@ unsigned long get_board_ddr_clk(void); #endif #endif + +/* PCIe */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ +#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" + #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP #define CONFIG_CMD_MII diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 3eac7ee..b5ecde3 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -236,6 +236,13 @@ #define CONFIG_HAS_ETH2 #endif +/* PCIe */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ +#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" + #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP #define CONFIG_CMD_MII -- cgit v1.1 From 86949c2b7c94542c20767c405fc458346bd3975b Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Wed, 3 Dec 2014 15:00:47 +0800 Subject: arm: ls102xa: Add SD boot support for LS1021AQDS board This patch adds SD boot support for LS1021AQDS board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from SD card to DDR, finally SPL transfer control to u-boot. Signed-off-by: Alison Wang Signed-off-by: Jason Jin Reviewed-by: York Sun --- include/configs/ls1021aqds.h | 45 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) (limited to 'include/configs') diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index a8383f1..4a2e609 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -40,6 +40,39 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg +#endif + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 + +#define CONFIG_SPL_TEXT_BASE 0x10000000 +#define CONFIG_SPL_MAX_SIZE 0x1a000 +#define CONFIG_SPL_STACK 0x1001d000 +#define CONFIG_SPL_PAD_TO 0x1c000 +#define CONFIG_SYS_TEXT_BASE 0x82000000 + +#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_MONITOR_LEN 0x80000 +#endif + #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0x67f80000 #endif @@ -356,6 +389,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMDLINE_TAG #define CONFIG_CMDLINE_EDITING + #define CONFIG_CMD_IMLS #define CONFIG_HWCONFIG @@ -404,17 +438,28 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif /* * Environment */ #define CONFIG_ENV_OVERWRITE +#if defined(CONFIG_SD_BOOT) +#define CONFIG_ENV_OFFSET 0x100000 +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif #define CONFIG_OF_LIBFDT #define CONFIG_OF_BOARD_SETUP -- cgit v1.1 From 8415bb68c8c2e0430f58fc349352a565bddf286e Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Wed, 3 Dec 2014 15:00:48 +0800 Subject: arm: ls102xa: Add SD boot support for LS1021ATWR board This patch adds SD boot support for LS1021ATWR board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from SD card to DDR, finally SPL transfer control to u-boot. Signed-off-by: Chen Lu Signed-off-by: Alison Wang Signed-off-by: Jason Jin Reviewed-by: York Sun --- include/configs/ls1021atwr.h | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) (limited to 'include/configs') diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index b5ecde3..9a54322 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -35,6 +35,38 @@ #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 100000000 +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg +#endif + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 + +#define CONFIG_SPL_TEXT_BASE 0x10000000 +#define CONFIG_SPL_MAX_SIZE 0x1a000 +#define CONFIG_SPL_STACK 0x1001d000 +#define CONFIG_SPL_PAD_TO 0x1c000 +#define CONFIG_SYS_TEXT_BASE 0x82000000 + +#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_MONITOR_LEN 0x80000 +#endif + #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0x67f80000 #endif @@ -250,6 +282,7 @@ #define CONFIG_CMDLINE_TAG #define CONFIG_CMDLINE_EDITING + #define CONFIG_CMD_IMLS #define CONFIG_HWCONFIG @@ -295,7 +328,11 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif #define CONFIG_SYS_QE_FW_ADDR 0x67f40000 @@ -304,10 +341,17 @@ */ #define CONFIG_ENV_OVERWRITE +#if defined(CONFIG_SD_BOOT) +#define CONFIG_ENV_OFFSET 0x100000 +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x20000 +#else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE 0x20000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif #define CONFIG_OF_LIBFDT #define CONFIG_OF_BOARD_SETUP -- cgit v1.1 From 8251ed2323bf6594560a3c0a620f4742f8c024dc Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Tue, 9 Dec 2014 17:37:34 +0800 Subject: arm: ls1021a: Add CONFIG_DOS_PARTITION and CONFIG_CMD_FAT support This patch will fix the bug that the partitions on the SD card could not be accessed and add the support for the FAT fs. Signed-off-by: Alison Wang Reviewed-by: York Sun --- include/configs/ls1021aqds.h | 3 +++ include/configs/ls1021atwr.h | 3 +++ 2 files changed, 6 insertions(+) (limited to 'include/configs') diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 4a2e609..df6843c 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -312,6 +312,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_FSL_ESDHC #define CONFIG_GENERIC_MMC +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + /* * USB */ diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 9a54322..aa9ec72 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -212,6 +212,9 @@ #define CONFIG_FSL_ESDHC #define CONFIG_GENERIC_MMC +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + /* * Video */ -- cgit v1.1 From 4c59ab9cfbdd34f5ef1e960470accdc63e2483c1 Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Tue, 9 Dec 2014 17:37:49 +0800 Subject: arm: ls102xa: Fix SD/NAND/QSPI boot defination error for QE support The SD/NAND/QSPI boot definations are wrong for QE support, this patch is to fix this error. Signed-off-by: Alison Wang Reviewed-by: York Sun --- include/configs/ls1021aqds.h | 3 ++- include/configs/ls1021atwr.h | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'include/configs') diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index df6843c..4496871 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -104,7 +104,8 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_FSL_CAAM /* Enable CAAM */ -#if !defined(CONFIG_SDCARD) && !defined(CONFIG_NAND) && !defined(CONFIG_SPI) +#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ + !defined(CONFIG_QSPI_BOOT) #define CONFIG_U_QE #endif diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index aa9ec72..972becd 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -82,7 +82,8 @@ #define CONFIG_FSL_CAAM /* Enable CAAM */ -#if !defined(CONFIG_SDCARD) && !defined(CONFIG_NAND) && !defined(CONFIG_SPI) +#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ + !defined(CONFIG_QSPI_BOOT) #define CONFIG_U_QE #endif -- cgit v1.1 From d612f0ab34b27be4ad50b1236fbd6c84450997f1 Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Tue, 9 Dec 2014 17:38:02 +0800 Subject: arm: ls102xa: Add QSPI boot support for LS1021AQDS/TWR board This patch adds QSPI boot support for LS1021AQDS/TWR board. The QSPI boot image need to be programmed into the QSPI flash first. Then the booting will start from QSPI memory space. Signed-off-by: Alison Wang Reviewed-by: York Sun --- include/configs/ls1021aqds.h | 34 ++++++++++++++++++++++++++++++++++ include/configs/ls1021atwr.h | 28 ++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+) (limited to 'include/configs') diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 4496871..6f8b43f 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -37,8 +37,14 @@ unsigned long get_board_sys_clk(void); unsigned long get_board_ddr_clk(void); #endif +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 +#define CONFIG_QIXIS_I2C_ACCESS +#else #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() +#endif #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg @@ -73,6 +79,11 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_MONITOR_LEN 0x80000 #endif +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_SYS_TEXT_BASE 0x40010000 +#define CONFIG_SYS_NO_FLASH +#endif + #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0x67f80000 #endif @@ -112,6 +123,7 @@ unsigned long get_board_ddr_clk(void); /* * IFC Definitions */ +#ifndef CONFIG_QSPI_BOOT #define CONFIG_FSL_IFC #define CONFIG_SYS_FLASH_BASE 0x60000000 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE @@ -204,6 +216,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#endif /* * QIXIS Definitions @@ -316,6 +329,18 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION +/* QSPI */ +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_FSL_QSPI +#define QSPI0_AMBA_BASE 0x40000000 +#define FSL_QSPI_FLASH_SIZE (1 << 24) +#define FSL_QSPI_FLASH_NUM 2 + +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#endif + /* * USB */ @@ -394,7 +419,11 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMDLINE_TAG #define CONFIG_CMDLINE_EDITING +#ifdef CONFIG_QSPI_BOOT +#undef CONFIG_CMD_IMLS +#else #define CONFIG_CMD_IMLS +#endif #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 @@ -458,6 +487,11 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 +#elif defined(CONFIG_QSPI_BOOT) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 972becd..a3271fe 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -67,6 +67,11 @@ #define CONFIG_SYS_MONITOR_LEN 0x80000 #endif +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_SYS_TEXT_BASE 0x40010000 +#define CONFIG_SYS_NO_FLASH +#endif + #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0x67f80000 #endif @@ -90,6 +95,7 @@ /* * IFC Definitions */ +#ifndef CONFIG_QSPI_BOOT #define CONFIG_FSL_IFC #define CONFIG_SYS_FLASH_BASE 0x60000000 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE @@ -133,6 +139,7 @@ #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS #define CONFIG_SYS_WRITE_SWAPPED_DATA +#endif /* CPLD */ @@ -216,6 +223,18 @@ #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION +/* QSPI */ +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_FSL_QSPI +#define QSPI0_AMBA_BASE 0x40000000 +#define FSL_QSPI_FLASH_SIZE (1 << 24) +#define FSL_QSPI_FLASH_NUM 2 + +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#endif + /* * Video */ @@ -287,7 +306,11 @@ #define CONFIG_CMDLINE_TAG #define CONFIG_CMDLINE_EDITING +#ifdef CONFIG_QSPI_BOOT +#undef CONFIG_CMD_IMLS +#else #define CONFIG_CMD_IMLS +#endif #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 @@ -350,6 +373,11 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x20000 +#elif defined(CONFIG_QSPI_BOOT) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET 0x100000 +#define CONFIG_ENV_SECT_SIZE 0x10000 #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -- cgit v1.1 From 8ab967b6c6007adbd30e58dfa9ef69154a351484 Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Tue, 9 Dec 2014 17:38:14 +0800 Subject: arm: ls102xa: Add NAND boot support for LS1021AQDS board This patch adds NAND boot support for LS1021AQDS board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from NAND flash to DDR, finally SPL transfer control to u-boot. Signed-off-by: Prabhakar Kushwaha Signed-off-by: Alison Wang Reviewed-by: York Sun --- include/configs/ls1021aqds.h | 72 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) (limited to 'include/configs') diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 6f8b43f..536d9f3 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -84,6 +84,39 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NO_FLASH #endif +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT + +#define CONFIG_SPL_TEXT_BASE 0x10000000 +#define CONFIG_SPL_MAX_SIZE 0x1a000 +#define CONFIG_SPL_STACK 0x1001d000 +#define CONFIG_SPL_PAD_TO 0x1c000 +#define CONFIG_SYS_TEXT_BASE 0x82000000 + +#define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) +#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_MONITOR_LEN 0x80000 +#endif + #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0x67f80000 #endif @@ -261,6 +294,40 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_FPGA_FTIM3 0x0 #endif +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT +#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR +#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK +#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR +#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 +#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 +#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 +#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#else #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK @@ -293,6 +360,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#endif /* * Serial Port @@ -492,6 +560,10 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ #define CONFIG_ENV_SECT_SIZE 0x10000 +#elif defined(CONFIG_NAND_BOOT) +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -- cgit v1.1 From 73a1cb27c0d9e93d97cd7a344fd341f638ba3a2a Mon Sep 17 00:00:00 2001 From: Xiubo Li Date: Fri, 21 Nov 2014 17:40:55 +0800 Subject: ARM: HYP/non-sec: Fix the ARCH Timer frequency setting. For some SoCs, the system clock frequency may not equal to the ARCH Timer's frequency. This patch uses the CONFIG_TIMER_CLK_FREQ instead of CONFIG_SYS_CLK_FREQ, then the system clock macro and arch timer macor could be set separately and without interfering each other. Signed-off-by: Xiubo Li Reviewed-by: York Sun --- include/configs/sun7i.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/configs') diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h index f6b1b3e..4426d24 100644 --- a/include/configs/sun7i.h +++ b/include/configs/sun7i.h @@ -25,6 +25,7 @@ #define CONFIG_ARMV7_PSCI 1 #define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE #define CONFIG_SYS_CLK_FREQ 24000000 +#define CONFIG_SYS_TIMER_CLK_FREQ CONFIG_SYS_CLK_FREQ /* * Include common sunxi configuration where most the settings are -- cgit v1.1 From 1a2826f6e02d0d3ec97b77b5b13c13d2ac27fb9d Mon Sep 17 00:00:00 2001 From: Xiubo Li Date: Fri, 21 Nov 2014 17:40:57 +0800 Subject: ls102xa: changing a few targets' configurations. Enable hypervisors utilizing the ARMv7 virtualization extension on the LS1021A-QDS/TWR boards with the A7 core tile, we add the required configuration variable. Signed-off-by: Xiubo Li Reviewed-by: York Sun --- include/configs/ls1021aqds.h | 7 +++++++ include/configs/ls1021atwr.h | 7 +++++++ 2 files changed, 14 insertions(+) (limited to 'include/configs') diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 536d9f3..704c349 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -493,6 +493,13 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_IMLS #endif +#define CONFIG_ARMV7_NONSEC +#define CONFIG_ARMV7_VIRT +#define CONFIG_PEN_ADDR_BIG_ENDIAN +#define CONFIG_SMP_PEN_ADDR 0x01ee0200 +#define CONFIG_TIMER_CLK_FREQ 12500000 +#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR + #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index a3271fe..809e80f 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -312,6 +312,13 @@ #define CONFIG_CMD_IMLS #endif +#define CONFIG_ARMV7_NONSEC +#define CONFIG_ARMV7_VIRT +#define CONFIG_PEN_ADDR_BIG_ENDIAN +#define CONFIG_SMP_PEN_ADDR 0x01ee0200 +#define CONFIG_TIMER_CLK_FREQ 12500000 +#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR + #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 -- cgit v1.1 From e87f3b308c454f6e78b02da857936c7d012c385b Mon Sep 17 00:00:00 2001 From: Xiubo Li Date: Fri, 21 Nov 2014 17:40:58 +0800 Subject: ARM: ls102xa: allow all the peripheral access permission as R/W. The Central Security Unit (CSU) allows secure world software to change the default access control policies of peripherals/bus slaves, determining which bus masters may access them. This allows peripherals to be separated into distinct security domains. Combined with SMMU configuration of the system masters privileges, these features provide protection against indirect unauthorized access to data. For now we configure all the peripheral access permissions as R/W. Signed-off-by: Xiubo Li Reviewed-by: York Sun --- include/configs/ls1021aqds.h | 1 + include/configs/ls1021atwr.h | 1 + 2 files changed, 2 insertions(+) (limited to 'include/configs') diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 704c349..7391882 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -496,6 +496,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_ARMV7_NONSEC #define CONFIG_ARMV7_VIRT #define CONFIG_PEN_ADDR_BIG_ENDIAN +#define CONFIG_LS102XA_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define CONFIG_TIMER_CLK_FREQ 12500000 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 809e80f..171346b 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -315,6 +315,7 @@ #define CONFIG_ARMV7_NONSEC #define CONFIG_ARMV7_VIRT #define CONFIG_PEN_ADDR_BIG_ENDIAN +#define CONFIG_LS102XA_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define CONFIG_TIMER_CLK_FREQ 12500000 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR -- cgit v1.1 From 660673af4fd10c544ceeedeb524ba92c27dbc586 Mon Sep 17 00:00:00 2001 From: Xiubo Li Date: Fri, 21 Nov 2014 17:40:59 +0800 Subject: ARM: ls102xa: Setting device's stream id for SMMUs. LS1 has 4 SMMUs for address translation of the masters. All the SMMUs' stream IDs are 8-bit. The address translation depends on the stream ID of the incoming transaction. Each master has unique stream ID assigned to it and is configurable through SCFG registers. The stream ID for the masters is identical and share the same register field of STREAM ID registers. Signed-off-by: Xiubo Li Reviewed-by: York Sun --- include/configs/ls1021aqds.h | 2 ++ include/configs/ls1021atwr.h | 2 ++ 2 files changed, 4 insertions(+) (limited to 'include/configs') diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 7391882..8dc04f2 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -536,6 +536,8 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_LOAD_ADDR 0x82000000 +#define CONFIG_LS102XA_STREAM_ID + /* * Stack sizes * The stack sizes are set up in start.S using the settings below diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 171346b..66954d0 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -352,6 +352,8 @@ #define CONFIG_SYS_LOAD_ADDR 0x82000000 +#define CONFIG_LS102XA_STREAM_ID + /* * Stack sizes * The stack sizes are set up in start.S using the settings below -- cgit v1.1 From d0419f400af6f4bbe5c4ee5c97f6fbbdedec6cf3 Mon Sep 17 00:00:00 2001 From: Xiubo Li Date: Thu, 11 Dec 2014 11:15:26 -0800 Subject: ARM: HYP/non-sec: Fix the ARCH Timer frequency setting for sun7i Earlier commit 73a1cb27 mistakenly used CONFIG_SYS_TIMER_CLK_FREQ. It should be CONFIG_TIMER_CLK_FREQ. Signed-off-by: Xiubo Li [York Sun: This is the difference between two patch versions] Reviewed-by: York Sun --- include/configs/sun7i.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h index 4426d24..ccec50c 100644 --- a/include/configs/sun7i.h +++ b/include/configs/sun7i.h @@ -25,7 +25,7 @@ #define CONFIG_ARMV7_PSCI 1 #define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE #define CONFIG_SYS_CLK_FREQ 24000000 -#define CONFIG_SYS_TIMER_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_TIMER_CLK_FREQ CONFIG_SYS_CLK_FREQ /* * Include common sunxi configuration where most the settings are -- cgit v1.1