From ebcaf966ed64b94ff3cd384ca9b3906a6ae0713e Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 30 Oct 2014 09:33:13 +0100 Subject: arm: socfpga: Add I2C support to SoCFPGA This patch adds I2C support for the SoCFPGA. Using the designware I2C controller driver. It supports all 4 I2C busses on the SoCFPGA. The designware I2C driver has now been converted to the CONFIG_SYS_I2C framework. So lets enable it on SoCFPGA. Tested on SoCrates. Signed-off-by: Stefan Roese Cc: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Vince Bridgers Cc: Pavel Machek Cc: Heiko Schocher --- include/configs/socfpga_common.h | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'include/configs/socfpga_common.h') diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 83a1bcd..f7b314d 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -141,6 +141,33 @@ #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ #endif + /* + * I2C support + */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DW +#define CONFIG_SYS_I2C_BUS_MAX 4 +#define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS +#define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS +#define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS +#define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS +/* Using standard mode which the speed up to 100Kb/s */ +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SPEED1 100000 +#define CONFIG_SYS_I2C_SPEED2 100000 +#define CONFIG_SYS_I2C_SPEED3 100000 +/* Address of device when used as slave */ +#define CONFIG_SYS_I2C_SLAVE 0x02 +#define CONFIG_SYS_I2C_SLAVE1 0x02 +#define CONFIG_SYS_I2C_SLAVE2 0x02 +#define CONFIG_SYS_I2C_SLAVE3 0x02 +#ifndef __ASSEMBLY__ +/* Clock supplied to I2C controller in unit of MHz */ +unsigned int cm_get_l4_sp_clk_hz(void); +#define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000) +#endif +#define CONFIG_CMD_I2C + /* * Serial Driver */ -- cgit v1.1 From 8a78ca9ea57e019869ddac2ef10a15593f211997 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 27 Sep 2014 01:18:29 +0200 Subject: arm: socfpga: Add example config entry for EPCS/EPCQ SPI Add example config file entry for the Altera SPI controller. This SPI controller can also, under special conditions, be used to operate the EPCS/EPCQ SPI NOR. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Vince Bridgers Cc: Pavel Machek Cc: Stefan Roese Reviewed-by: Jagannadha Sutradharudu Teki --- include/configs/socfpga_common.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'include/configs/socfpga_common.h') diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index f7b314d..c213082 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -79,6 +79,25 @@ #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS /* + * EPCS/EPCQx1 Serial Flash Controller + */ +#ifdef CONFIG_ALTERA_SPI +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_BAR +/* + * The base address is configurable in QSys, each board must specify the + * base address based on it's particular FPGA configuration. Please note + * that the address here is incremented by 0x400 from the Base address + * selected in QSys, since the SPI registers are at offset +0x400. + * #define CONFIG_SYS_SPI_BASE 0xff240400 + */ +#endif + +/* * Ethernet on SoC (EMAC) */ #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) -- cgit v1.1