From 65b20dcefc89618193fa51947968dada91e4c778 Mon Sep 17 00:00:00 2001 From: Yuri Tikhonov Date: Mon, 4 Feb 2008 14:10:42 +0100 Subject: The patch adds new POST tests for the Lwmon5 board. These are: * External Watchdog test; * dsPIC tests; * FPGA test; * GDC test; * Sysmon tests. Signed-off-by: Dmitry Rakhchev Signed-off-by: Yuri Tikhonov --- include/configs/lwmon5.h | 92 +++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 88 insertions(+), 4 deletions(-) (limited to 'include/configs/lwmon5.h') diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index c3f10c7..6489e0e 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -86,6 +86,15 @@ #define CFG_POST_ALT_WORD_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP6) /* unused GPT0 COMP reg */ +/* Additional registers for watchdog timer post test */ + +#define CFG_DSPIC_TEST_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP5) +#define CFG_WATCHDOG_TIME_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP4) +#define CFG_WATCHDOG_FLAGS_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP5) +#define CFG_WATCHDOG_MAGIC 0x12480000 +#define CFG_WATCHDOG_MAGIC_MASK 0xFFFF0000 +#define CFG_DSPIC_TEST_MASK 0x00000001 + /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ @@ -156,7 +165,81 @@ CFG_POST_MEMORY | \ CFG_POST_RTC | \ CFG_POST_SPR | \ - CFG_POST_UART) + CFG_POST_UART | \ + CFG_POST_SYSMON | \ + CFG_POST_WATCHDOG | \ + CFG_POST_DSP | \ + CFG_POST_BSPEC1 | \ + CFG_POST_BSPEC2 | \ + CFG_POST_BSPEC3 | \ + CFG_POST_BSPEC4 | \ + CFG_POST_BSPEC5) + +#define CONFIG_POST_WATCHDOG {\ + "Watchdog timer test", \ + "watchdog", \ + "This test checks the watchdog timer.", \ + POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, \ + &lwmon5_watchdog_post_test, \ + NULL, \ + NULL, \ + CFG_POST_WATCHDOG \ + } + +#define CONFIG_POST_BSPEC1 {\ + "dsPIC init test", \ + "dspic_init", \ + "This test returns result of dsPIC READY test run earlier.", \ + POST_RAM | POST_ALWAYS, \ + &dspic_init_post_test, \ + NULL, \ + NULL, \ + CFG_POST_BSPEC1 \ + } + +#define CONFIG_POST_BSPEC2 {\ + "dsPIC test", \ + "dspic", \ + "This test gets result of dsPIC POST and dsPIC version.", \ + POST_RAM | POST_ALWAYS, \ + &dspic_post_test, \ + NULL, \ + NULL, \ + CFG_POST_BSPEC2 \ + } + +#define CONFIG_POST_BSPEC3 {\ + "FPGA test", \ + "fpga", \ + "This test checks FPGA registers and memory.", \ + POST_RAM | POST_ALWAYS, \ + &fpga_post_test, \ + NULL, \ + NULL, \ + CFG_POST_BSPEC3 \ + } + +#define CONFIG_POST_BSPEC4 {\ + "GDC test", \ + "gdc", \ + "This test checks GDC registers and memory.", \ + POST_RAM | POST_ALWAYS, \ + &gdc_post_test, \ + NULL, \ + NULL, \ + CFG_POST_BSPEC4 \ + } + +#define CONFIG_POST_BSPEC5 {\ + "SYSMON1 test", \ + "sysmon1", \ + "This test checks GPIO_62_EPX pin indicating power failure.", \ + POST_RAM | POST_MANUAL | POST_NORMAL | POST_SLOWTEST, \ + &sysmon1_post_test, \ + NULL, \ + NULL, \ + CFG_POST_BSPEC5 \ + } #define CFG_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */ #define CONFIG_LOGBUFFER @@ -181,6 +264,7 @@ #define CONFIG_RTC_PCF8563 1 /* enable Philips PCF8563 RTC */ #define CFG_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */ #define CFG_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */ +#define CFG_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */ #define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */ #if 0 @@ -366,9 +450,6 @@ #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ #define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ -/* - * ToDo: Watchdog is not test fully, so exclude it for now - */ #define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */ #define CONFIG_WD_PERIOD 40000 /* in usec */ @@ -431,10 +512,13 @@ #define CFG_GPIO_PHY1_RST 12 #define CFG_GPIO_FLASH_WP 14 #define CFG_GPIO_PHY0_RST 22 +#define CFG_GPIO_DSPIC_READY 51 #define CFG_GPIO_EEPROM_EXT_WP 55 +#define CFG_GPIO_HIGHSIDE 56 #define CFG_GPIO_EEPROM_INT_WP 57 #define CFG_GPIO_LIME_S 59 #define CFG_GPIO_LIME_RST 60 +#define CFG_GPIO_SYSMON_STATUS 62 #define CFG_GPIO_WATCHDOG 63 /*----------------------------------------------------------------------- -- cgit v1.1 From ff818b21b069f4bc9cb73373cc5a16014be101b7 Mon Sep 17 00:00:00 2001 From: Yuri Tikhonov Date: Mon, 4 Feb 2008 17:11:53 +0100 Subject: Add support for the lwmon5 board reset via GPIO58. Signed-off-by: Dmitry Rakhchev Signed-off-by: Yuri Tikhonov --- include/configs/lwmon5.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/configs/lwmon5.h') diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 6489e0e..e179e4f 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -36,6 +36,7 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ +#define CONFIG_BOARD_RESET 1 /* Call board_reset */ /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the @@ -516,6 +517,7 @@ #define CFG_GPIO_EEPROM_EXT_WP 55 #define CFG_GPIO_HIGHSIDE 56 #define CFG_GPIO_EEPROM_INT_WP 57 +#define CFG_GPIO_BOARD_RESET 58 #define CFG_GPIO_LIME_S 59 #define CFG_GPIO_LIME_RST 60 #define CFG_GPIO_SYSMON_STATUS 62 -- cgit v1.1 From 2d991958b1e420fbfe17b128bd26ade74be5efcc Mon Sep 17 00:00:00 2001 From: Yuri Tikhonov Date: Wed, 6 Feb 2008 18:48:36 +0100 Subject: The patch introduces the alternative configuration of the log buffer for the lwmon5 board: the storage for the log-buffer itself is OCM(on-chip memory), the log-buffer header is moved to six GPT registers (PPC440EPX_GPT0_COMP1, ..., PPC440EPX_GPT0_COMP5). To enable this, alternative, configuration the U-Boot board configuration file for lwmon5 includes the definitions of alternative addresses for header (CONFIG_ALT_LH_ADDR) and buffer (CONFIG_ALT_LB_ADDR). The Linux shall be configured with the CONFIG_ALT_LB_LOCATION option set, and has the BOARD_ALT_LH_ADDR and BOARD_ALT_LB_ADDR constants defined in the lwmon5 board-specific header (arch/ppc/platforms/4xx/lwmon5.h). Signed-off-by: Yuri Tikhonov --- include/configs/lwmon5.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/configs/lwmon5.h') diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index e179e4f..ced7ba6 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -244,6 +244,8 @@ #define CFG_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */ #define CONFIG_LOGBUFFER +#define CONFIG_ALT_LH_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP1) +#define CONFIG_ALT_LB_ADDR (CFG_OCM_BASE) #define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ /*----------------------------------------------------------------------- -- cgit v1.1 From d32a874b9b4c1e949ee38be7790f6bf6d6143451 Mon Sep 17 00:00:00 2001 From: Yuri Tikhonov Date: Sun, 6 Apr 2008 19:19:14 +0200 Subject: lwmon5 watchdog: limit trigger rate Limit the rate of h/w watch-dog triggering on the LWMON5 board by the CONFIG_WD_MAX_RATE value. Note that an earlier version of this patch which used microseconds instead of ticks dis not work. The problem was that we used usec2ticks() to convert microseconds into ticks. usec2ticks() uses get_tbclk(), which in turn calls get_sys_info(). It turns out that this function does a lot of prolonged operations (like divisions) which take too much time so we do not trigger the watchdog in time, and it resets the system. Signed-off-by: Yuri Tikhonov --- include/configs/lwmon5.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/configs/lwmon5.h') diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index ced7ba6..58f078b 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -455,6 +455,7 @@ #define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */ #define CONFIG_WD_PERIOD 40000 /* in usec */ +#define CONFIG_WD_MAX_RATE 66600 /* in ticks */ /* * For booting Linux, the board info and command line data -- cgit v1.1