From 877bfe37dc00b0ae59f37742954a62bce3fdf3a0 Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Fri, 18 Oct 2013 11:47:24 +0200 Subject: mpc85xx: introduce the kmp204x reference design support This patch introduces the support for Keymile's kmp204x reference design. This design is based on Freescale's P2040/P2041 SoC. The peripherals used by this design are: - DDR3 RAM with SPD support - SPI NOR Flash as boot medium - NAND Flash - 2 PCIe busses (hosts 1 and 3) - 3 FMAN Ethernet devices (FMAN1 DTSEC1/2/5) - 3 Local Bus windows, with one dedicated to the QRIO reset/power mgmt FPGA - 2 HW I2C busses - last but not least, the mandatory serial port The board/keymile/kmp204x code is mostly based on Freescale's P2041rdb support and was changed according to our design (that means essentially removing what is not present on the designs and a few adaptations). There is currently only one prototype board that is based on this design and this patch also introduces it. The board is called kmlion1. Signed-off-by: Stefan Bigler Signed-off-by: Valentin Longchamp kmp204x: update the ENV #define The comments had to be refined as well as the total size Signed-off-by: Valentin Longchamp [York Sun: fix ddr.c] Acked-by: York Sun --- include/configs/kmp204x.h | 68 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 include/configs/kmp204x.h (limited to 'include/configs/kmp204x.h') diff --git a/include/configs/kmp204x.h b/include/configs/kmp204x.h new file mode 100644 index 0000000..4158c8d --- /dev/null +++ b/include/configs/kmp204x.h @@ -0,0 +1,68 @@ +/* + * (C) Copyright 2013 Keymile AG + * Valentin Longchamp + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* KMLION1 */ +#if defined(CONFIG_KMLION1) +#define CONFIG_HOSTNAME kmlion1 +#define CONFIG_KM_BOARD_NAME "kmlion1" + +#else +#error ("Board not supported") +#endif + +#define CONFIG_KMP204X + +#include "km/kmp204x-common.h" + +#if defined(CONFIG_KMLION1) +/* App1 Local bus */ +#define CONFIG_SYS_LBAPP1_BASE 0xD0000000 +#define CONFIG_SYS_LBAPP1_BASE_PHYS 0xFD0000000ull + +#define CONFIG_SYS_LBAPP1_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBAPP1_BASE_PHYS) \ + | BR_PS_8 /* Port Size 8 bits */ \ + | BR_DECC_OFF /* no error corr */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ + +#define CONFIG_SYS_LBAPP1_OR_PRELIM (OR_AM_256MB /* length 256MB */ \ + | OR_GPCM_ACS_DIV2 /* LCS 1/2 clk after */ \ + | OR_GPCM_CSNT /* LCS 1/4 clk before */ \ + | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \ + | OR_GPCM_TRLX /* relaxed tmgs */ \ + | OR_GPCM_EAD) /* extra bus clk cycles */ +/* Local bus app1 Base Address */ +#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_LBAPP1_BR_PRELIM +/* Local bus app1 Options */ +#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_LBAPP1_OR_PRELIM + +/* App2 Local bus */ +#define CONFIG_SYS_LBAPP2_BASE 0xE0000000 +#define CONFIG_SYS_LBAPP2_BASE_PHYS 0xFE0000000ull + +#define CONFIG_SYS_LBAPP2_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBAPP2_BASE_PHYS) \ + | BR_PS_8 /* Port Size 8 bits */ \ + | BR_DECC_OFF /* no error corr */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ + +#define CONFIG_SYS_LBAPP2_OR_PRELIM (OR_AM_256MB /* length 256MB */ \ + | OR_GPCM_ACS_DIV2 /* LCS 1/2 clk after */ \ + | OR_GPCM_CSNT /* LCS 1/4 clk before */ \ + | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \ + | OR_GPCM_TRLX /* relaxed tmgs */ \ + | OR_GPCM_EAD) /* extra bus clk cycles */ +/* Local bus app2 Base Address */ +#define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_LBAPP2_BR_PRELIM +/* Local bus app2 Options */ +#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_LBAPP2_OR_PRELIM +#endif + +#endif /* __CONFIG_H */ -- cgit v1.1