From e02aea61cb17fc1e39368e4911491305d805e886 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 9 Feb 2011 02:00:08 +0000 Subject: powerpc: Add P3041DS/P5020DS board support (uses corenet_ds code) The P3041DS & P5020DS boards are almost identical (except for the processor in them). Additionally they are based on the P4080DS board design so we use the some board code for all 3 boards. Some ngPIXIS (FPGA) registers where reserved on P4080DS and now have meaning on P3041DS/P5020DS. We utilize some of these for SERDES clock configuration. Additionally, the P3041DS/P5020DS support NAND. Signed-off-by: Timur Tabi Signed-off-by: Shaohui Xie Signed-off-by: Kumar Gala --- include/configs/corenet_ds.h | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) (limited to 'include/configs/corenet_ds.h') diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 9be7f1f..b1ca537 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -162,6 +162,7 @@ #define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 +#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ /* @@ -218,6 +219,43 @@ #define CONFIG_SYS_RAMBOOT #endif +/* Nand Flash */ +#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) +#define CONFIG_NAND_FSL_ELBC +#ifdef CONFIG_NAND_FSL_ELBC +#define CONFIG_SYS_NAND_BASE 0xffa00000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull +#else +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif + +#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +/* NAND flash config */ +#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | (2<