From 202d94875c98b7b573f136c4f353609758ed9733 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 15 Sep 2009 22:21:58 -0500 Subject: ppc/85xx: Fix LCRR_CLKDIV defines For some reason the CLKDIV field varies between SoC in how it interprets the bit values. All 83xx and early (e500v1) PQ3 devices support: clk/2: CLKDIV = 2 clk/4: CLKDIV = 4 clk/8: CLKDIV = 8 Newer PQ3 (e500v2) and MPC86xx support: clk/4: CLKDIV = 2 clk/8: CLKDIV = 4 clk/16: CLKDIV = 8 Ensure that the MPC86xx and MPC85xx still get the same behavior and make the defines reflect their logical view (not the value of the field). Signed-off-by: Kumar Gala Acked-by: Peter Tyser --- include/configs/XPEDITE5170.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/configs/XPEDITE5170.h') diff --git a/include/configs/XPEDITE5170.h b/include/configs/XPEDITE5170.h index 242466a..30642cd 100644 --- a/include/configs/XPEDITE5170.h +++ b/include/configs/XPEDITE5170.h @@ -122,7 +122,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable */ -#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_2 | LCRR_EADC_3) +#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3) /* * NAND flash configuration -- cgit v1.1