From f9fc6a5852a6335840882fa2111925010eea1abe Mon Sep 17 00:00:00 2001 From: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Date: Wed, 7 Mar 2007 15:32:01 +0100 Subject: fixed ethernet phy configuration for plu405 board Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> --- include/configs/PLU405.h | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) (limited to 'include/configs/PLU405.h') diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index dd5d831..d02c39b 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -51,17 +51,13 @@ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#if 0 /* test-only */ #define CONFIG_NET_MULTI 1 +#undef CONFIG_HAS_ETH1 #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_PHY1_ADDR 1 /* PHY address */ -#else -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#endif #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ -- cgit v1.1