From 18ea5551307866af06eb7628ec05b1959212efa0 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 17 Dec 2010 06:53:52 -0600 Subject: powerpc/85xx: Rework MPC8572DS pci_init_board to use common FSL PCIe code Remove duplicated code in MPC8572DS board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Chenhui Zhao Signed-off-by: Kumar Gala --- include/configs/MPC8572DS.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include/configs/MPC8572DS.h') diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 8cdcbea..9ec02cc 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -467,6 +467,7 @@ */ /* controller 3, direct to uli, tgtid 3, Base address 8000 */ +#define CONFIG_SYS_PCIE3_NAME "ULI" #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 @@ -486,6 +487,7 @@ #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 9000 */ +#define CONFIG_SYS_PCIE2_NAME "Slot 1" #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 @@ -505,6 +507,7 @@ #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 1, Slot 1, tgtid 1, Base address a000 */ +#define CONFIG_SYS_PCIE1_NAME "Slot 2" #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 -- cgit v1.1