From 93f6d72544da4510a146bc4c93d609b0116cde37 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Wed, 10 Sep 2008 22:48:00 +0200 Subject: rename CFG_ENV_IS_NOWHERE in CONFIG_ENV_IS_NOWHERE Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- include/configs/MPC837XEMDS.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/configs/MPC837XEMDS.h') diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index f9c1b17..220c148 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -427,7 +427,7 @@ #define CFG_ENV_SIZE 0x2000 #else #define CFG_NO_FLASH 1 /* Flash is not usable now */ - #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) #define CFG_ENV_SIZE 0x2000 #endif -- cgit v1.1 From 5a1aceb0689e2f731491838970884a673ef7e7d3 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Wed, 10 Sep 2008 22:48:04 +0200 Subject: rename CFG_ENV_IS_IN_FLASH in CONFIG_ENV_IS_IN_FLASH Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- include/configs/MPC837XEMDS.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/configs/MPC837XEMDS.h') diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 220c148..21d7d2d 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -421,7 +421,7 @@ * Environment */ #ifndef CFG_RAMBOOT - #define CFG_ENV_IS_IN_FLASH 1 + #define CONFIG_ENV_IS_IN_FLASH 1 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ #define CFG_ENV_SIZE 0x2000 -- cgit v1.1 From 0e8d158664a913392cb01fb11a948d83f72e105e Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Wed, 10 Sep 2008 22:48:06 +0200 Subject: rename CFG_ENV macros to CONFIG_ENV Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- include/configs/MPC837XEMDS.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'include/configs/MPC837XEMDS.h') diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 21d7d2d..7c87388 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -203,7 +203,7 @@ #undef CFG_RAMBOOT #endif -/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */ +/* CFG_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ @@ -422,14 +422,14 @@ */ #ifndef CFG_RAMBOOT #define CONFIG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) - #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ - #define CFG_ENV_SIZE 0x2000 + #define CONFIG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) + #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ + #define CONFIG_ENV_SIZE 0x2000 #else #define CFG_NO_FLASH 1 /* Flash is not usable now */ #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) - #define CFG_ENV_SIZE 0x2000 + #define CONFIG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CONFIG_ENV_SIZE 0x2000 #endif #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -- cgit v1.1 From 162c41c03179727a1d14262f703c9a8bc40231fa Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Tue, 23 Sep 2008 09:38:49 -0500 Subject: mpc83xx: add h/w flash protection to board configs the operating system may leave flash in a h/w locked state after writing. This allows u-boot to continue to write flash by enabling h/w unlocking by default. Signed-off-by: Kim Phillips --- include/configs/MPC837XEMDS.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/configs/MPC837XEMDS.h') diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 7c87388..256f156 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -229,6 +229,7 @@ #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ #define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CFG_FLASH_SIZE 32 /* max FLASH size is 32M */ +#define CFG_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ #define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ -- cgit v1.1 From 6d0f6bcf337c5261c08fabe12982178c2c489d76 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Thu, 16 Oct 2008 15:01:15 +0200 Subject: rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- include/configs/MPC837XEMDS.h | 344 +++++++++++++++++++++--------------------- 1 file changed, 172 insertions(+), 172 deletions(-) (limited to 'include/configs/MPC837XEMDS.h') diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 256f156..aeb61a9 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -47,7 +47,7 @@ * if CLKIN is 66MHz, then * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz */ -#define CFG_HRCW_LOW (\ +#define CONFIG_SYS_HRCW_LOW (\ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ HRCWL_DDR_TO_SCB_CLK_1X1 |\ HRCWL_SVCOD_DIV_2 |\ @@ -55,7 +55,7 @@ HRCWL_CORE_TO_CSB_1_5X1) #ifdef CONFIG_PCISLAVE -#define CFG_HRCW_HIGH (\ +#define CONFIG_SYS_HRCW_HIGH (\ HRCWH_PCI_AGENT |\ HRCWH_PCI1_ARBITER_DISABLE |\ HRCWH_CORE_ENABLE |\ @@ -69,7 +69,7 @@ HRCWH_BIG_ENDIAN |\ HRCWH_LDP_CLEAR) #else -#define CFG_HRCW_HIGH (\ +#define CONFIG_SYS_HRCW_HIGH (\ HRCWH_PCI_HOST |\ HRCWH_PCI1_ARBITER_ENABLE |\ HRCWH_CORE_ENABLE |\ @@ -85,29 +85,29 @@ #endif /* Arbiter Configuration Register */ -#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ -#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ /* System Priority Control Register */ -#define CFG_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */ +#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */ /* * IP blocks clock configuration */ -#define CFG_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */ -#define CFG_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */ -#define CFG_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */ +#define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */ +#define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */ +#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */ /* * System IO Config */ -#define CFG_SICRH 0x00000000 -#define CFG_SICRL 0x00000000 +#define CONFIG_SYS_SICRH 0x00000000 +#define CONFIG_SYS_SICRL 0x00000000 /* * Output Buffer Impedance */ -#define CFG_OBIR 0x31100000 +#define CONFIG_SYS_OBIR 0x31100000 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ #define CONFIG_BOARD_EARLY_INIT_R @@ -115,17 +115,17 @@ /* * IMMR new address */ -#define CFG_IMMR 0xE0000000 +#define CONFIG_SYS_IMMR 0xE0000000 /* * DDR Setup */ -#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CFG_SDRAM_BASE CFG_DDR_BASE -#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE -#define CFG_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 -#define CFG_83XX_DDR_USES_CS0 -#define CFG_DDRCDR_VALUE 0x80080001 /* ODT 150ohm on SoC */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 +#define CONFIG_SYS_83XX_DDR_USES_CS0 +#define CONFIG_SYS_DDRCDR_VALUE 0x80080001 /* ODT 150ohm on SoC */ #undef CONFIG_DDR_ECC /* support DDR ECC function */ #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ @@ -141,14 +141,14 @@ * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5 */ -#define CFG_DDR_SIZE 512 /* MB */ -#define CFG_DDR_CS0_BNDS 0x0000001f -#define CFG_DDR_CS0_CONFIG ( CSCONFIG_EN \ +#define CONFIG_SYS_DDR_SIZE 512 /* MB */ +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f +#define CONFIG_SYS_DDR_CS0_CONFIG ( CSCONFIG_EN \ | 0x00010000 /* ODT_WR to CSn */ \ | CSCONFIG_ROW_BIT_14 | CSCONFIG_COL_BIT_10 ) /* 0x80010202 */ -#define CFG_DDR_TIMING_3 0x00000000 -#define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ @@ -157,7 +157,7 @@ | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) /* 0x00620802 */ -#define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ +#define CONFIG_SYS_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ @@ -166,7 +166,7 @@ | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) /* 0x3935d322 */ -#define CFG_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ +#define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ | ( 6 << TIMING_CFG2_CPO_SHIFT ) \ | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ | ( 4 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ @@ -174,70 +174,70 @@ | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ | ( 8 << TIMING_CFG2_FOUR_ACT_SHIFT) ) /* 0x131088c8 */ -#define CFG_DDR_INTERVAL ( ( 0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT ) \ +#define CONFIG_SYS_DDR_INTERVAL ( ( 0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT ) \ | ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) /* 0x03E00100 */ -#define CFG_DDR_SDRAM_CFG 0x43000000 -#define CFG_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ -#define CFG_DDR_MODE ( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \ +#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ +#define CONFIG_SYS_DDR_MODE ( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \ | ( 0x1432 << SDRAM_MODE_SD_SHIFT ) ) /* ODT 150ohm CL=3, AL=1 on SDRAM */ -#define CFG_DDR_MODE2 0x00000000 +#define CONFIG_SYS_DDR_MODE2 0x00000000 #endif /* * Memory test */ -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00040000 /* memtest region */ -#define CFG_MEMTEST_END 0x00140000 +#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ +#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ +#define CONFIG_SYS_MEMTEST_END 0x00140000 /* * The reserved memory */ -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -#define CFG_RAMBOOT +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT #else -#undef CFG_RAMBOOT +#undef CONFIG_SYS_RAMBOOT #endif -/* CFG_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ +/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ /* * Initial RAM Base Address Setup */ -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) /* * Local Bus Configuration & Clock Setup */ -#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) -#define CFG_LBC_LBCR 0x00000000 +#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) +#define CONFIG_SYS_LBC_LBCR 0x00000000 /* * FLASH on the Local Bus */ -#define CFG_FLASH_CFI /* use the Common Flash Interface */ +#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ -#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ -#define CFG_FLASH_SIZE 32 /* max FLASH size is 32M */ -#define CFG_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ +#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ +#define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ +#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ -#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ -#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ +#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ -#define CFG_BR0_PRELIM ( CFG_FLASH_BASE /* Flash Base address */ \ +#define CONFIG_SYS_BR0_PRELIM ( CONFIG_SYS_FLASH_BASE /* Flash Base address */ \ | (2 << BR_PS_SHIFT) /* 16 bit port size */ \ | BR_V ) /* valid */ -#define CFG_OR0_PRELIM ( (~(CFG_FLASH_SIZE - 1) << 20) \ +#define CONFIG_SYS_OR0_PRELIM ( (~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \ | OR_UPM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \ @@ -248,33 +248,33 @@ | OR_GPCM_EAD ) /* 0xFE000FF7 */ -#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ -#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ /* * BCSR on the Local Bus */ -#define CFG_BCSR 0xF8000000 -#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */ -#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ +#define CONFIG_SYS_BCSR 0xF8000000 +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR /* Access window base at BCSR base */ +#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ -#define CFG_BR1_PRELIM (CFG_BCSR | 0x00000801) /* Port size=8bit, MSEL=GPCM */ -#define CFG_OR1_PRELIM 0xFFFFE9f7 /* length 32K */ +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x00000801) /* Port size=8bit, MSEL=GPCM */ +#define CONFIG_SYS_OR1_PRELIM 0xFFFFE9f7 /* length 32K */ /* * NAND Flash on the Local Bus */ -#define CFG_NAND_BASE 0xE0600000 /* 0xE0600000 */ -#define CFG_BR3_PRELIM ( CFG_NAND_BASE \ +#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ +#define CONFIG_SYS_BR3_PRELIM ( CONFIG_SYS_NAND_BASE \ | (2< " +#define CONFIG_SYS_HUSH_PARSER +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #endif /* Pass open firmware flat tree */ @@ -317,35 +317,35 @@ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CONFIG_FSL_I2C -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */ -#define CFG_I2C_OFFSET 0x3000 -#define CFG_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */ +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 /* * Config on-board RTC */ #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ -#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ /* * General PCI * Addresses are mapped 1-1. */ -#define CFG_PCI_MEM_BASE 0x80000000 -#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE -#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */ -#define CFG_PCI_MMIO_BASE 0x90000000 -#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE -#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */ -#define CFG_PCI_IO_BASE 0x00000000 -#define CFG_PCI_IO_PHYS 0xE0300000 -#define CFG_PCI_IO_SIZE 0x100000 /* 1M */ +#define CONFIG_SYS_PCI_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE +#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 +#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE +#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 +#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ -#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE -#define CFG_PCI_SLV_MEM_BUS 0x00000000 -#define CFG_PCI_SLV_MEM_SIZE 0x80000000 +#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 +#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 #ifdef CONFIG_PCI #define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */ @@ -356,7 +356,7 @@ #undef CONFIG_EEPRO100 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ #endif /* CONFIG_PCI */ #ifndef CONFIG_NET_MULTI @@ -367,10 +367,10 @@ * TSEC */ #define CONFIG_TSEC_ENET /* TSEC ethernet support */ -#define CFG_TSEC1_OFFSET 0x24000 -#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) -#define CFG_TSEC2_OFFSET 0x25000 -#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) +#define CONFIG_SYS_TSEC2_OFFSET 0x25000 +#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) /* * TSEC ethernet configuration @@ -401,15 +401,15 @@ #define CONFIG_LIBATA #define CONFIG_FSL_SATA -#define CFG_SATA_MAX_DEVICE 2 +#define CONFIG_SYS_SATA_MAX_DEVICE 2 #define CONFIG_SATA1 -#define CFG_SATA1_OFFSET 0x18000 -#define CFG_SATA1 (CFG_IMMR + CFG_SATA1_OFFSET) -#define CFG_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SYS_SATA1_OFFSET 0x18000 +#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA #define CONFIG_SATA2 -#define CFG_SATA2_OFFSET 0x19000 -#define CFG_SATA2 (CFG_IMMR + CFG_SATA2_OFFSET) -#define CFG_SATA2_FLAGS FLAGS_DMA +#define CONFIG_SYS_SATA2_OFFSET 0x19000 +#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA #ifdef CONFIG_FSL_SATA #define CONFIG_LBA48 @@ -421,20 +421,20 @@ /* * Environment */ -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT #define CONFIG_ENV_IS_IN_FLASH 1 - #define CONFIG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ #define CONFIG_ENV_SIZE 0x2000 #else - #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CONFIG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) #define CONFIG_ENV_SIZE 0x2000 #endif #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ /* * BOOTP options @@ -459,7 +459,7 @@ #define CONFIG_CMD_PCI #endif -#if defined(CFG_RAMBOOT) +#if defined(CONFIG_SYS_RAMBOOT) #undef CONFIG_CMD_ENV #undef CONFIG_CMD_LOADS #endif @@ -471,34 +471,34 @@ /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_LOAD_ADDR 0x2000000 /* default load address */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ + #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ + #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /* * Core HID Setup */ -#define CFG_HID0_INIT 0x000000000 -#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK -#define CFG_HID2 HID2_HBE +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID2 HID2_HBE /* * MMU Setup @@ -506,67 +506,67 @@ #define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR: cache cacheable */ -#define CFG_SDRAM_LOWER CFG_SDRAM_BASE -#define CFG_SDRAM_UPPER (CFG_SDRAM_BASE + 0x10000000) +#define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) -#define CFG_IBAT0L (CFG_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT0U (CFG_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT0L CFG_IBAT0L -#define CFG_DBAT0U CFG_IBAT0U +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CFG_IBAT1L (CFG_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ -#define CFG_IBAT2L (CFG_IMMR | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_10 | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_IBAT2U (CFG_IMMR | BATU_BL_8M | BATU_VS | BATU_VP) -#define CFG_DBAT2L CFG_IBAT2L -#define CFG_DBAT2U CFG_IBAT2U +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U /* BCSR: cache-inhibit and guarded */ -#define CFG_IBAT3L (CFG_BCSR | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR | BATL_PP_10 | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_IBAT3U (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP) -#define CFG_DBAT3L CFG_IBAT3L -#define CFG_DBAT3U CFG_IBAT3U +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U /* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CFG_IBAT4L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT4U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) -#define CFG_DBAT4L (CFG_FLASH_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT4U CFG_IBAT4U +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U /* Stack in dcache: cacheable, no memory coherence */ -#define CFG_IBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_10) -#define CFG_IBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -#define CFG_DBAT5L CFG_IBAT5L -#define CFG_DBAT5U CFG_IBAT5U +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U #ifdef CONFIG_PCI /* PCI MEM space: cacheable */ -#define CFG_IBAT6L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT6U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT6L CFG_IBAT6L -#define CFG_DBAT6U CFG_IBAT6U +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U /* PCI MMIO space: cache-inhibit and guarded */ -#define CFG_IBAT7L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_IBAT7U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT7L CFG_IBAT7L -#define CFG_DBAT7U CFG_IBAT7U +#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U #else -#define CFG_IBAT6L (0) -#define CFG_IBAT6U (0) -#define CFG_IBAT7L (0) -#define CFG_IBAT7U (0) -#define CFG_DBAT6L CFG_IBAT6L -#define CFG_DBAT6U CFG_IBAT6U -#define CFG_DBAT7L CFG_IBAT7L -#define CFG_DBAT7U CFG_IBAT7U +#define CONFIG_SYS_IBAT6L (0) +#define CONFIG_SYS_IBAT6U (0) +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U #endif /* -- cgit v1.1 From 1da83a63d8e1b4bddeb82581b1745a09aac3e2d3 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Thu, 2 Oct 2008 18:32:25 +0400 Subject: mpc83xx: add SGMII riser module support for the MPC8378E-MDS boards This involves configuring the SerDes and fixing up the flags and PHY addresses for the TSECs. For Linux we also fix up the device tree. Signed-off-by: Anton Vorontsov Signed-off-by: Kim Phillips --- include/configs/MPC837XEMDS.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/configs/MPC837XEMDS.h') diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index aeb61a9..e2f0942 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -382,6 +382,8 @@ #define CONFIG_TSEC2_NAME "eTSEC1" #define TSEC1_PHY_ADDR 2 #define TSEC2_PHY_ADDR 3 +#define TSEC1_PHY_ADDR_SGMII 8 +#define TSEC2_PHY_ADDR_SGMII 4 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -- cgit v1.1 From 00f7bbae92e3b13f2b37aeb1def9bb12445521b7 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Thu, 2 Oct 2008 19:17:33 +0400 Subject: mpc83xx: fix PCI scan hang on the standalone MPC837xE-MDS boards The MPC837xE-MDS board's CPLD can auto-detect if the board is on the PIB, standalone or acting as a PCI agent. User's Guide says: - When the CPLD recognizes its location on the PIB it automatically configures RCW to the PCI Host. - If the CPLD fails to recognize its location then it is automatically configured as an Agent and the PCI is configured to an external arbiter. This sounds good. Though in the standalone setup the CPLD sets PCI_HOST flag (it's ok, we can't act as PCI agents since we receive CLKIN, not PCICLK), but the CPLD doesn't set the ARBITER_ENABLE flag, and without any arbiter bad things will happen (here the board hangs during any config space reads). In this situation we must disable the PCI. And in case of anybody really want to use an external arbiter, we provide "pci_external_aribter" environment variable. Signed-off-by: Anton Vorontsov Signed-off-by: Kim Phillips --- include/configs/MPC837XEMDS.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include/configs/MPC837XEMDS.h') diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index e2f0942..c3431ee 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -348,6 +348,9 @@ #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 #ifdef CONFIG_PCI +#ifndef __ASSEMBLY__ +extern int board_pci_host_broken(void); +#endif #define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */ #define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */ -- cgit v1.1 From b3379f3fd13969934c00097c05754e7a8990fd39 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Wed, 8 Oct 2008 20:52:54 +0400 Subject: mpc83xx: add ELBC NAND support for the MPC837XEMDS boards Though NAND chip is replaceable on the MPC837XE-MDS boards, the current settings don't work with the default chip on the board. Nevertheless Freescale's U-Boot sets the option register correctly, so I just dumped the register from the working u-boot. My guess is that the old settings were applicable for some pilot boards, not found in the production. This patch also enables FSL ELBC driver so that we could access the NAND storage in the u-boot. The NAND support costs about 45KB, so the u-boot no longer fits into two 128KB NOR flash sectors, thus we also have to adjust environment location: add another 128KB to the monitor length. Signed-off-by: Anton Vorontsov It is due to hardware design and logic defect, that is the I/O[0:7] of NAND chip is connected to LAD[7:0], so when the NAND chip connected to nLCS3, you have to set up the OR3[BCTLD] = '1' for normal operation, otherwise it will have bus contention due to the pin 48/25 of U60 is enabled. Setup the OR3[BCTLD] = '1' , that meaning the LBCTL is not asserted upon access to the NAND chip, keep the default state. Acked-by: Dave Liu Signed-off-by: Kim Phillips --- include/configs/MPC837XEMDS.h | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) (limited to 'include/configs/MPC837XEMDS.h') diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index c3431ee..1e46ce2 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -204,7 +204,7 @@ #endif /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ /* @@ -268,6 +268,12 @@ /* * NAND Flash on the Local Bus */ +#define CONFIG_CMD_NAND 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_NAND_FSL_ELBC 1 + #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ #define CONFIG_SYS_BR3_PRELIM ( CONFIG_SYS_NAND_BASE \ | (2< Date: Tue, 14 Oct 2008 22:58:53 +0400 Subject: mpc83xx: add support for switching between USB Host/Function for MPC837XEMDS With this patch u-boot can fixup the dr_mode and phy_type properties for the Dual-Role USB controller. While at it, also remove #ifdefs around includes, they are not needed. Signed-off-by: Anton Vorontsov Signed-off-by: Kim Phillips --- include/configs/MPC837XEMDS.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/configs/MPC837XEMDS.h') diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 1e46ce2..d49155f 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -361,6 +361,8 @@ extern int board_pci_host_broken(void); #define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */ #define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */ +#define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */ + #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ -- cgit v1.1