From 72cd4087c9644812b0fff9440e88e986d259bf41 Mon Sep 17 00:00:00 2001 From: Joe Hershberger Date: Tue, 11 Oct 2011 23:57:28 -0500 Subject: mpc83xx: Cleanup usage of BAT constants Signed-off-by: Joe Hershberger Cc: Joe Hershberger Signed-off-by: Kim Phillips --- include/configs/MPC8323ERDB.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'include/configs/MPC8323ERDB.h') diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index f310423..b830a98 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -454,7 +454,7 @@ /* DDR: cache cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | BATU_BL_256M \ @@ -465,7 +465,7 @@ /* IMMRBAR & PCI IO: cache-inhibit and guarded */ #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ @@ -477,14 +477,14 @@ /* FLASH: icache cacheable, but dcache-inhibit and guarded */ #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \ | BATU_BL_32M \ | BATU_VS \ | BATU_VP) #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U @@ -495,7 +495,7 @@ #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U /* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \ | BATU_BL_128K \ | BATU_VS \ @@ -506,7 +506,7 @@ #ifdef CONFIG_PCI /* PCI MEM space: cacheable */ #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_MEM_PHYS \ | BATU_BL_256M \ @@ -516,7 +516,7 @@ #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U /* PCI MMIO space: cache-inhibit and guarded */ #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MMIO_PHYS \ -- cgit v1.1