From 96026d42fa4e646d28318c0a1438aac4b2017909 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Thu, 12 Jun 2008 12:40:11 +0200 Subject: Fix 4xx build issue Building for 4xx doesn't work since commit 4dbdb768: In file included from 4xx_pcie.c:28: include/asm/processor.h:971: error: expected ')' before 'ver' make[1]: *** [4xx_pcie.o] Error 1 This patch fixes the problem. Signed-off-by: Anatolij Gustschin Acked-by: Stefan Roese Acked-by: Kumar Gala --- include/asm-ppc/processor.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/asm-ppc') diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 139e686..5b50679 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -968,7 +968,7 @@ struct cpu_type { u32 soc_ver; }; -struct cpu_type *identify_cpu(uint ver); +struct cpu_type *identify_cpu(u32 ver); #define CPU_TYPE_ENTRY(n, v) \ { .name = #n, .soc_ver = SVR_##v, } -- cgit v1.1 From 4890246a2c5df90a74e2941e3673a49bbd36aee9 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Tue, 17 Jun 2008 17:45:27 -0500 Subject: mpc83xx: move CPU_TYPE_ENTRY over to processor.h to avoid this: cpu.c:47:1: warning: "CPU_TYPE_ENTRY" redefined In file included from cpu.c:33: /home/kim/git/u-boot/include/asm/processor.h:982:1: warning: this is the location of the previous definition Signed-off-by: Kim Phillips --- include/asm-ppc/processor.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'include/asm-ppc') diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 5b50679..10fd478 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -970,8 +970,15 @@ struct cpu_type { struct cpu_type *identify_cpu(u32 ver); +#if defined(CONFIG_MPC85xx) #define CPU_TYPE_ENTRY(n, v) \ { .name = #n, .soc_ver = SVR_##v, } +#else +#if defined(CONFIG_MPC83XX) +#define CPU_TYPE_ENTRY(x) {#x, SPR_##x} +#endif +#endif + #ifndef CONFIG_MACH_SPECIFIC extern int _machine; -- cgit v1.1 From 4928e97c8531283ca9b368b7c29a8a12e726562a Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 11 Jun 2008 10:14:06 -0500 Subject: PPC: Added fls, fls64, __ilog2_u64, and ffs64 to bitops fls64, __ilog2_u64, ffs64 are variants that work on an u64, and fls is used to implement them. Signed-off-by: Kumar Gala --- include/asm-ppc/bitops.h | 52 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) (limited to 'include/asm-ppc') diff --git a/include/asm-ppc/bitops.h b/include/asm-ppc/bitops.h index 4e9c608..daa66cf 100644 --- a/include/asm-ppc/bitops.h +++ b/include/asm-ppc/bitops.h @@ -152,6 +152,7 @@ extern __inline__ int test_bit(int nr, __const__ volatile void *addr) } /* Return the bit position of the most significant 1 bit in a word */ +/* - the result is undefined when x == 0 */ extern __inline__ int __ilog2(unsigned int x) { int lz; @@ -167,6 +168,57 @@ extern __inline__ int ffz(unsigned int x) return __ilog2(x & -x); } +/* + * fls: find last (most-significant) bit set. + * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. + * + * On powerpc, __ilog2(0) returns -1, but this is not safe in general + */ +static __inline__ int fls(unsigned int x) +{ + return __ilog2(x) + 1; +} + +/** + * fls64 - find last set bit in a 64-bit word + * @x: the word to search + * + * This is defined in a similar way as the libc and compiler builtin + * ffsll, but returns the position of the most significant set bit. + * + * fls64(value) returns 0 if value is 0 or the position of the last + * set bit if value is nonzero. The last (most significant) bit is + * at position 64. + */ +#if BITS_PER_LONG == 32 +static inline int fls64(__u64 x) +{ + __u32 h = x >> 32; + if (h) + return fls(h) + 32; + return fls(x); +} +#elif BITS_PER_LONG == 64 +static inline int fls64(__u64 x) +{ + if (x == 0) + return 0; + return __ilog2(x) + 1; +} +#else +#error BITS_PER_LONG not 32 or 64 +#endif + +static inline int __ilog2_u64(u64 n) +{ + return fls64(n) - 1; +} + +static inline int ffs64(u64 x) +{ + return __ilog2_u64(x & -x) + 1ull; +} + #ifdef __KERNEL__ /* -- cgit v1.1 From 5d812b8b4ad9667c77a5bf92b4ba81699abc9fc3 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 9 Jul 2008 17:33:57 +0200 Subject: ppc4xx: Enable support for > 2GB SDRAM on AMCC Katmai Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM. To support such configurations, we "only" map the first 2GB via the TLB's. We need some free virtual address space for the remaining peripherals like, SoC devices, FLASH etc. Note that ECC is currently not supported on configurations with more than 2GB SDRAM. This is because we only map the first 2GB on such systems, and therefore the ECC parity byte of the remaining area can't be written. Signed-off-by: Stefan Roese --- include/asm-ppc/ppc4xx-sdram.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include/asm-ppc') diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h index 83931f1..e151f0c 100644 --- a/include/asm-ppc/ppc4xx-sdram.h +++ b/include/asm-ppc/ppc4xx-sdram.h @@ -284,8 +284,8 @@ #if defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) #define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */ -#define SDRAM_RXBAS_SDBA_ENCODE(n) ((((u32)(n))&0xFFE00000)>>2) -#define SDRAM_RXBAS_SDBA_DECODE(n) ((((u32)(n))&0xFFE00000)<<2) +#define SDRAM_RXBAS_SDBA_ENCODE(n) ((u32)(((phys_size_t)(n) >> 2) & 0xFFE00000)) +#define SDRAM_RXBAS_SDBA_DECODE(n) ((((phys_size_t)(n)) & 0xFFE00000) << 2) #endif /* CONFIG_440SPE */ #if defined(CONFIG_440SP) #define SDRAM_RXBAS_SDBA_MASK 0xFF800000 /* Base address */ -- cgit v1.1