From d865fd09809a3a18669f35f970781820af40e4de Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Delgado Date: Thu, 17 Jul 2008 11:44:12 +0200 Subject: ppc4xx: CPU PPC440x5 on Virtex5 FX -This patchs gives support for the embbedded ppc440 on the Virtex5 FPGAs -interrupts.c divided in uic.c and interrupts.c -xilinx_irq.c for xilinx interrupt controller -Include modifications propossed by Stefan Roese Signed-off-by: Ricardo Ribalda Delgado Acked-by: Stefan Roese --- include/asm-ppc/xilinx_irq.h | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 include/asm-ppc/xilinx_irq.h (limited to 'include/asm-ppc/xilinx_irq.h') diff --git a/include/asm-ppc/xilinx_irq.h b/include/asm-ppc/xilinx_irq.h new file mode 100644 index 0000000..ddccc75 --- /dev/null +++ b/include/asm-ppc/xilinx_irq.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . +*/ +#ifndef XILINX_IRQ_H +#define XILINX_IRQ_H + +#define intc XPAR_INTC_0_BASEADDR +#define ISR (intc+(0*4)) /* Interrupt Status Register */ +#define IPR (intc+(1*4)) /* Interrupt Pending Register */ +#define IER (intc+(2*4)) /* Interrupt Enable Register */ +#define IAR (intc+(3*4)) /* Interrupt Acknowledge Register */ +#define SIE (intc+(4*4)) /* Set Interrupt Enable bits */ +#define CIE (intc+(5*4)) /* Clear Interrupt Enable bits */ +#define IVR (intc+(6*4)) /* Interrupt Vector Register */ +#define MER (intc+(7*4)) /* Master Enable Register */ + +#define IRQ_MASK(irq) (1<<(irq&0x1f)) + +#define IRQ_MAX XPAR_INTC_MAX_NUM_INTR_INPUTS + +#endif -- cgit v1.1