From f6b6c45840f9b4671d2d97243a12a1f3ffb64765 Mon Sep 17 00:00:00 2001 From: Adam Graham Date: Wed, 3 Sep 2008 12:26:59 -0700 Subject: ppc4xx: Update Kilauea to use PPC4xx DDR autocalibration routines Signed-off-by: Adam Graham Signed-off-by: Stefan Roese --- include/asm-ppc/ppc4xx-sdram.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include/asm-ppc/ppc4xx-sdram.h') diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h index 0174d62..a1ef029 100644 --- a/include/asm-ppc/ppc4xx-sdram.h +++ b/include/asm-ppc/ppc4xx-sdram.h @@ -29,6 +29,7 @@ /* * SDRAM Controller */ + /* * XXX - ToDo: Revisit file to change all these lower case defines into * upper case. Also needs to be done in the controller setup code too @@ -256,6 +257,7 @@ #define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK) #define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2) +#if !defined(CONFIG_405EX) /* * Memory queue defines */ @@ -293,7 +295,6 @@ #define SDRAM_PLBADDUHB (SDRAMQ_DCR_BASE+0x10) /* PLB base address upper 32 LL */ -#if !defined(CONFIG_405EX) /* * Memory Bank 0-7 configuration */ -- cgit v1.1 From 5ff889349d2ace13f10c9335e09365fcec8247cc Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 8 Sep 2008 14:11:12 +0200 Subject: ppc4xx: Move ppc4xx specific prototypes to ppc4xx header This patch moves some 4xx specific prototypes out of include common.h to a ppc4xx specific header. Signed-off-by: Stefan Roese --- include/asm-ppc/ppc4xx-sdram.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'include/asm-ppc/ppc4xx-sdram.h') diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h index a1ef029..8efa557 100644 --- a/include/asm-ppc/ppc4xx-sdram.h +++ b/include/asm-ppc/ppc4xx-sdram.h @@ -1402,4 +1402,18 @@ #endif /* CONFIG_SDRAM_PPC4xx_DENALI_DDR2 */ +#ifndef __ASSEMBLY__ +/* + * Prototypes + */ +void inline blank_string(int size); +inline void ppc4xx_ibm_ddr2_register_dump(void); +u32 mfdcr_any(u32); +void mtdcr_any(u32, u32); +u32 ddr_wrdtr(u32); +u32 ddr_clktr(u32); +void spd_ddr_init_hang(void); +u32 DQS_autocalibration(void); +#endif /* __ASSEMBLY__ */ + #endif /* _PPC4xx_SDRAM_H_ */ -- cgit v1.1 From 3eec160a3a405b29ce9c06920f6427b9047dd8a8 Mon Sep 17 00:00:00 2001 From: Victor Gallardo Date: Tue, 16 Sep 2008 06:59:13 -0700 Subject: ppc4xx: Fix DDR2 auto calibration on Kilauea 600MHz (200MHz PLB) Signed-off-by: Victor Gallardo Signed-off-by: Adam Graham Signed-off-by: Stefan Roese --- include/asm-ppc/ppc4xx-sdram.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include/asm-ppc/ppc4xx-sdram.h') diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h index 8efa557..2ba5619 100644 --- a/include/asm-ppc/ppc4xx-sdram.h +++ b/include/asm-ppc/ppc4xx-sdram.h @@ -1403,6 +1403,12 @@ #endif /* CONFIG_SDRAM_PPC4xx_DENALI_DDR2 */ #ifndef __ASSEMBLY__ + +struct sdram_timing { + u32 wrdtr; + u32 clktr; +}; + /* * Prototypes */ -- cgit v1.1 From 023824549a370bd185d7129d9a6c86f9be7b86a8 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 22 Sep 2008 11:06:50 +0200 Subject: Revert "ppc4xx: Fix DDR2 auto calibration on Kilauea 600MHz (200MHz PLB)" This reverts commit 3eec160a3a405b29ce9c06920f6427b9047dd8a8. Signed-off-by: Stefan Roese --- include/asm-ppc/ppc4xx-sdram.h | 6 ------ 1 file changed, 6 deletions(-) (limited to 'include/asm-ppc/ppc4xx-sdram.h') diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h index 2ba5619..8efa557 100644 --- a/include/asm-ppc/ppc4xx-sdram.h +++ b/include/asm-ppc/ppc4xx-sdram.h @@ -1403,12 +1403,6 @@ #endif /* CONFIG_SDRAM_PPC4xx_DENALI_DDR2 */ #ifndef __ASSEMBLY__ - -struct sdram_timing { - u32 wrdtr; - u32 clktr; -}; - /* * Prototypes */ -- cgit v1.1 From bf29e0ea0af03d593c64614136acc723a7a022a2 Mon Sep 17 00:00:00 2001 From: Yuri Tikhonov Date: Fri, 17 Oct 2008 12:54:18 +0200 Subject: ppc4xx: PPC44x MQ initialization Set the MQ Read Passing & MCIF Cycle limits to the recommended by AMCC values. This fixes the occasional 440SPe hard locking issues when the 440SPe's dedicated DMA engines are used (e.g. by the h/w accelerated RAID driver). Previously the appropriate initialization had been made in Linux, by the ppc440spe ADMA driver, which is wrong because modifying the MQ configuration registers after normal operation has begun is not supported and could have unpredictable results. Comment from Stefan: This patch doesn't change the resulting value of the MQ registers. It explicitly sets/clears all bits to the desired state which better documents the resulting register value instead of relying on pre-set default values. Signed-off-by: Yuri Tikhonov Signed-off-by: Stefan Roese --- include/asm-ppc/ppc4xx-sdram.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include/asm-ppc/ppc4xx-sdram.h') diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h index 8efa557..98faced 100644 --- a/include/asm-ppc/ppc4xx-sdram.h +++ b/include/asm-ppc/ppc4xx-sdram.h @@ -272,8 +272,11 @@ #define SDRAM_CONF1HB_PRPD 0x00080000 /* PLB Read pipeline Disable - Bit 12 */ #define SDRAM_CONF1HB_PWPD 0x00040000 /* PLB Write pipeline Disable - Bit 13 */ #define SDRAM_CONF1HB_PRW 0x00020000 /* PLB Read Wait - Bit 14 */ +#define SDRAM_CONF1HB_RPLM 0x00001000 /* Read Passing Limit 1 - Bits 16..19 */ #define SDRAM_CONF1HB_RPEN 0x00000800 /* Read Passing Enable - Bit 20 */ #define SDRAM_CONF1HB_RFTE 0x00000400 /* Read Flow Through Enable - Bit 21 */ +#define SDRAM_CONF1HB_WRCL 0x00000080 /* MCIF Cycle Limit 1 - Bits 22..24 */ +#define SDRAM_CONF1HB_MASK 0x0000F380 /* RPLM & WRCL mask */ #define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7) /* error status HB */ #define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8) /* error address upper 32 HB */ @@ -284,8 +287,10 @@ #define SDRAM_CONF1LL_PRPD 0x00080000 /* PLB Read pipeline Disable - Bit 12 */ #define SDRAM_CONF1LL_PWPD 0x00040000 /* PLB Write pipeline Disable - Bit 13 */ #define SDRAM_CONF1LL_PRW 0x00020000 /* PLB Read Wait - Bit 14 */ +#define SDRAM_CONF1LL_RPLM 0x00001000 /* Read Passing Limit 1 - Bits 16..19 */ #define SDRAM_CONF1LL_RPEN 0x00000800 /* Read Passing Enable - Bit 20 */ #define SDRAM_CONF1LL_RFTE 0x00000400 /* Read Flow Through Enable - Bit 21 */ +#define SDRAM_CONF1LL_MASK 0x0000F000 /* RPLM mask */ #define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC) /* error status LL */ #define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD) /* error address upper 32 LL */ -- cgit v1.1