From 6d0f6bcf337c5261c08fabe12982178c2c489d76 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Thu, 16 Oct 2008 15:01:15 +0200 Subject: rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- include/asm-ppc/cache.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'include/asm-ppc/cache.h') diff --git a/include/asm-ppc/cache.h b/include/asm-ppc/cache.h index 9d9b971..3d5f3f7 100644 --- a/include/asm-ppc/cache.h +++ b/include/asm-ppc/cache.h @@ -19,10 +19,10 @@ #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) /* - * For compatibility reasons support the CFG_CACHELINE_SIZE too + * For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too */ -#ifndef CFG_CACHELINE_SIZE -#define CFG_CACHELINE_SIZE L1_CACHE_BYTES +#ifndef CONFIG_SYS_CACHELINE_SIZE +#define CONFIG_SYS_CACHELINE_SIZE L1_CACHE_BYTES #endif #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) @@ -44,9 +44,9 @@ extern void clean_dcache_range(unsigned long start, unsigned long stop); extern void invalidate_dcache_range(unsigned long start, unsigned long stop); extern void flush_dcache(void); extern void invalidate_dcache(void); -#ifdef CFG_INIT_RAM_LOCK +#ifdef CONFIG_SYS_INIT_RAM_LOCK extern void unlock_ram_in_cache(void); -#endif /* CFG_INIT_RAM_LOCK */ +#endif /* CONFIG_SYS_INIT_RAM_LOCK */ #endif /* __ASSEMBLY__ */ /* prep registers for L2 */ -- cgit v1.1 From 54e091d3b603a3332c619199ca83a07e95960da4 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 22 Sep 2008 14:11:10 -0500 Subject: 85xx: Export invalidate_{i,d}cache and add flush_dcache Added the ability for C code to invalidate the i/d-cache's and to flush the d-cache. This allows us to more efficient change mappings from cache-able to cache-inhibited. Signed-off-by: Kumar Gala --- include/asm-ppc/cache.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/asm-ppc/cache.h') diff --git a/include/asm-ppc/cache.h b/include/asm-ppc/cache.h index 3d5f3f7..7252be7 100644 --- a/include/asm-ppc/cache.h +++ b/include/asm-ppc/cache.h @@ -44,6 +44,7 @@ extern void clean_dcache_range(unsigned long start, unsigned long stop); extern void invalidate_dcache_range(unsigned long start, unsigned long stop); extern void flush_dcache(void); extern void invalidate_dcache(void); +extern void invalidate_icache(void); #ifdef CONFIG_SYS_INIT_RAM_LOCK extern void unlock_ram_in_cache(void); #endif /* CONFIG_SYS_INIT_RAM_LOCK */ -- cgit v1.1 From 0f060c3bf82832331a509f2e5d2442539e7aad09 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 23 Oct 2008 01:47:38 -0500 Subject: 85xx: Add basic e500mc core support Introduce CONFIG_E500MC to deal with the minor differences between e500v2 and e500mc. * Certain fields of HID0/1 don't exist anymore on e500mc * Cache line size is 64-bytes on e500mc * reset value of PIR is different Signed-off-by: Kumar Gala --- include/asm-ppc/cache.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/asm-ppc/cache.h') diff --git a/include/asm-ppc/cache.h b/include/asm-ppc/cache.h index 7252be7..53e8d05 100644 --- a/include/asm-ppc/cache.h +++ b/include/asm-ppc/cache.h @@ -12,6 +12,8 @@ #define L1_CACHE_SHIFT 4 #elif defined(CONFIG_PPC64BRIDGE) #define L1_CACHE_SHIFT 7 +#elif defined(CONFIG_E500MC) +#define L1_CACHE_SHIFT 6 #else #define L1_CACHE_SHIFT 5 #endif -- cgit v1.1