From de9a738faa7c2f47286119c3bfebc3dfbfe7d86d Mon Sep 17 00:00:00 2001 From: Vlad Lungu Date: Sun, 21 Oct 2007 22:10:10 +0900 Subject: [MIPS] Fix UNCACHED_SDRAM PHYSADDR is for physical address, KSEG1ADDR is for uncached. Signed-off-by: Vlad Lungu Signed-off-by: Shinya Kuribayashi --- include/asm-mips/addrspace.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/asm-mips') diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h index b8214b1..0e6abd7 100644 --- a/include/asm-mips/addrspace.h +++ b/include/asm-mips/addrspace.h @@ -49,7 +49,7 @@ cannot access physical memory directly from core */ #define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000) #else /* !CONFIG_AU1X00 */ -#define UNCACHED_SDRAM(a) PHYSADDR(a) +#define UNCACHED_SDRAM(a) KSEG1ADDR(a) #endif /* CONFIG_AU1X00 */ #endif /* __ASSEMBLY__ */ /* -- cgit v1.1 From 5c15010efad980ad5498cc565fc1ed70df2f52b4 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Tue, 13 Nov 2007 09:11:05 +0100 Subject: Fixed mips_io_port_base build errors. This patch has been sent on: - 29 Sep 2007 Although mips_io_port_base is currently a part of IDE command, it is quite fundamental for MIPS I/O port access such as in[bwl] and out[bwl]. So move it to MIPS general part, and introduce `set_io_port_base()' from Linux. This patch is triggered by multiple definition of `mips_io_port_base' build error on gth2 (and tb0229 also needs this fix.) board/gth2/libgth2.a(gth2.o): In function `log_serial_char': /home/skuribay/devel/u-boot.git/board/gth2/gth2.c:47: multiple definition of `mips_io_port_base' common/libcommon.a(cmd_ide.o):/home/skuribay/devel/u-boot.git/common/cmd_ide.c:712: first defined here make: *** [u-boot] Error 1 Signed-off-by: Shinya Kuribayashi Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- include/asm-mips/io.h | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) (limited to 'include/asm-mips') diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h index cd4d5dc..1e060f7 100644 --- a/include/asm-mips/io.h +++ b/include/asm-mips/io.h @@ -71,7 +71,21 @@ * instruction, so the lower 16 bits must be zero. Should be true on * on any sane architecture; generic code does not use this assumption. */ -extern unsigned long mips_io_port_base; +extern const unsigned long mips_io_port_base; + +/* + * Gcc will generate code to load the value of mips_io_port_base after each + * function call which may be fairly wasteful in some cases. So we don't + * play quite by the book. We tell gcc mips_io_port_base is a long variable + * which solves the code generation issue. Now we need to violate the + * aliasing rules a little to make initialization possible and finally we + * will need the barrier() to fight side effects of the aliasing chat. + * This trickery will eventually collapse under gcc's optimizer. Oh well. + */ +static inline void set_io_port_base(unsigned long base) +{ + * (unsigned long *) &mips_io_port_base = base; +} /* * Thanks to James van Artsdalen for a better timing-fix than -- cgit v1.1