From 5c15010efad980ad5498cc565fc1ed70df2f52b4 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Tue, 13 Nov 2007 09:11:05 +0100 Subject: Fixed mips_io_port_base build errors. This patch has been sent on: - 29 Sep 2007 Although mips_io_port_base is currently a part of IDE command, it is quite fundamental for MIPS I/O port access such as in[bwl] and out[bwl]. So move it to MIPS general part, and introduce `set_io_port_base()' from Linux. This patch is triggered by multiple definition of `mips_io_port_base' build error on gth2 (and tb0229 also needs this fix.) board/gth2/libgth2.a(gth2.o): In function `log_serial_char': /home/skuribay/devel/u-boot.git/board/gth2/gth2.c:47: multiple definition of `mips_io_port_base' common/libcommon.a(cmd_ide.o):/home/skuribay/devel/u-boot.git/common/cmd_ide.c:712: first defined here make: *** [u-boot] Error 1 Signed-off-by: Shinya Kuribayashi Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- include/asm-mips/io.h | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) (limited to 'include/asm-mips/io.h') diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h index cd4d5dc..1e060f7 100644 --- a/include/asm-mips/io.h +++ b/include/asm-mips/io.h @@ -71,7 +71,21 @@ * instruction, so the lower 16 bits must be zero. Should be true on * on any sane architecture; generic code does not use this assumption. */ -extern unsigned long mips_io_port_base; +extern const unsigned long mips_io_port_base; + +/* + * Gcc will generate code to load the value of mips_io_port_base after each + * function call which may be fairly wasteful in some cases. So we don't + * play quite by the book. We tell gcc mips_io_port_base is a long variable + * which solves the code generation issue. Now we need to violate the + * aliasing rules a little to make initialization possible and finally we + * will need the barrier() to fight side effects of the aliasing chat. + * This trickery will eventually collapse under gcc's optimizer. Oh well. + */ +static inline void set_io_port_base(unsigned long base) +{ + * (unsigned long *) &mips_io_port_base = base; +} /* * Thanks to James van Artsdalen for a better timing-fix than -- cgit v1.1 From 4d7d6936eb29af7cca330937808312aa5f61454d Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Thu, 13 Dec 2007 12:56:33 +0100 Subject: Introduce map_physmem() and unmap_physmem() map_physmem() returns a virtual address which can be used to access a given physical address without involving the cache. unmap_physmem() should be called when the virtual address returned by map_physmem() is no longer needed. This patch adds a stub implementation which simply returns the physical address cast to a uchar * for all architectures except AVR32, which converts the physical address to an uncached virtual mapping. unmap_physmem() is a no-op on all architectures, but if any architecture needs to do such mappings through the TLB, this is the hook where those TLB entries can be invalidated. Signed-off-by: Haavard Skinnemoen --- include/asm-mips/io.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'include/asm-mips/io.h') diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h index 1e060f7..e27d1f1 100644 --- a/include/asm-mips/io.h +++ b/include/asm-mips/io.h @@ -465,4 +465,30 @@ static inline void sync(void) { } +/* + * Given a physical address and a length, return a virtual address + * that can be used to access the memory range with the caching + * properties specified by "flags". + */ +typedef unsigned long phys_addr_t; + +#define MAP_NOCACHE (0) +#define MAP_WRCOMBINE (0) +#define MAP_WRBACK (0) +#define MAP_WRTHROUGH (0) + +static inline void * +map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) +{ + return (void *)paddr; +} + +/* + * Take down a mapping set up by map_physmem(). + */ +static inline void unmap_physmem(void *vaddr, unsigned long flags) +{ + +} + #endif /* _ASM_IO_H */ -- cgit v1.1