From 6d0f6bcf337c5261c08fabe12982178c2c489d76 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Thu, 16 Oct 2008 15:01:15 +0200 Subject: rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- include/asm-m68k/global_data.h | 2 +- include/asm-m68k/immap.h | 346 ++++++++++++++++---------------- include/asm-m68k/immap_5227x.h | 76 ++++---- include/asm-m68k/immap_5235.h | 72 +++---- include/asm-m68k/immap_5249.h | 12 +- include/asm-m68k/immap_5253.h | 22 +-- include/asm-m68k/immap_5271.h | 72 +++---- include/asm-m68k/immap_5272.h | 36 ++-- include/asm-m68k/immap_5275.h | 76 ++++---- include/asm-m68k/immap_5282.h | 72 +++---- include/asm-m68k/immap_547x_8x.h | 60 +++--- include/asm-m68k/m5249.h | 16 +- include/asm-m68k/m5271.h | 12 +- include/asm-m68k/m5282.h | 412 +++++++++++++++++++-------------------- 14 files changed, 643 insertions(+), 643 deletions(-) (limited to 'include/asm-m68k') diff --git a/include/asm-m68k/global_data.h b/include/asm-m68k/global_data.h index 187618d..413c200 100644 --- a/include/asm-m68k/global_data.h +++ b/include/asm-m68k/global_data.h @@ -30,7 +30,7 @@ * global variables during system initialization (until we have set * up the memory controller so that we can use RAM). * - * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t) + * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t) */ typedef struct global_data { diff --git a/include/asm-m68k/immap.h b/include/asm-m68k/immap.h index b0814f1..ccd7c2b 100644 --- a/include/asm-m68k/immap.h +++ b/include/asm-m68k/immap.h @@ -30,84 +30,84 @@ #include #include -#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x4000)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) -#define CFG_MCFRTC_BASE (MMAP_RTC) +#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) #ifdef CONFIG_LCD -#define CFG_LCD_BASE (MMAP_LCD) +#define CONFIG_SYS_LCD_BASE (MMAP_LCD) #endif /* Timer */ #ifdef CONFIG_MCFTMR -#define CFG_UDELAY_BASE (MMAP_DTMR0) -#define CFG_TMR_BASE (MMAP_DTMR1) -#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0) -#define CFG_TMRINTR_NO (INT0_HI_DTMR1) -#define CFG_TMRINTR_MASK (INTC_IPRH_INT33) -#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) -#define CFG_TMRINTR_PRI (6) -#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) +#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) +#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) +#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) +#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) +#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) +#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) +#define CONFIG_SYS_TMRINTR_PRI (6) +#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) #endif #ifdef CONFIG_MCFPIT -#define CFG_UDELAY_BASE (MMAP_PIT0) -#define CFG_PIT_BASE (MMAP_PIT1) -#define CFG_PIT_PRESCALE (6) +#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) +#define CONFIG_SYS_PIT_BASE (MMAP_PIT1) +#define CONFIG_SYS_PIT_PRESCALE (6) #endif -#define CFG_INTR_BASE (MMAP_INTC0) -#define CFG_NUM_IRQS (128) +#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) +#define CONFIG_SYS_NUM_IRQS (128) #endif /* CONFIG_M52277 */ #ifdef CONFIG_M5235 #include #include -#define CFG_FEC0_IOBASE (MMAP_FEC) -#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40)) +#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) /* Timer */ #ifdef CONFIG_MCFTMR -#define CFG_UDELAY_BASE (MMAP_DTMR0) -#define CFG_TMR_BASE (MMAP_DTMR3) -#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0) -#define CFG_TMRINTR_NO (INT0_LO_DTMR3) -#define CFG_TMRINTR_MASK (INTC_IPRL_INT22) -#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) -#define CFG_TMRINTR_PRI (0x1E) /* Level must include inorder to work */ -#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) +#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) +#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3) +#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0) +#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3) +#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22) +#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) +#define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */ +#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) #endif #ifdef CONFIG_MCFPIT -#define CFG_UDELAY_BASE (MMAP_PIT0) -#define CFG_PIT_BASE (MMAP_PIT1) -#define CFG_PIT_PRESCALE (6) +#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) +#define CONFIG_SYS_PIT_BASE (MMAP_PIT1) +#define CONFIG_SYS_PIT_PRESCALE (6) #endif -#define CFG_INTR_BASE (MMAP_INTC0) -#define CFG_NUM_IRQS (128) +#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) +#define CONFIG_SYS_NUM_IRQS (128) #endif /* CONFIG_M5235 */ #ifdef CONFIG_M5249 #include #include -#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) -#define CFG_INTR_BASE (MMAP_INTC) -#define CFG_NUM_IRQS (64) +#define CONFIG_SYS_INTR_BASE (MMAP_INTC) +#define CONFIG_SYS_NUM_IRQS (64) /* Timer */ #ifdef CONFIG_MCFTMR -#define CFG_UDELAY_BASE (MMAP_DTMR0) -#define CFG_TMR_BASE (MMAP_DTMR1) -#define CFG_TMRPND_REG (mbar_readLong(MCFSIM_IPR)) -#define CFG_TMRINTR_NO (31) -#define CFG_TMRINTR_MASK (0x00000400) -#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) -#define CFG_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3) -#define CFG_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8) +#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) +#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) +#define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR)) +#define CONFIG_SYS_TMRINTR_NO (31) +#define CONFIG_SYS_TMRINTR_MASK (0x00000400) +#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) +#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3) +#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8) #endif #endif /* CONFIG_M5249 */ @@ -116,21 +116,21 @@ #include #include -#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) -#define CFG_INTR_BASE (MMAP_INTC) -#define CFG_NUM_IRQS (64) +#define CONFIG_SYS_INTR_BASE (MMAP_INTC) +#define CONFIG_SYS_NUM_IRQS (64) /* Timer */ #ifdef CONFIG_MCFTMR -#define CFG_UDELAY_BASE (MMAP_DTMR0) -#define CFG_TMR_BASE (MMAP_DTMR1) -#define CFG_TMRPND_REG (mbar_readLong(MCFSIM_IPR)) -#define CFG_TMRINTR_NO (27) -#define CFG_TMRINTR_MASK (0x00000400) -#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) -#define CFG_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3) -#define CFG_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8) +#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) +#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) +#define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR)) +#define CONFIG_SYS_TMRINTR_NO (27) +#define CONFIG_SYS_TMRINTR_MASK (0x00000400) +#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) +#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3) +#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8) #endif #endif /* CONFIG_M5253 */ @@ -138,45 +138,45 @@ #include #include -#define CFG_FEC0_IOBASE (MMAP_FEC) -#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40)) +#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) /* Timer */ #ifdef CONFIG_MCFTMR -#define CFG_UDELAY_BASE (MMAP_DTMR0) -#define CFG_TMR_BASE (MMAP_DTMR3) -#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0) -#define CFG_TMRINTR_NO (INT0_LO_DTMR3) -#define CFG_TMRINTR_MASK (INTC_IPRL_INT22) -#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) -#define CFG_TMRINTR_PRI (0) /* Level must include inorder to work */ -#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) +#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) +#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3) +#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0) +#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3) +#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22) +#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) +#define CONFIG_SYS_TMRINTR_PRI (0) /* Level must include inorder to work */ +#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) #endif -#define CFG_INTR_BASE (MMAP_INTC0) -#define CFG_NUM_IRQS (128) +#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) +#define CONFIG_SYS_NUM_IRQS (128) #endif /* CONFIG_M5271 */ #ifdef CONFIG_M5272 #include #include -#define CFG_FEC0_IOBASE (MMAP_FEC) -#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40)) +#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) -#define CFG_INTR_BASE (MMAP_INTC) -#define CFG_NUM_IRQS (64) +#define CONFIG_SYS_INTR_BASE (MMAP_INTC) +#define CONFIG_SYS_NUM_IRQS (64) /* Timer */ #ifdef CONFIG_MCFTMR -#define CFG_UDELAY_BASE (MMAP_TMR0) -#define CFG_TMR_BASE (MMAP_TMR3) -#define CFG_TMRPND_REG (((volatile intctrl_t *)(CFG_INTR_BASE))->int_isr) -#define CFG_TMRINTR_NO (INT_TMR3) -#define CFG_TMRINTR_MASK (INT_ISR_INT24) -#define CFG_TMRINTR_PEND (0) -#define CFG_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5)) -#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) +#define CONFIG_SYS_UDELAY_BASE (MMAP_TMR0) +#define CONFIG_SYS_TMR_BASE (MMAP_TMR3) +#define CONFIG_SYS_TMRPND_REG (((volatile intctrl_t *)(CONFIG_SYS_INTR_BASE))->int_isr) +#define CONFIG_SYS_TMRINTR_NO (INT_TMR3) +#define CONFIG_SYS_TMRINTR_MASK (INT_ISR_INT24) +#define CONFIG_SYS_TMRINTR_PEND (0) +#define CONFIG_SYS_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5)) +#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) #endif #endif /* CONFIG_M5272 */ @@ -184,23 +184,23 @@ #include #include -#define CFG_FEC0_IOBASE (MMAP_FEC0) -#define CFG_FEC1_IOBASE (MMAP_FEC1) -#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40)) +#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) +#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) -#define CFG_INTR_BASE (MMAP_INTC0) -#define CFG_NUM_IRQS (192) +#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) +#define CONFIG_SYS_NUM_IRQS (192) /* Timer */ #ifdef CONFIG_MCFTMR -#define CFG_UDELAY_BASE (MMAP_DTMR0) -#define CFG_TMR_BASE (MMAP_DTMR3) -#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0) -#define CFG_TMRINTR_NO (INT0_LO_DTMR3) -#define CFG_TMRINTR_MASK (INTC_IPRL_INT22) -#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) -#define CFG_TMRINTR_PRI (0x1E) -#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) +#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) +#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3) +#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0) +#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3) +#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22) +#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) +#define CONFIG_SYS_TMRINTR_PRI (0x1E) +#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) #endif #endif /* CONFIG_M5275 */ @@ -208,22 +208,22 @@ #include #include -#define CFG_FEC0_IOBASE (MMAP_FEC) -#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40)) +#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) -#define CFG_INTR_BASE (MMAP_INTC0) -#define CFG_NUM_IRQS (128) +#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) +#define CONFIG_SYS_NUM_IRQS (128) /* Timer */ #ifdef CONFIG_MCFTMR -#define CFG_UDELAY_BASE (MMAP_DTMR0) -#define CFG_TMR_BASE (MMAP_DTMR3) -#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0) -#define CFG_TMRINTR_NO (INT0_LO_DTMR3) -#define CFG_TMRINTR_MASK (1 << INT0_LO_DTMR3) -#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) -#define CFG_TMRINTR_PRI (0x1E) /* Level must include inorder to work */ -#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) +#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) +#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3) +#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0) +#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3) +#define CONFIG_SYS_TMRINTR_MASK (1 << INT0_LO_DTMR3) +#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) +#define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */ +#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) #endif #endif /* CONFIG_M5282 */ @@ -231,71 +231,71 @@ #include #include -#define CFG_FEC0_IOBASE (MMAP_FEC) -#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x4000)) -#define CFG_MCFRTC_BASE (MMAP_RTC) +#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) +#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) /* Timer */ #ifdef CONFIG_MCFTMR -#define CFG_UDELAY_BASE (MMAP_DTMR0) -#define CFG_TMR_BASE (MMAP_DTMR1) -#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0) -#define CFG_TMRINTR_NO (INT0_HI_DTMR1) -#define CFG_TMRINTR_MASK (INTC_IPRH_INT33) -#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) -#define CFG_TMRINTR_PRI (6) -#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) +#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) +#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) +#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) +#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) +#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) +#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) +#define CONFIG_SYS_TMRINTR_PRI (6) +#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) #endif #ifdef CONFIG_MCFPIT -#define CFG_UDELAY_BASE (MMAP_PIT0) -#define CFG_PIT_BASE (MMAP_PIT1) -#define CFG_PIT_PRESCALE (6) +#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) +#define CONFIG_SYS_PIT_BASE (MMAP_PIT1) +#define CONFIG_SYS_PIT_PRESCALE (6) #endif -#define CFG_INTR_BASE (MMAP_INTC0) -#define CFG_NUM_IRQS (128) +#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) +#define CONFIG_SYS_NUM_IRQS (128) #endif /* CONFIG_M5329 && CONFIG_M5373 */ #if defined(CONFIG_M54451) || defined(CONFIG_M54455) #include #include -#define CFG_FEC0_IOBASE (MMAP_FEC0) +#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) #if defined(CONFIG_M54455EVB) -#define CFG_FEC1_IOBASE (MMAP_FEC1) +#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) #endif -#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x4000)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) -#define CFG_MCFRTC_BASE (MMAP_RTC) +#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) /* Timer */ #ifdef CONFIG_MCFTMR -#define CFG_UDELAY_BASE (MMAP_DTMR0) -#define CFG_TMR_BASE (MMAP_DTMR1) -#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0) -#define CFG_TMRINTR_NO (INT0_HI_DTMR1) -#define CFG_TMRINTR_MASK (INTC_IPRH_INT33) -#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) -#define CFG_TMRINTR_PRI (6) -#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) +#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) +#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) +#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) +#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) +#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) +#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) +#define CONFIG_SYS_TMRINTR_PRI (6) +#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) #endif #ifdef CONFIG_MCFPIT -#define CFG_UDELAY_BASE (MMAP_PIT0) -#define CFG_PIT_BASE (MMAP_PIT1) -#define CFG_PIT_PRESCALE (6) +#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) +#define CONFIG_SYS_PIT_BASE (MMAP_PIT1) +#define CONFIG_SYS_PIT_PRESCALE (6) #endif -#define CFG_INTR_BASE (MMAP_INTC0) -#define CFG_NUM_IRQS (128) +#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) +#define CONFIG_SYS_NUM_IRQS (128) #ifdef CONFIG_PCI -#define CFG_PCI_BAR0 (CFG_MBAR) -#define CFG_PCI_BAR5 (CFG_SDRAM_BASE) -#define CFG_PCI_TBATR0 (CFG_MBAR) -#define CFG_PCI_TBATR5 (CFG_SDRAM_BASE) +#define CONFIG_SYS_PCI_BAR0 (CONFIG_SYS_MBAR) +#define CONFIG_SYS_PCI_BAR5 (CONFIG_SYS_SDRAM_BASE) +#define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR) +#define CONFIG_SYS_PCI_TBATR5 (CONFIG_SYS_SDRAM_BASE) #endif #endif /* CONFIG_M54451 || CONFIG_M54455 */ @@ -304,8 +304,8 @@ #include #ifdef CONFIG_FSLDMAFEC -#define CFG_FEC0_IOBASE (MMAP_FEC0) -#define CFG_FEC1_IOBASE (MMAP_FEC1) +#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) +#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) #define FEC0_RX_TASK 0 #define FEC0_TX_TASK 1 @@ -321,27 +321,27 @@ #define FEC1_TX_INIT 31 #endif -#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x100)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100)) #ifdef CONFIG_SLTTMR -#define CFG_UDELAY_BASE (MMAP_SLT1) -#define CFG_TMR_BASE (MMAP_SLT0) -#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0) -#define CFG_TMRINTR_NO (INT0_HI_SLT0) -#define CFG_TMRINTR_MASK (INTC_IPRH_INT54) -#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) -#define CFG_TMRINTR_PRI (0x1E) -#define CFG_TIMER_PRESCALER (gd->bus_clk / 1000000) +#define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1) +#define CONFIG_SYS_TMR_BASE (MMAP_SLT0) +#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) +#define CONFIG_SYS_TMRINTR_NO (INT0_HI_SLT0) +#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT54) +#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) +#define CONFIG_SYS_TMRINTR_PRI (0x1E) +#define CONFIG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000) #endif -#define CFG_INTR_BASE (MMAP_INTC0) -#define CFG_NUM_IRQS (128) +#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) +#define CONFIG_SYS_NUM_IRQS (128) #ifdef CONFIG_PCI -#define CFG_PCI_BAR0 (0x40000000) -#define CFG_PCI_BAR1 (CFG_SDRAM_BASE) -#define CFG_PCI_TBATR0 (CFG_MBAR) -#define CFG_PCI_TBATR1 (CFG_SDRAM_BASE) +#define CONFIG_SYS_PCI_BAR0 (0x40000000) +#define CONFIG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE) +#define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR) +#define CONFIG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE) #endif #endif /* CONFIG_M547x */ @@ -350,8 +350,8 @@ #include #ifdef CONFIG_FSLDMAFEC -#define CFG_FEC0_IOBASE (MMAP_FEC0) -#define CFG_FEC1_IOBASE (MMAP_FEC1) +#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) +#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) #define FEC0_RX_TASK 0 #define FEC0_TX_TASK 1 @@ -367,28 +367,28 @@ #define FEC1_TX_INIT 31 #endif -#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x100)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100)) /* Timer */ #ifdef CONFIG_SLTTMR -#define CFG_UDELAY_BASE (MMAP_SLT1) -#define CFG_TMR_BASE (MMAP_SLT0) -#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0) -#define CFG_TMRINTR_NO (INT0_HI_SLT0) -#define CFG_TMRINTR_MASK (INTC_IPRH_INT54) -#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) -#define CFG_TMRINTR_PRI (0x1E) -#define CFG_TIMER_PRESCALER (gd->bus_clk / 1000000) +#define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1) +#define CONFIG_SYS_TMR_BASE (MMAP_SLT0) +#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) +#define CONFIG_SYS_TMRINTR_NO (INT0_HI_SLT0) +#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT54) +#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) +#define CONFIG_SYS_TMRINTR_PRI (0x1E) +#define CONFIG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000) #endif -#define CFG_INTR_BASE (MMAP_INTC0) -#define CFG_NUM_IRQS (128) +#define CONFIG_SYS_INTR_BASE (MMAP_INTC0) +#define CONFIG_SYS_NUM_IRQS (128) #ifdef CONFIG_PCI -#define CFG_PCI_BAR0 (CFG_MBAR) -#define CFG_PCI_BAR1 (CFG_SDRAM_BASE) -#define CFG_PCI_TBATR0 (CFG_MBAR) -#define CFG_PCI_TBATR1 (CFG_SDRAM_BASE) +#define CONFIG_SYS_PCI_BAR0 (CONFIG_SYS_MBAR) +#define CONFIG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE) +#define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR) +#define CONFIG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE) #endif #endif /* CONFIG_M548x */ diff --git a/include/asm-m68k/immap_5227x.h b/include/asm-m68k/immap_5227x.h index 1d1e6f1..83da3d5 100644 --- a/include/asm-m68k/immap_5227x.h +++ b/include/asm-m68k/immap_5227x.h @@ -27,44 +27,44 @@ #define __IMMAP_5227X__ /* Module Base Addresses */ -#define MMAP_SCM1 (CFG_MBAR + 0x00000000) -#define MMAP_XBS (CFG_MBAR + 0x00004000) -#define MMAP_FBCS (CFG_MBAR + 0x00008000) -#define MMAP_CAN (CFG_MBAR + 0x00020000) -#define MMAP_RTC (CFG_MBAR + 0x0003C000) -#define MMAP_SCM2 (CFG_MBAR + 0x00040010) -#define MMAP_SCM3 (CFG_MBAR + 0x00040070) -#define MMAP_EDMA (CFG_MBAR + 0x00044000) -#define MMAP_INTC0 (CFG_MBAR + 0x00048000) -#define MMAP_INTC1 (CFG_MBAR + 0x0004C000) -#define MMAP_IACK (CFG_MBAR + 0x00054000) -#define MMAP_I2C (CFG_MBAR + 0x00058000) -#define MMAP_DSPI (CFG_MBAR + 0x0005C000) -#define MMAP_UART0 (CFG_MBAR + 0x00060000) -#define MMAP_UART1 (CFG_MBAR + 0x00064000) -#define MMAP_UART2 (CFG_MBAR + 0x00068000) -#define MMAP_DTMR0 (CFG_MBAR + 0x00070000) -#define MMAP_DTMR1 (CFG_MBAR + 0x00074000) -#define MMAP_DTMR2 (CFG_MBAR + 0x00078000) -#define MMAP_DTMR3 (CFG_MBAR + 0x0007C000) -#define MMAP_PIT0 (CFG_MBAR + 0x00080000) -#define MMAP_PIT1 (CFG_MBAR + 0x00084000) -#define MMAP_PWM (CFG_MBAR + 0x00090000) -#define MMAP_EPORT (CFG_MBAR + 0x00094000) -#define MMAP_RCM (CFG_MBAR + 0x000A0000) -#define MMAP_CCM (CFG_MBAR + 0x000A0004) -#define MMAP_GPIO (CFG_MBAR + 0x000A4000) -#define MMAP_ADC (CFG_MBAR + 0x000A8000) -#define MMAP_LCD (CFG_MBAR + 0x000AC000) -#define MMAP_LCD_BGLUT (CFG_MBAR + 0x000AC800) -#define MMAP_LCD_GWLUT (CFG_MBAR + 0x000ACC00) -#define MMAP_USBHW (CFG_MBAR + 0x000B0000) -#define MMAP_USBCAPS (CFG_MBAR + 0x000B0100) -#define MMAP_USBEHCI (CFG_MBAR + 0x000B0140) -#define MMAP_USBOTG (CFG_MBAR + 0x000B01A0) -#define MMAP_SDRAM (CFG_MBAR + 0x000B8000) -#define MMAP_SSI (CFG_MBAR + 0x000BC000) -#define MMAP_PLL (CFG_MBAR + 0x000C0000) +#define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000) +#define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000) +#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000) +#define MMAP_CAN (CONFIG_SYS_MBAR + 0x00020000) +#define MMAP_RTC (CONFIG_SYS_MBAR + 0x0003C000) +#define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040010) +#define MMAP_SCM3 (CONFIG_SYS_MBAR + 0x00040070) +#define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000) +#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000) +#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x0004C000) +#define MMAP_IACK (CONFIG_SYS_MBAR + 0x00054000) +#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00058000) +#define MMAP_DSPI (CONFIG_SYS_MBAR + 0x0005C000) +#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00060000) +#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00064000) +#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00068000) +#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00070000) +#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00074000) +#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00078000) +#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x0007C000) +#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00080000) +#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00084000) +#define MMAP_PWM (CONFIG_SYS_MBAR + 0x00090000) +#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00094000) +#define MMAP_RCM (CONFIG_SYS_MBAR + 0x000A0000) +#define MMAP_CCM (CONFIG_SYS_MBAR + 0x000A0004) +#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x000A4000) +#define MMAP_ADC (CONFIG_SYS_MBAR + 0x000A8000) +#define MMAP_LCD (CONFIG_SYS_MBAR + 0x000AC000) +#define MMAP_LCD_BGLUT (CONFIG_SYS_MBAR + 0x000AC800) +#define MMAP_LCD_GWLUT (CONFIG_SYS_MBAR + 0x000ACC00) +#define MMAP_USBHW (CONFIG_SYS_MBAR + 0x000B0000) +#define MMAP_USBCAPS (CONFIG_SYS_MBAR + 0x000B0100) +#define MMAP_USBEHCI (CONFIG_SYS_MBAR + 0x000B0140) +#define MMAP_USBOTG (CONFIG_SYS_MBAR + 0x000B01A0) +#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x000B8000) +#define MMAP_SSI (CONFIG_SYS_MBAR + 0x000BC000) +#define MMAP_PLL (CONFIG_SYS_MBAR + 0x000C0000) #include #include diff --git a/include/asm-m68k/immap_5235.h b/include/asm-m68k/immap_5235.h index 4a03450..3ef0321 100644 --- a/include/asm-m68k/immap_5235.h +++ b/include/asm-m68k/immap_5235.h @@ -26,42 +26,42 @@ #ifndef __IMMAP_5235__ #define __IMMAP_5235__ -#define MMAP_SCM (CFG_MBAR + 0x00000000) -#define MMAP_SDRAM (CFG_MBAR + 0x00000040) -#define MMAP_FBCS (CFG_MBAR + 0x00000080) -#define MMAP_DMA0 (CFG_MBAR + 0x00000100) -#define MMAP_DMA1 (CFG_MBAR + 0x00000110) -#define MMAP_DMA2 (CFG_MBAR + 0x00000120) -#define MMAP_DMA3 (CFG_MBAR + 0x00000130) -#define MMAP_UART0 (CFG_MBAR + 0x00000200) -#define MMAP_UART1 (CFG_MBAR + 0x00000240) -#define MMAP_UART2 (CFG_MBAR + 0x00000280) -#define MMAP_I2C (CFG_MBAR + 0x00000300) -#define MMAP_QSPI (CFG_MBAR + 0x00000340) -#define MMAP_DTMR0 (CFG_MBAR + 0x00000400) -#define MMAP_DTMR1 (CFG_MBAR + 0x00000440) -#define MMAP_DTMR2 (CFG_MBAR + 0x00000480) -#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0) -#define MMAP_INTC0 (CFG_MBAR + 0x00000C00) -#define MMAP_INTC1 (CFG_MBAR + 0x00000D00) -#define MMAP_INTCACK (CFG_MBAR + 0x00000F00) -#define MMAP_FEC (CFG_MBAR + 0x00001000) -#define MMAP_FECFIFO (CFG_MBAR + 0x00001400) -#define MMAP_GPIO (CFG_MBAR + 0x00100000) -#define MMAP_CCM (CFG_MBAR + 0x00110000) -#define MMAP_PLL (CFG_MBAR + 0x00120000) -#define MMAP_EPORT (CFG_MBAR + 0x00130000) -#define MMAP_WDOG (CFG_MBAR + 0x00140000) -#define MMAP_PIT0 (CFG_MBAR + 0x00150000) -#define MMAP_PIT1 (CFG_MBAR + 0x00160000) -#define MMAP_PIT2 (CFG_MBAR + 0x00170000) -#define MMAP_PIT3 (CFG_MBAR + 0x00180000) -#define MMAP_MDHA (CFG_MBAR + 0x00190000) -#define MMAP_RNG (CFG_MBAR + 0x001A0000) -#define MMAP_SKHA (CFG_MBAR + 0x001B0000) -#define MMAP_CAN1 (CFG_MBAR + 0x001C0000) -#define MMAP_ETPU (CFG_MBAR + 0x001D0000) -#define MMAP_CAN2 (CFG_MBAR + 0x001F0000) +#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000) +#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040) +#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) +#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100) +#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110) +#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120) +#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130) +#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200) +#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240) +#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280) +#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300) +#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340) +#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400) +#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440) +#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480) +#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0) +#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00) +#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00) +#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00) +#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00001000) +#define MMAP_FECFIFO (CONFIG_SYS_MBAR + 0x00001400) +#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000) +#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110000) +#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000) +#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000) +#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000) +#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000) +#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000) +#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000) +#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000) +#define MMAP_MDHA (CONFIG_SYS_MBAR + 0x00190000) +#define MMAP_RNG (CONFIG_SYS_MBAR + 0x001A0000) +#define MMAP_SKHA (CONFIG_SYS_MBAR + 0x001B0000) +#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x001C0000) +#define MMAP_ETPU (CONFIG_SYS_MBAR + 0x001D0000) +#define MMAP_CAN2 (CONFIG_SYS_MBAR + 0x001F0000) /* System Control Module register */ typedef struct scm_ctrl { diff --git a/include/asm-m68k/immap_5249.h b/include/asm-m68k/immap_5249.h index 6c6fbcc..6b57ba7 100644 --- a/include/asm-m68k/immap_5249.h +++ b/include/asm-m68k/immap_5249.h @@ -25,11 +25,11 @@ #ifndef __IMMAP_5249__ #define __IMMAP_5249__ -#define MMAP_INTC (CFG_MBAR + 0x00000040) -#define MMAP_DTMR0 (CFG_MBAR + 0x00000140) -#define MMAP_DTMR1 (CFG_MBAR + 0x00000180) -#define MMAP_UART0 (CFG_MBAR + 0x000001C0) -#define MMAP_UART1 (CFG_MBAR + 0x00000200) -#define MMAP_QSPI (CFG_MBAR + 0x00000400) +#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040) +#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140) +#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180) +#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0) +#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200) +#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000400) #endif /* __IMMAP_5249__ */ diff --git a/include/asm-m68k/immap_5253.h b/include/asm-m68k/immap_5253.h index aafbdd0..4e3a481 100644 --- a/include/asm-m68k/immap_5253.h +++ b/include/asm-m68k/immap_5253.h @@ -26,18 +26,18 @@ #ifndef __IMMAP_5249__ #define __IMMAP_5249__ -#define MMAP_INTC (CFG_MBAR + 0x00000040) -#define MMAP_DTMR0 (CFG_MBAR + 0x00000140) -#define MMAP_DTMR1 (CFG_MBAR + 0x00000180) -#define MMAP_UART0 (CFG_MBAR + 0x000001C0) -#define MMAP_UART1 (CFG_MBAR + 0x00000200) -#define MMAP_I2C0 (CFG_MBAR + 0x00000280) -#define MMAP_QSPI (CFG_MBAR + 0x00000400) -#define MMAP_CAN0 (CFG_MBAR + 0x00010000) -#define MMAP_CAN1 (CFG_MBAR + 0x00011000) +#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040) +#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140) +#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180) +#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0) +#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200) +#define MMAP_I2C0 (CONFIG_SYS_MBAR + 0x00000280) +#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000400) +#define MMAP_CAN0 (CONFIG_SYS_MBAR + 0x00010000) +#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x00011000) -#define MMAP_I2C1 (CFG_MBAR2 + 0x00000440) -#define MMAP_UART2 (CFG_MBAR2 + 0x00000C00) +#define MMAP_I2C1 (CONFIG_SYS_MBAR2 + 0x00000440) +#define MMAP_UART2 (CONFIG_SYS_MBAR2 + 0x00000C00) /********************************************************************* * ATA Module (ATAC) diff --git a/include/asm-m68k/immap_5271.h b/include/asm-m68k/immap_5271.h index d9dc015..462d5f2 100644 --- a/include/asm-m68k/immap_5271.h +++ b/include/asm-m68k/immap_5271.h @@ -26,42 +26,42 @@ #ifndef __IMMAP_5271__ #define __IMMAP_5271__ -#define MMAP_SCM (CFG_MBAR + 0x00000000) -#define MMAP_SDRAM (CFG_MBAR + 0x00000040) -#define MMAP_FBCS (CFG_MBAR + 0x00000080) -#define MMAP_DMA0 (CFG_MBAR + 0x00000100) -#define MMAP_DMA1 (CFG_MBAR + 0x00000110) -#define MMAP_DMA2 (CFG_MBAR + 0x00000120) -#define MMAP_DMA3 (CFG_MBAR + 0x00000130) -#define MMAP_UART0 (CFG_MBAR + 0x00000200) -#define MMAP_UART1 (CFG_MBAR + 0x00000240) -#define MMAP_UART2 (CFG_MBAR + 0x00000280) -#define MMAP_I2C (CFG_MBAR + 0x00000300) -#define MMAP_QSPI (CFG_MBAR + 0x00000340) -#define MMAP_DTMR0 (CFG_MBAR + 0x00000400) -#define MMAP_DTMR1 (CFG_MBAR + 0x00000440) -#define MMAP_DTMR2 (CFG_MBAR + 0x00000480) -#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0) -#define MMAP_INTC0 (CFG_MBAR + 0x00000C00) -#define MMAP_INTC1 (CFG_MBAR + 0x00000D00) -#define MMAP_INTCACK (CFG_MBAR + 0x00000F00) -#define MMAP_FEC (CFG_MBAR + 0x00001000) -#define MMAP_FECFIFO (CFG_MBAR + 0x00001400) -#define MMAP_GPIO (CFG_MBAR + 0x00100000) -#define MMAP_CCM (CFG_MBAR + 0x00110000) -#define MMAP_PLL (CFG_MBAR + 0x00120000) -#define MMAP_EPORT (CFG_MBAR + 0x00130000) -#define MMAP_WDOG (CFG_MBAR + 0x00140000) -#define MMAP_PIT0 (CFG_MBAR + 0x00150000) -#define MMAP_PIT1 (CFG_MBAR + 0x00160000) -#define MMAP_PIT2 (CFG_MBAR + 0x00170000) -#define MMAP_PIT3 (CFG_MBAR + 0x00180000) -#define MMAP_MDHA (CFG_MBAR + 0x00190000) -#define MMAP_RNG (CFG_MBAR + 0x001A0000) -#define MMAP_SKHA (CFG_MBAR + 0x001B0000) -#define MMAP_CAN1 (CFG_MBAR + 0x001C0000) -#define MMAP_ETPU (CFG_MBAR + 0x001D0000) -#define MMAP_CAN2 (CFG_MBAR + 0x001F0000) +#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000) +#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040) +#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) +#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100) +#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110) +#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120) +#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130) +#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200) +#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240) +#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280) +#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300) +#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340) +#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400) +#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440) +#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480) +#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0) +#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00) +#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00) +#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00) +#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00001000) +#define MMAP_FECFIFO (CONFIG_SYS_MBAR + 0x00001400) +#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000) +#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110000) +#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000) +#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000) +#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000) +#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000) +#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000) +#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000) +#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000) +#define MMAP_MDHA (CONFIG_SYS_MBAR + 0x00190000) +#define MMAP_RNG (CONFIG_SYS_MBAR + 0x001A0000) +#define MMAP_SKHA (CONFIG_SYS_MBAR + 0x001B0000) +#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x001C0000) +#define MMAP_ETPU (CONFIG_SYS_MBAR + 0x001D0000) +#define MMAP_CAN2 (CONFIG_SYS_MBAR + 0x001F0000) /* Interrupt module registers */ typedef struct int0_ctrl { diff --git a/include/asm-m68k/immap_5272.h b/include/asm-m68k/immap_5272.h index 2ebb140..b106289 100644 --- a/include/asm-m68k/immap_5272.h +++ b/include/asm-m68k/immap_5272.h @@ -25,24 +25,24 @@ #ifndef __IMMAP_5272__ #define __IMMAP_5272__ -#define MMAP_CFG (CFG_MBAR + 0x00000000) -#define MMAP_INTC (CFG_MBAR + 0x00000020) -#define MMAP_FBCS (CFG_MBAR + 0x00000040) -#define MMAP_GPIO (CFG_MBAR + 0x00000080) -#define MMAP_QSPI (CFG_MBAR + 0x000000A0) -#define MMAP_PWM (CFG_MBAR + 0x000000C0) -#define MMAP_DMA0 (CFG_MBAR + 0x000000E0) -#define MMAP_UART0 (CFG_MBAR + 0x00000100) -#define MMAP_UART1 (CFG_MBAR + 0x00000140) -#define MMAP_SDRAM (CFG_MBAR + 0x00000180) -#define MMAP_TMR0 (CFG_MBAR + 0x00000200) -#define MMAP_TMR1 (CFG_MBAR + 0x00000220) -#define MMAP_TMR2 (CFG_MBAR + 0x00000240) -#define MMAP_TMR3 (CFG_MBAR + 0x00000260) -#define MMAP_WDOG (CFG_MBAR + 0x00000280) -#define MMAP_PLIC (CFG_MBAR + 0x00000300) -#define MMAP_FEC (CFG_MBAR + 0x00000840) -#define MMAP_USB (CFG_MBAR + 0x00001000) +#define MMAP_CFG (CONFIG_SYS_MBAR + 0x00000000) +#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000020) +#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000040) +#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000080) +#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x000000A0) +#define MMAP_PWM (CONFIG_SYS_MBAR + 0x000000C0) +#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x000000E0) +#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000100) +#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000140) +#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000180) +#define MMAP_TMR0 (CONFIG_SYS_MBAR + 0x00000200) +#define MMAP_TMR1 (CONFIG_SYS_MBAR + 0x00000220) +#define MMAP_TMR2 (CONFIG_SYS_MBAR + 0x00000240) +#define MMAP_TMR3 (CONFIG_SYS_MBAR + 0x00000260) +#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00000280) +#define MMAP_PLIC (CONFIG_SYS_MBAR + 0x00000300) +#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00000840) +#define MMAP_USB (CONFIG_SYS_MBAR + 0x00001000) /* System configuration registers */ typedef struct sys_ctrl { diff --git a/include/asm-m68k/immap_5275.h b/include/asm-m68k/immap_5275.h index 774866e..495010b 100644 --- a/include/asm-m68k/immap_5275.h +++ b/include/asm-m68k/immap_5275.h @@ -27,44 +27,44 @@ #ifndef __IMMAP_5275__ #define __IMMAP_5275__ -#define MMAP_SCM (CFG_MBAR + 0x00000000) -#define MMAP_SDRAM (CFG_MBAR + 0x00000040) -#define MMAP_FBCS (CFG_MBAR + 0x00000080) -#define MMAP_DMA0 (CFG_MBAR + 0x00000100) -#define MMAP_DMA1 (CFG_MBAR + 0x00000110) -#define MMAP_DMA2 (CFG_MBAR + 0x00000120) -#define MMAP_DMA3 (CFG_MBAR + 0x00000130) -#define MMAP_UART0 (CFG_MBAR + 0x00000200) -#define MMAP_UART1 (CFG_MBAR + 0x00000240) -#define MMAP_UART2 (CFG_MBAR + 0x00000280) -#define MMAP_I2C (CFG_MBAR + 0x00000300) -#define MMAP_QSPI (CFG_MBAR + 0x00000340) -#define MMAP_DTMR0 (CFG_MBAR + 0x00000400) -#define MMAP_DTMR1 (CFG_MBAR + 0x00000440) -#define MMAP_DTMR2 (CFG_MBAR + 0x00000480) -#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0) -#define MMAP_INTC0 (CFG_MBAR + 0x00000C00) -#define MMAP_INTC1 (CFG_MBAR + 0x00000D00) -#define MMAP_INTCACK (CFG_MBAR + 0x00000F00) -#define MMAP_FEC0 (CFG_MBAR + 0x00001000) -#define MMAP_FEC0FIFO (CFG_MBAR + 0x00001400) -#define MMAP_FEC1 (CFG_MBAR + 0x00001800) -#define MMAP_FEC1FIFO (CFG_MBAR + 0x00001C00) -#define MMAP_GPIO (CFG_MBAR + 0x00100000) -#define MMAP_RCM (CFG_MBAR + 0x00110000) -#define MMAP_CCM (CFG_MBAR + 0x00110004) -#define MMAP_PLL (CFG_MBAR + 0x00120000) -#define MMAP_EPORT (CFG_MBAR + 0x00130000) -#define MMAP_WDOG (CFG_MBAR + 0x00140000) -#define MMAP_PIT0 (CFG_MBAR + 0x00150000) -#define MMAP_PIT1 (CFG_MBAR + 0x00160000) -#define MMAP_PIT2 (CFG_MBAR + 0x00170000) -#define MMAP_PIT3 (CFG_MBAR + 0x00180000) -#define MMAP_MDHA (CFG_MBAR + 0x00190000) -#define MMAP_RNG (CFG_MBAR + 0x001A0000) -#define MMAP_SKHA (CFG_MBAR + 0x001B0000) -#define MMAP_USB (CFG_MBAR + 0x001C0000) -#define MMAP_PWM0 (CFG_MBAR + 0x001D0000) +#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000) +#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040) +#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) +#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100) +#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110) +#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120) +#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130) +#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200) +#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240) +#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280) +#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300) +#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340) +#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400) +#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440) +#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480) +#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0) +#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00) +#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00) +#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00) +#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00001000) +#define MMAP_FEC0FIFO (CONFIG_SYS_MBAR + 0x00001400) +#define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00001800) +#define MMAP_FEC1FIFO (CONFIG_SYS_MBAR + 0x00001C00) +#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000) +#define MMAP_RCM (CONFIG_SYS_MBAR + 0x00110000) +#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110004) +#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000) +#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000) +#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000) +#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000) +#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000) +#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000) +#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000) +#define MMAP_MDHA (CONFIG_SYS_MBAR + 0x00190000) +#define MMAP_RNG (CONFIG_SYS_MBAR + 0x001A0000) +#define MMAP_SKHA (CONFIG_SYS_MBAR + 0x001B0000) +#define MMAP_USB (CONFIG_SYS_MBAR + 0x001C0000) +#define MMAP_PWM0 (CONFIG_SYS_MBAR + 0x001D0000) /* System configuration registers */ diff --git a/include/asm-m68k/immap_5282.h b/include/asm-m68k/immap_5282.h index e82960a..e96463be 100644 --- a/include/asm-m68k/immap_5282.h +++ b/include/asm-m68k/immap_5282.h @@ -25,42 +25,42 @@ #ifndef __IMMAP_5282__ #define __IMMAP_5282__ -#define MMAP_SCM (CFG_MBAR + 0x00000000) -#define MMAP_SDRAMC (CFG_MBAR + 0x00000040) -#define MMAP_FBCS (CFG_MBAR + 0x00000080) -#define MMAP_DMA0 (CFG_MBAR + 0x00000100) -#define MMAP_DMA1 (CFG_MBAR + 0x00000140) -#define MMAP_DMA2 (CFG_MBAR + 0x00000180) -#define MMAP_DMA3 (CFG_MBAR + 0x000001C0) -#define MMAP_UART0 (CFG_MBAR + 0x00000200) -#define MMAP_UART1 (CFG_MBAR + 0x00000240) -#define MMAP_UART2 (CFG_MBAR + 0x00000280) -#define MMAP_I2C (CFG_MBAR + 0x00000300) -#define MMAP_QSPI (CFG_MBAR + 0x00000340) -#define MMAP_DTMR0 (CFG_MBAR + 0x00000400) -#define MMAP_DTMR1 (CFG_MBAR + 0x00000440) -#define MMAP_DTMR2 (CFG_MBAR + 0x00000480) -#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0) -#define MMAP_INTC0 (CFG_MBAR + 0x00000C00) -#define MMAP_INTC1 (CFG_MBAR + 0x00000D00) -#define MMAP_INTCACK (CFG_MBAR + 0x00000F00) -#define MMAP_FEC (CFG_MBAR + 0x00001000) -#define MMAP_FECFIFO (CFG_MBAR + 0x00001400) -#define MMAP_GPIO (CFG_MBAR + 0x00100000) -#define MMAP_CCM (CFG_MBAR + 0x00110000) -#define MMAP_PLL (CFG_MBAR + 0x00120000) -#define MMAP_EPORT (CFG_MBAR + 0x00130000) -#define MMAP_WDOG (CFG_MBAR + 0x00140000) -#define MMAP_PIT0 (CFG_MBAR + 0x00150000) -#define MMAP_PIT1 (CFG_MBAR + 0x00160000) -#define MMAP_PIT2 (CFG_MBAR + 0x00170000) -#define MMAP_PIT3 (CFG_MBAR + 0x00180000) -#define MMAP_QADC (CFG_MBAR + 0x00190000) -#define MMAP_GPTMRA (CFG_MBAR + 0x001A0000) -#define MMAP_GPTMRB (CFG_MBAR + 0x001B0000) -#define MMAP_CAN (CFG_MBAR + 0x001C0000) -#define MMAP_CFMC (CFG_MBAR + 0x001D0000) -#define MMAP_CFMMEM (CFG_MBAR + 0x04000000) +#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000) +#define MMAP_SDRAMC (CONFIG_SYS_MBAR + 0x00000040) +#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) +#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100) +#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000140) +#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000180) +#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x000001C0) +#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200) +#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240) +#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280) +#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300) +#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340) +#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400) +#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440) +#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480) +#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0) +#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00) +#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00) +#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00) +#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00001000) +#define MMAP_FECFIFO (CONFIG_SYS_MBAR + 0x00001400) +#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000) +#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110000) +#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000) +#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000) +#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000) +#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000) +#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000) +#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000) +#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000) +#define MMAP_QADC (CONFIG_SYS_MBAR + 0x00190000) +#define MMAP_GPTMRA (CONFIG_SYS_MBAR + 0x001A0000) +#define MMAP_GPTMRB (CONFIG_SYS_MBAR + 0x001B0000) +#define MMAP_CAN (CONFIG_SYS_MBAR + 0x001C0000) +#define MMAP_CFMC (CONFIG_SYS_MBAR + 0x001D0000) +#define MMAP_CFMMEM (CONFIG_SYS_MBAR + 0x04000000) /* System Control Module */ typedef struct scm_ctrl { diff --git a/include/asm-m68k/immap_547x_8x.h b/include/asm-m68k/immap_547x_8x.h index 54ef40f..c221936 100644 --- a/include/asm-m68k/immap_547x_8x.h +++ b/include/asm-m68k/immap_547x_8x.h @@ -26,36 +26,36 @@ #ifndef __IMMAP_547x_8x__ #define __IMMAP_547x_8x__ -#define MMAP_SIU (CFG_MBAR + 0x00000000) -#define MMAP_SDRAM (CFG_MBAR + 0x00000100) -#define MMAP_XARB (CFG_MBAR + 0x00000240) -#define MMAP_FBCS (CFG_MBAR + 0x00000500) -#define MMAP_INTC0 (CFG_MBAR + 0x00000700) -#define MMAP_GPTMR (CFG_MBAR + 0x00000800) -#define MMAP_SLT0 (CFG_MBAR + 0x00000900) -#define MMAP_SLT1 (CFG_MBAR + 0x00000910) -#define MMAP_GPIO (CFG_MBAR + 0x00000A00) -#define MMAP_PCI (CFG_MBAR + 0x00000B00) -#define MMAP_PCIARB (CFG_MBAR + 0x00000C00) -#define MMAP_EXTDMA (CFG_MBAR + 0x00000D00) -#define MMAP_EPORT (CFG_MBAR + 0x00000F00) -#define MMAP_CTM (CFG_MBAR + 0x00007F00) -#define MMAP_MCDMA (CFG_MBAR + 0x00008000) -#define MMAP_SCPCI (CFG_MBAR + 0x00008400) -#define MMAP_UART0 (CFG_MBAR + 0x00008600) -#define MMAP_UART1 (CFG_MBAR + 0x00008700) -#define MMAP_UART2 (CFG_MBAR + 0x00008800) -#define MMAP_UART3 (CFG_MBAR + 0x00008900) -#define MMAP_DSPI (CFG_MBAR + 0x00008A00) -#define MMAP_I2C (CFG_MBAR + 0x00008F00) -#define MMAP_FEC0 (CFG_MBAR + 0x00009000) -#define MMAP_FEC1 (CFG_MBAR + 0x00009800) -#define MMAP_CAN0 (CFG_MBAR + 0x0000A000) -#define MMAP_CAN1 (CFG_MBAR + 0x0000A800) -#define MMAP_USBD (CFG_MBAR + 0x0000B000) -#define MMAP_SRAM (CFG_MBAR + 0x00010000) -#define MMAP_SRAMCFG (CFG_MBAR + 0x0001FF00) -#define MMAP_SEC (CFG_MBAR + 0x00020000) +#define MMAP_SIU (CONFIG_SYS_MBAR + 0x00000000) +#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000100) +#define MMAP_XARB (CONFIG_SYS_MBAR + 0x00000240) +#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000500) +#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000700) +#define MMAP_GPTMR (CONFIG_SYS_MBAR + 0x00000800) +#define MMAP_SLT0 (CONFIG_SYS_MBAR + 0x00000900) +#define MMAP_SLT1 (CONFIG_SYS_MBAR + 0x00000910) +#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000A00) +#define MMAP_PCI (CONFIG_SYS_MBAR + 0x00000B00) +#define MMAP_PCIARB (CONFIG_SYS_MBAR + 0x00000C00) +#define MMAP_EXTDMA (CONFIG_SYS_MBAR + 0x00000D00) +#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00000F00) +#define MMAP_CTM (CONFIG_SYS_MBAR + 0x00007F00) +#define MMAP_MCDMA (CONFIG_SYS_MBAR + 0x00008000) +#define MMAP_SCPCI (CONFIG_SYS_MBAR + 0x00008400) +#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00008600) +#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00008700) +#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00008800) +#define MMAP_UART3 (CONFIG_SYS_MBAR + 0x00008900) +#define MMAP_DSPI (CONFIG_SYS_MBAR + 0x00008A00) +#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00008F00) +#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00009000) +#define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00009800) +#define MMAP_CAN0 (CONFIG_SYS_MBAR + 0x0000A000) +#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x0000A800) +#define MMAP_USBD (CONFIG_SYS_MBAR + 0x0000B000) +#define MMAP_SRAM (CONFIG_SYS_MBAR + 0x00010000) +#define MMAP_SRAMCFG (CONFIG_SYS_MBAR + 0x0001FF00) +#define MMAP_SEC (CONFIG_SYS_MBAR + 0x00020000) #include diff --git a/include/asm-m68k/m5249.h b/include/asm-m68k/m5249.h index facf0c9..feb675c 100644 --- a/include/asm-m68k/m5249.h +++ b/include/asm-m68k/m5249.h @@ -31,14 +31,14 @@ /* * useful definitions for reading/writing MBAR offset memory */ -#define mbar_readLong(x) *((volatile unsigned long *) (CFG_MBAR + x)) -#define mbar_writeLong(x,y) *((volatile unsigned long *) (CFG_MBAR + x)) = y -#define mbar_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR + x)) = y -#define mbar_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR + x)) = y -#define mbar2_readLong(x) *((volatile unsigned long *) (CFG_MBAR2 + x)) -#define mbar2_writeLong(x,y) *((volatile unsigned long *) (CFG_MBAR2 + x)) = y -#define mbar2_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR2 + x)) = y -#define mbar2_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR2 + x)) = y +#define mbar_readLong(x) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) +#define mbar_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y +#define mbar_writeShort(x,y) *((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) = y +#define mbar_writeByte(x,y) *((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) = y +#define mbar2_readLong(x) *((volatile unsigned long *) (CONFIG_SYS_MBAR2 + x)) +#define mbar2_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR2 + x)) = y +#define mbar2_writeShort(x,y) *((volatile unsigned short *) (CONFIG_SYS_MBAR2 + x)) = y +#define mbar2_writeByte(x,y) *((volatile unsigned char *) (CONFIG_SYS_MBAR2 + x)) = y /* * Size of internal RAM diff --git a/include/asm-m68k/m5271.h b/include/asm-m68k/m5271.h index be34398..000f0a5 100644 --- a/include/asm-m68k/m5271.h +++ b/include/asm-m68k/m5271.h @@ -28,12 +28,12 @@ #ifndef _MCF5271_H_ #define _MCF5271_H_ -#define mbar_readLong(x) *((volatile unsigned long *) (CFG_MBAR + x)) -#define mbar_readShort(x) *((volatile unsigned short *) (CFG_MBAR + x)) -#define mbar_readByte(x) *((volatile unsigned char *) (CFG_MBAR + x)) -#define mbar_writeLong(x,y) *((volatile unsigned long *) (CFG_MBAR + x)) = y -#define mbar_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR + x)) = y -#define mbar_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR + x)) = y +#define mbar_readLong(x) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) +#define mbar_readShort(x) *((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) +#define mbar_readByte(x) *((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) +#define mbar_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y +#define mbar_writeShort(x,y) *((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) = y +#define mbar_writeByte(x,y) *((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) = y #define MCF_FMPLL_SYNCR 0x120000 #define MCF_FMPLL_SYNSR 0x120004 diff --git a/include/asm-m68k/m5282.h b/include/asm-m68k/m5282.h index f6a6b04..772c7e0 100644 --- a/include/asm-m68k/m5282.h +++ b/include/asm-m68k/m5282.h @@ -125,112 +125,112 @@ /* General Purpose I/O Module GPIO */ -#define MCFGPIO_PORTA (*(vu_char *) (CFG_MBAR+0x100000)) -#define MCFGPIO_PORTB (*(vu_char *) (CFG_MBAR+0x100001)) -#define MCFGPIO_PORTC (*(vu_char *) (CFG_MBAR+0x100002)) -#define MCFGPIO_PORTD (*(vu_char *) (CFG_MBAR+0x100003)) -#define MCFGPIO_PORTE (*(vu_char *) (CFG_MBAR+0x100004)) -#define MCFGPIO_PORTF (*(vu_char *) (CFG_MBAR+0x100005)) -#define MCFGPIO_PORTG (*(vu_char *) (CFG_MBAR+0x100006)) -#define MCFGPIO_PORTH (*(vu_char *) (CFG_MBAR+0x100007)) -#define MCFGPIO_PORTJ (*(vu_char *) (CFG_MBAR+0x100008)) -#define MCFGPIO_PORTDD (*(vu_char *) (CFG_MBAR+0x100009)) -#define MCFGPIO_PORTEH (*(vu_char *) (CFG_MBAR+0x10000A)) -#define MCFGPIO_PORTEL (*(vu_char *) (CFG_MBAR+0x10000B)) -#define MCFGPIO_PORTAS (*(vu_char *) (CFG_MBAR+0x10000C)) -#define MCFGPIO_PORTQS (*(vu_char *) (CFG_MBAR+0x10000D)) -#define MCFGPIO_PORTSD (*(vu_char *) (CFG_MBAR+0x10000E)) -#define MCFGPIO_PORTTC (*(vu_char *) (CFG_MBAR+0x10000F)) -#define MCFGPIO_PORTTD (*(vu_char *) (CFG_MBAR+0x100010)) -#define MCFGPIO_PORTUA (*(vu_char *) (CFG_MBAR+0x100011)) - -#define MCFGPIO_DDRA (*(vu_char *) (CFG_MBAR+0x100014)) -#define MCFGPIO_DDRB (*(vu_char *) (CFG_MBAR+0x100015)) -#define MCFGPIO_DDRC (*(vu_char *) (CFG_MBAR+0x100016)) -#define MCFGPIO_DDRD (*(vu_char *) (CFG_MBAR+0x100017)) -#define MCFGPIO_DDRE (*(vu_char *) (CFG_MBAR+0x100018)) -#define MCFGPIO_DDRF (*(vu_char *) (CFG_MBAR+0x100019)) -#define MCFGPIO_DDRG (*(vu_char *) (CFG_MBAR+0x10001A)) -#define MCFGPIO_DDRH (*(vu_char *) (CFG_MBAR+0x10001B)) -#define MCFGPIO_DDRJ (*(vu_char *) (CFG_MBAR+0x10001C)) -#define MCFGPIO_DDRDD (*(vu_char *) (CFG_MBAR+0x10001D)) -#define MCFGPIO_DDREH (*(vu_char *) (CFG_MBAR+0x10001E)) -#define MCFGPIO_DDREL (*(vu_char *) (CFG_MBAR+0x10001F)) -#define MCFGPIO_DDRAS (*(vu_char *) (CFG_MBAR+0x100020)) -#define MCFGPIO_DDRQS (*(vu_char *) (CFG_MBAR+0x100021)) -#define MCFGPIO_DDRSD (*(vu_char *) (CFG_MBAR+0x100022)) -#define MCFGPIO_DDRTC (*(vu_char *) (CFG_MBAR+0x100023)) -#define MCFGPIO_DDRTD (*(vu_char *) (CFG_MBAR+0x100024)) -#define MCFGPIO_DDRUA (*(vu_char *) (CFG_MBAR+0x100025)) - -#define MCFGPIO_PORTAP (*(vu_char *) (CFG_MBAR+0x100028)) -#define MCFGPIO_PORTBP (*(vu_char *) (CFG_MBAR+0x100029)) -#define MCFGPIO_PORTCP (*(vu_char *) (CFG_MBAR+0x10002A)) -#define MCFGPIO_PORTDP (*(vu_char *) (CFG_MBAR+0x10002B)) -#define MCFGPIO_PORTEP (*(vu_char *) (CFG_MBAR+0x10002C)) -#define MCFGPIO_PORTFP (*(vu_char *) (CFG_MBAR+0x10002D)) -#define MCFGPIO_PORTGP (*(vu_char *) (CFG_MBAR+0x10002E)) -#define MCFGPIO_PORTHP (*(vu_char *) (CFG_MBAR+0x10002F)) -#define MCFGPIO_PORTJP (*(vu_char *) (CFG_MBAR+0x100030)) -#define MCFGPIO_PORTDDP (*(vu_char *) (CFG_MBAR+0x100031)) -#define MCFGPIO_PORTEHP (*(vu_char *) (CFG_MBAR+0x100032)) -#define MCFGPIO_PORTELP (*(vu_char *) (CFG_MBAR+0x100033)) -#define MCFGPIO_PORTASP (*(vu_char *) (CFG_MBAR+0x100034)) -#define MCFGPIO_PORTQSP (*(vu_char *) (CFG_MBAR+0x100035)) -#define MCFGPIO_PORTSDP (*(vu_char *) (CFG_MBAR+0x100036)) -#define MCFGPIO_PORTTCP (*(vu_char *) (CFG_MBAR+0x100037)) -#define MCFGPIO_PORTTDP (*(vu_char *) (CFG_MBAR+0x100038)) -#define MCFGPIO_PORTUAP (*(vu_char *) (CFG_MBAR+0x100039)) - -#define MCFGPIO_SETA (*(vu_char *) (CFG_MBAR+0x100028)) -#define MCFGPIO_SETB (*(vu_char *) (CFG_MBAR+0x100029)) -#define MCFGPIO_SETC (*(vu_char *) (CFG_MBAR+0x10002A)) -#define MCFGPIO_SETD (*(vu_char *) (CFG_MBAR+0x10002B)) -#define MCFGPIO_SETE (*(vu_char *) (CFG_MBAR+0x10002C)) -#define MCFGPIO_SETF (*(vu_char *) (CFG_MBAR+0x10002D)) -#define MCFGPIO_SETG (*(vu_char *) (CFG_MBAR+0x10002E)) -#define MCFGPIO_SETH (*(vu_char *) (CFG_MBAR+0x10002F)) -#define MCFGPIO_SETJ (*(vu_char *) (CFG_MBAR+0x100030)) -#define MCFGPIO_SETDD (*(vu_char *) (CFG_MBAR+0x100031)) -#define MCFGPIO_SETEH (*(vu_char *) (CFG_MBAR+0x100032)) -#define MCFGPIO_SETEL (*(vu_char *) (CFG_MBAR+0x100033)) -#define MCFGPIO_SETAS (*(vu_char *) (CFG_MBAR+0x100034)) -#define MCFGPIO_SETQS (*(vu_char *) (CFG_MBAR+0x100035)) -#define MCFGPIO_SETSD (*(vu_char *) (CFG_MBAR+0x100036)) -#define MCFGPIO_SETTC (*(vu_char *) (CFG_MBAR+0x100037)) -#define MCFGPIO_SETTD (*(vu_char *) (CFG_MBAR+0x100038)) -#define MCFGPIO_SETUA (*(vu_char *) (CFG_MBAR+0x100039)) - -#define MCFGPIO_CLRA (*(vu_char *) (CFG_MBAR+0x10003C)) -#define MCFGPIO_CLRB (*(vu_char *) (CFG_MBAR+0x10003D)) -#define MCFGPIO_CLRC (*(vu_char *) (CFG_MBAR+0x10003E)) -#define MCFGPIO_CLRD (*(vu_char *) (CFG_MBAR+0x10003F)) -#define MCFGPIO_CLRE (*(vu_char *) (CFG_MBAR+0x100040)) -#define MCFGPIO_CLRF (*(vu_char *) (CFG_MBAR+0x100041)) -#define MCFGPIO_CLRG (*(vu_char *) (CFG_MBAR+0x100042)) -#define MCFGPIO_CLRH (*(vu_char *) (CFG_MBAR+0x100043)) -#define MCFGPIO_CLRJ (*(vu_char *) (CFG_MBAR+0x100044)) -#define MCFGPIO_CLRDD (*(vu_char *) (CFG_MBAR+0x100045)) -#define MCFGPIO_CLREH (*(vu_char *) (CFG_MBAR+0x100046)) -#define MCFGPIO_CLREL (*(vu_char *) (CFG_MBAR+0x100047)) -#define MCFGPIO_CLRAS (*(vu_char *) (CFG_MBAR+0x100048)) -#define MCFGPIO_CLRQS (*(vu_char *) (CFG_MBAR+0x100049)) -#define MCFGPIO_CLRSD (*(vu_char *) (CFG_MBAR+0x10004A)) -#define MCFGPIO_CLRTC (*(vu_char *) (CFG_MBAR+0x10004B)) -#define MCFGPIO_CLRTD (*(vu_char *) (CFG_MBAR+0x10004C)) -#define MCFGPIO_CLRUA (*(vu_char *) (CFG_MBAR+0x10004D)) - -#define MCFGPIO_PBCDPAR (*(vu_char *) (CFG_MBAR+0x100050)) -#define MCFGPIO_PFPAR (*(vu_char *) (CFG_MBAR+0x100051)) -#define MCFGPIO_PEPAR (*(vu_short *)(CFG_MBAR+0x100052)) -#define MCFGPIO_PJPAR (*(vu_char *) (CFG_MBAR+0x100054)) -#define MCFGPIO_PSDPAR (*(vu_char *) (CFG_MBAR+0x100055)) -#define MCFGPIO_PASPAR (*(vu_short *)(CFG_MBAR+0x100056)) -#define MCFGPIO_PEHLPAR (*(vu_char *) (CFG_MBAR+0x100058)) -#define MCFGPIO_PQSPAR (*(vu_char *) (CFG_MBAR+0x100059)) -#define MCFGPIO_PTCPAR (*(vu_char *) (CFG_MBAR+0x10005A)) -#define MCFGPIO_PTDPAR (*(vu_char *) (CFG_MBAR+0x10005B)) -#define MCFGPIO_PUAPAR (*(vu_char *) (CFG_MBAR+0x10005C)) +#define MCFGPIO_PORTA (*(vu_char *) (CONFIG_SYS_MBAR+0x100000)) +#define MCFGPIO_PORTB (*(vu_char *) (CONFIG_SYS_MBAR+0x100001)) +#define MCFGPIO_PORTC (*(vu_char *) (CONFIG_SYS_MBAR+0x100002)) +#define MCFGPIO_PORTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100003)) +#define MCFGPIO_PORTE (*(vu_char *) (CONFIG_SYS_MBAR+0x100004)) +#define MCFGPIO_PORTF (*(vu_char *) (CONFIG_SYS_MBAR+0x100005)) +#define MCFGPIO_PORTG (*(vu_char *) (CONFIG_SYS_MBAR+0x100006)) +#define MCFGPIO_PORTH (*(vu_char *) (CONFIG_SYS_MBAR+0x100007)) +#define MCFGPIO_PORTJ (*(vu_char *) (CONFIG_SYS_MBAR+0x100008)) +#define MCFGPIO_PORTDD (*(vu_char *) (CONFIG_SYS_MBAR+0x100009)) +#define MCFGPIO_PORTEH (*(vu_char *) (CONFIG_SYS_MBAR+0x10000A)) +#define MCFGPIO_PORTEL (*(vu_char *) (CONFIG_SYS_MBAR+0x10000B)) +#define MCFGPIO_PORTAS (*(vu_char *) (CONFIG_SYS_MBAR+0x10000C)) +#define MCFGPIO_PORTQS (*(vu_char *) (CONFIG_SYS_MBAR+0x10000D)) +#define MCFGPIO_PORTSD (*(vu_char *) (CONFIG_SYS_MBAR+0x10000E)) +#define MCFGPIO_PORTTC (*(vu_char *) (CONFIG_SYS_MBAR+0x10000F)) +#define MCFGPIO_PORTTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100010)) +#define MCFGPIO_PORTUA (*(vu_char *) (CONFIG_SYS_MBAR+0x100011)) + +#define MCFGPIO_DDRA (*(vu_char *) (CONFIG_SYS_MBAR+0x100014)) +#define MCFGPIO_DDRB (*(vu_char *) (CONFIG_SYS_MBAR+0x100015)) +#define MCFGPIO_DDRC (*(vu_char *) (CONFIG_SYS_MBAR+0x100016)) +#define MCFGPIO_DDRD (*(vu_char *) (CONFIG_SYS_MBAR+0x100017)) +#define MCFGPIO_DDRE (*(vu_char *) (CONFIG_SYS_MBAR+0x100018)) +#define MCFGPIO_DDRF (*(vu_char *) (CONFIG_SYS_MBAR+0x100019)) +#define MCFGPIO_DDRG (*(vu_char *) (CONFIG_SYS_MBAR+0x10001A)) +#define MCFGPIO_DDRH (*(vu_char *) (CONFIG_SYS_MBAR+0x10001B)) +#define MCFGPIO_DDRJ (*(vu_char *) (CONFIG_SYS_MBAR+0x10001C)) +#define MCFGPIO_DDRDD (*(vu_char *) (CONFIG_SYS_MBAR+0x10001D)) +#define MCFGPIO_DDREH (*(vu_char *) (CONFIG_SYS_MBAR+0x10001E)) +#define MCFGPIO_DDREL (*(vu_char *) (CONFIG_SYS_MBAR+0x10001F)) +#define MCFGPIO_DDRAS (*(vu_char *) (CONFIG_SYS_MBAR+0x100020)) +#define MCFGPIO_DDRQS (*(vu_char *) (CONFIG_SYS_MBAR+0x100021)) +#define MCFGPIO_DDRSD (*(vu_char *) (CONFIG_SYS_MBAR+0x100022)) +#define MCFGPIO_DDRTC (*(vu_char *) (CONFIG_SYS_MBAR+0x100023)) +#define MCFGPIO_DDRTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100024)) +#define MCFGPIO_DDRUA (*(vu_char *) (CONFIG_SYS_MBAR+0x100025)) + +#define MCFGPIO_PORTAP (*(vu_char *) (CONFIG_SYS_MBAR+0x100028)) +#define MCFGPIO_PORTBP (*(vu_char *) (CONFIG_SYS_MBAR+0x100029)) +#define MCFGPIO_PORTCP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002A)) +#define MCFGPIO_PORTDP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002B)) +#define MCFGPIO_PORTEP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002C)) +#define MCFGPIO_PORTFP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002D)) +#define MCFGPIO_PORTGP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002E)) +#define MCFGPIO_PORTHP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002F)) +#define MCFGPIO_PORTJP (*(vu_char *) (CONFIG_SYS_MBAR+0x100030)) +#define MCFGPIO_PORTDDP (*(vu_char *) (CONFIG_SYS_MBAR+0x100031)) +#define MCFGPIO_PORTEHP (*(vu_char *) (CONFIG_SYS_MBAR+0x100032)) +#define MCFGPIO_PORTELP (*(vu_char *) (CONFIG_SYS_MBAR+0x100033)) +#define MCFGPIO_PORTASP (*(vu_char *) (CONFIG_SYS_MBAR+0x100034)) +#define MCFGPIO_PORTQSP (*(vu_char *) (CONFIG_SYS_MBAR+0x100035)) +#define MCFGPIO_PORTSDP (*(vu_char *) (CONFIG_SYS_MBAR+0x100036)) +#define MCFGPIO_PORTTCP (*(vu_char *) (CONFIG_SYS_MBAR+0x100037)) +#define MCFGPIO_PORTTDP (*(vu_char *) (CONFIG_SYS_MBAR+0x100038)) +#define MCFGPIO_PORTUAP (*(vu_char *) (CONFIG_SYS_MBAR+0x100039)) + +#define MCFGPIO_SETA (*(vu_char *) (CONFIG_SYS_MBAR+0x100028)) +#define MCFGPIO_SETB (*(vu_char *) (CONFIG_SYS_MBAR+0x100029)) +#define MCFGPIO_SETC (*(vu_char *) (CONFIG_SYS_MBAR+0x10002A)) +#define MCFGPIO_SETD (*(vu_char *) (CONFIG_SYS_MBAR+0x10002B)) +#define MCFGPIO_SETE (*(vu_char *) (CONFIG_SYS_MBAR+0x10002C)) +#define MCFGPIO_SETF (*(vu_char *) (CONFIG_SYS_MBAR+0x10002D)) +#define MCFGPIO_SETG (*(vu_char *) (CONFIG_SYS_MBAR+0x10002E)) +#define MCFGPIO_SETH (*(vu_char *) (CONFIG_SYS_MBAR+0x10002F)) +#define MCFGPIO_SETJ (*(vu_char *) (CONFIG_SYS_MBAR+0x100030)) +#define MCFGPIO_SETDD (*(vu_char *) (CONFIG_SYS_MBAR+0x100031)) +#define MCFGPIO_SETEH (*(vu_char *) (CONFIG_SYS_MBAR+0x100032)) +#define MCFGPIO_SETEL (*(vu_char *) (CONFIG_SYS_MBAR+0x100033)) +#define MCFGPIO_SETAS (*(vu_char *) (CONFIG_SYS_MBAR+0x100034)) +#define MCFGPIO_SETQS (*(vu_char *) (CONFIG_SYS_MBAR+0x100035)) +#define MCFGPIO_SETSD (*(vu_char *) (CONFIG_SYS_MBAR+0x100036)) +#define MCFGPIO_SETTC (*(vu_char *) (CONFIG_SYS_MBAR+0x100037)) +#define MCFGPIO_SETTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100038)) +#define MCFGPIO_SETUA (*(vu_char *) (CONFIG_SYS_MBAR+0x100039)) + +#define MCFGPIO_CLRA (*(vu_char *) (CONFIG_SYS_MBAR+0x10003C)) +#define MCFGPIO_CLRB (*(vu_char *) (CONFIG_SYS_MBAR+0x10003D)) +#define MCFGPIO_CLRC (*(vu_char *) (CONFIG_SYS_MBAR+0x10003E)) +#define MCFGPIO_CLRD (*(vu_char *) (CONFIG_SYS_MBAR+0x10003F)) +#define MCFGPIO_CLRE (*(vu_char *) (CONFIG_SYS_MBAR+0x100040)) +#define MCFGPIO_CLRF (*(vu_char *) (CONFIG_SYS_MBAR+0x100041)) +#define MCFGPIO_CLRG (*(vu_char *) (CONFIG_SYS_MBAR+0x100042)) +#define MCFGPIO_CLRH (*(vu_char *) (CONFIG_SYS_MBAR+0x100043)) +#define MCFGPIO_CLRJ (*(vu_char *) (CONFIG_SYS_MBAR+0x100044)) +#define MCFGPIO_CLRDD (*(vu_char *) (CONFIG_SYS_MBAR+0x100045)) +#define MCFGPIO_CLREH (*(vu_char *) (CONFIG_SYS_MBAR+0x100046)) +#define MCFGPIO_CLREL (*(vu_char *) (CONFIG_SYS_MBAR+0x100047)) +#define MCFGPIO_CLRAS (*(vu_char *) (CONFIG_SYS_MBAR+0x100048)) +#define MCFGPIO_CLRQS (*(vu_char *) (CONFIG_SYS_MBAR+0x100049)) +#define MCFGPIO_CLRSD (*(vu_char *) (CONFIG_SYS_MBAR+0x10004A)) +#define MCFGPIO_CLRTC (*(vu_char *) (CONFIG_SYS_MBAR+0x10004B)) +#define MCFGPIO_CLRTD (*(vu_char *) (CONFIG_SYS_MBAR+0x10004C)) +#define MCFGPIO_CLRUA (*(vu_char *) (CONFIG_SYS_MBAR+0x10004D)) + +#define MCFGPIO_PBCDPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100050)) +#define MCFGPIO_PFPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100051)) +#define MCFGPIO_PEPAR (*(vu_short *)(CONFIG_SYS_MBAR+0x100052)) +#define MCFGPIO_PJPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100054)) +#define MCFGPIO_PSDPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100055)) +#define MCFGPIO_PASPAR (*(vu_short *)(CONFIG_SYS_MBAR+0x100056)) +#define MCFGPIO_PEHLPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100058)) +#define MCFGPIO_PQSPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100059)) +#define MCFGPIO_PTCPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x10005A)) +#define MCFGPIO_PTDPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x10005B)) +#define MCFGPIO_PUAPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x10005C)) /* Bit level definitions and macros */ #define MCFGPIO_PORT7 (0x80) @@ -327,25 +327,25 @@ /* System Conrol Module SCM */ -#define MCFSCM_RAMBAR (*(vu_long *) (CFG_MBAR+0x00000008)) -#define MCFSCM_CRSR (*(vu_char *) (CFG_MBAR+0x00000010)) -#define MCFSCM_CWCR (*(vu_char *) (CFG_MBAR+0x00000011)) -#define MCFSCM_LPICR (*(vu_char *) (CFG_MBAR+0x00000012)) -#define MCFSCM_CWSR (*(vu_char *) (CFG_MBAR+0x00000013)) - -#define MCFSCM_MPARK (*(vu_long *) (CFG_MBAR+0x0000001C)) -#define MCFSCM_MPR (*(vu_char *) (CFG_MBAR+0x00000020)) -#define MCFSCM_PACR0 (*(vu_char *) (CFG_MBAR+0x00000024)) -#define MCFSCM_PACR1 (*(vu_char *) (CFG_MBAR+0x00000025)) -#define MCFSCM_PACR2 (*(vu_char *) (CFG_MBAR+0x00000026)) -#define MCFSCM_PACR3 (*(vu_char *) (CFG_MBAR+0x00000027)) -#define MCFSCM_PACR4 (*(vu_char *) (CFG_MBAR+0x00000028)) -#define MCFSCM_PACR5 (*(vu_char *) (CFG_MBAR+0x0000002A)) -#define MCFSCM_PACR6 (*(vu_char *) (CFG_MBAR+0x0000002B)) -#define MCFSCM_PACR7 (*(vu_char *) (CFG_MBAR+0x0000002C)) -#define MCFSCM_PACR8 (*(vu_char *) (CFG_MBAR+0x0000002E)) -#define MCFSCM_GPACR0 (*(vu_char *) (CFG_MBAR+0x00000030)) -#define MCFSCM_GPACR1 (*(vu_char *) (CFG_MBAR+0x00000031)) +#define MCFSCM_RAMBAR (*(vu_long *) (CONFIG_SYS_MBAR+0x00000008)) +#define MCFSCM_CRSR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000010)) +#define MCFSCM_CWCR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000011)) +#define MCFSCM_LPICR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000012)) +#define MCFSCM_CWSR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000013)) + +#define MCFSCM_MPARK (*(vu_long *) (CONFIG_SYS_MBAR+0x0000001C)) +#define MCFSCM_MPR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000020)) +#define MCFSCM_PACR0 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000024)) +#define MCFSCM_PACR1 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000025)) +#define MCFSCM_PACR2 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000026)) +#define MCFSCM_PACR3 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000027)) +#define MCFSCM_PACR4 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000028)) +#define MCFSCM_PACR5 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002A)) +#define MCFSCM_PACR6 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002B)) +#define MCFSCM_PACR7 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002C)) +#define MCFSCM_PACR8 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002E)) +#define MCFSCM_GPACR0 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000030)) +#define MCFSCM_GPACR1 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000031)) #define MCFSCM_CRSR_EXT (0x80) #define MCFSCM_CRSR_CWDR (0x20) @@ -354,8 +354,8 @@ /* Reset Controller Module RCM */ -#define MCFRESET_RCR (*(vu_char *) (CFG_MBAR+0x00110000)) -#define MCFRESET_RSR (*(vu_char *) (CFG_MBAR+0x00110001)) +#define MCFRESET_RCR (*(vu_char *) (CONFIG_SYS_MBAR+0x00110000)) +#define MCFRESET_RSR (*(vu_char *) (CONFIG_SYS_MBAR+0x00110001)) #define MCFRESET_RCR_SOFTRST (0x80) #define MCFRESET_RCR_FRCRSTOUT (0x40) @@ -377,9 +377,9 @@ /* Chip Configuration Module CCM */ -#define MCFCCM_CCR (*(vu_short *)(CFG_MBAR+0x00110004)) -#define MCFCCM_RCON (*(vu_short *)(CFG_MBAR+0x00110008)) -#define MCFCCM_CIR (*(vu_short *)(CFG_MBAR+0x0011000A)) +#define MCFCCM_CCR (*(vu_short *)(CONFIG_SYS_MBAR+0x00110004)) +#define MCFCCM_RCON (*(vu_short *)(CONFIG_SYS_MBAR+0x00110008)) +#define MCFCCM_CIR (*(vu_short *)(CONFIG_SYS_MBAR+0x0011000A)) /* Bit level definitions and macros */ #define MCFCCM_CCR_LOAD (0x8000) @@ -394,18 +394,18 @@ /* Clock Module */ -#define MCFCLOCK_SYNCR (*(vu_short *)(CFG_MBAR+0x120000)) -#define MCFCLOCK_SYNSR (*(vu_char *) (CFG_MBAR+0x120002)) +#define MCFCLOCK_SYNCR (*(vu_short *)(CONFIG_SYS_MBAR+0x120000)) +#define MCFCLOCK_SYNSR (*(vu_char *) (CONFIG_SYS_MBAR+0x120002)) #define MCFCLOCK_SYNCR_MFD(x) (((x)&0x0007)<<12) #define MCFCLOCK_SYNCR_RFD(x) (((x)&0x0007)<<8) #define MCFCLOCK_SYNSR_LOCK 0x08 -#define MCFSDRAMC_DCR (*(vu_short *)(CFG_MBAR+0x00000040)) -#define MCFSDRAMC_DACR0 (*(vu_long *) (CFG_MBAR+0x00000048)) -#define MCFSDRAMC_DMR0 (*(vu_long *) (CFG_MBAR+0x0000004c)) -#define MCFSDRAMC_DACR1 (*(vu_long *) (CFG_MBAR+0x00000050)) -#define MCFSDRAMC_DMR1 (*(vu_long *) (CFG_MBAR+0x00000054)) +#define MCFSDRAMC_DCR (*(vu_short *)(CONFIG_SYS_MBAR+0x00000040)) +#define MCFSDRAMC_DACR0 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000048)) +#define MCFSDRAMC_DMR0 (*(vu_long *) (CONFIG_SYS_MBAR+0x0000004c)) +#define MCFSDRAMC_DACR1 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000050)) +#define MCFSDRAMC_DMR1 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000054)) #define MCFSDRAMC_DCR_NAM (0x2000) #define MCFSDRAMC_DCR_COC (0x1000) @@ -435,24 +435,24 @@ #define MCFSDRAMC_DMR_UD (0x00000002) #define MCFSDRAMC_DMR_V (0x00000001) -#define MCFWTM_WCR (*(vu_short *)(CFG_MBAR+0x00140000)) -#define MCFWTM_WMR (*(vu_short *)(CFG_MBAR+0x00140002)) -#define MCFWTM_WCNTR (*(vu_short *)(CFG_MBAR+0x00140004)) -#define MCFWTM_WSR (*(vu_short *)(CFG_MBAR+0x00140006)) +#define MCFWTM_WCR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140000)) +#define MCFWTM_WMR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140002)) +#define MCFWTM_WCNTR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140004)) +#define MCFWTM_WSR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140006)) /* Chip SELECT Module CSM */ -#define MCFCSM_CSAR0 (*(vu_short *)(CFG_MBAR+0x00000080)) -#define MCFCSM_CSMR0 (*(vu_long *) (CFG_MBAR+0x00000084)) -#define MCFCSM_CSCR0 (*(vu_short *)(CFG_MBAR+0x0000008a)) -#define MCFCSM_CSAR1 (*(vu_short *)(CFG_MBAR+0x0000008C)) -#define MCFCSM_CSMR1 (*(vu_long *) (CFG_MBAR+0x00000090)) -#define MCFCSM_CSCR1 (*(vu_short *)(CFG_MBAR+0x00000096)) -#define MCFCSM_CSAR2 (*(vu_short *)(CFG_MBAR+0x00000098)) -#define MCFCSM_CSMR2 (*(vu_long *) (CFG_MBAR+0x0000009C)) -#define MCFCSM_CSCR2 (*(vu_short *)(CFG_MBAR+0x000000A2)) -#define MCFCSM_CSAR3 (*(vu_short *)(CFG_MBAR+0x000000A4)) -#define MCFCSM_CSMR3 (*(vu_long *) (CFG_MBAR+0x000000A8)) -#define MCFCSM_CSCR3 (*(vu_short *)(CFG_MBAR+0x000000AE)) +#define MCFCSM_CSAR0 (*(vu_short *)(CONFIG_SYS_MBAR+0x00000080)) +#define MCFCSM_CSMR0 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000084)) +#define MCFCSM_CSCR0 (*(vu_short *)(CONFIG_SYS_MBAR+0x0000008a)) +#define MCFCSM_CSAR1 (*(vu_short *)(CONFIG_SYS_MBAR+0x0000008C)) +#define MCFCSM_CSMR1 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000090)) +#define MCFCSM_CSCR1 (*(vu_short *)(CONFIG_SYS_MBAR+0x00000096)) +#define MCFCSM_CSAR2 (*(vu_short *)(CONFIG_SYS_MBAR+0x00000098)) +#define MCFCSM_CSMR2 (*(vu_long *) (CONFIG_SYS_MBAR+0x0000009C)) +#define MCFCSM_CSCR2 (*(vu_short *)(CONFIG_SYS_MBAR+0x000000A2)) +#define MCFCSM_CSAR3 (*(vu_short *)(CONFIG_SYS_MBAR+0x000000A4)) +#define MCFCSM_CSMR3 (*(vu_long *) (CONFIG_SYS_MBAR+0x000000A8)) +#define MCFCSM_CSCR3 (*(vu_short *)(CONFIG_SYS_MBAR+0x000000AE)) #define MCFCSM_CSMR_BAM(x) ((x) & 0xFFFF0000) #define MCFCSM_CSMR_WP (1<<8) @@ -467,51 +467,51 @@ * General Purpose Timer (GPT) Module *********************************************************************/ -#define MCFGPTA_GPTIOS (*(vu_char *)(CFG_MBAR+0x1A0000)) -#define MCFGPTA_GPTCFORC (*(vu_char *)(CFG_MBAR+0x1A0001)) -#define MCFGPTA_GPTOC3M (*(vu_char *)(CFG_MBAR+0x1A0002)) -#define MCFGPTA_GPTOC3D (*(vu_char *)(CFG_MBAR+0x1A0003)) -#define MCFGPTA_GPTCNT (*(vu_short *)(CFG_MBAR+0x1A0004)) -#define MCFGPTA_GPTSCR1 (*(vu_char *)(CFG_MBAR+0x1A0006)) -#define MCFGPTA_GPTTOV (*(vu_char *)(CFG_MBAR+0x1A0008)) -#define MCFGPTA_GPTCTL1 (*(vu_char *)(CFG_MBAR+0x1A0009)) -#define MCFGPTA_GPTCTL2 (*(vu_char *)(CFG_MBAR+0x1A000B)) -#define MCFGPTA_GPTIE (*(vu_char *)(CFG_MBAR+0x1A000C)) -#define MCFGPTA_GPTSCR2 (*(vu_char *)(CFG_MBAR+0x1A000D)) -#define MCFGPTA_GPTFLG1 (*(vu_char *)(CFG_MBAR+0x1A000E)) -#define MCFGPTA_GPTFLG2 (*(vu_char *)(CFG_MBAR+0x1A000F)) -#define MCFGPTA_GPTC0 (*(vu_short *)(CFG_MBAR+0x1A0010)) -#define MCFGPTA_GPTC1 (*(vu_short *)(CFG_MBAR+0x1A0012)) -#define MCFGPTA_GPTC2 (*(vu_short *)(CFG_MBAR+0x1A0014)) -#define MCFGPTA_GPTC3 (*(vu_short *)(CFG_MBAR+0x1A0016)) -#define MCFGPTA_GPTPACTL (*(vu_char *)(CFG_MBAR+0x1A0018)) -#define MCFGPTA_GPTPAFLG (*(vu_char *)(CFG_MBAR+0x1A0019)) -#define MCFGPTA_GPTPACNT (*(vu_short *)(CFG_MBAR+0x1A001A)) -#define MCFGPTA_GPTPORT (*(vu_char *)(CFG_MBAR+0x1A001D)) -#define MCFGPTA_GPTDDR (*(vu_char *)(CFG_MBAR+0x1A001E)) - -#define MCFGPTB_GPTIOS (*(vu_char *)(CFG_MBAR+0x1B0000)) -#define MCFGPTB_GPTCFORC (*(vu_char *)(CFG_MBAR+0x1B0001)) -#define MCFGPTB_GPTOC3M (*(vu_char *)(CFG_MBAR+0x1B0002)) -#define MCFGPTB_GPTOC3D (*(vu_char *)(CFG_MBAR+0x1B0003)) -#define MCFGPTB_GPTCNT (*(vu_short *)(CFG_MBAR+0x1B0004)) -#define MCFGPTB_GPTSCR1 (*(vu_char *)(CFG_MBAR+0x1B0006)) -#define MCFGPTB_GPTTOV (*(vu_char *)(CFG_MBAR+0x1B0008)) -#define MCFGPTB_GPTCTL1 (*(vu_char *)(CFG_MBAR+0x1B0009)) -#define MCFGPTB_GPTCTL2 (*(vu_char *)(CFG_MBAR+0x1B000B)) -#define MCFGPTB_GPTIE (*(vu_char *)(CFG_MBAR+0x1B000C)) -#define MCFGPTB_GPTSCR2 (*(vu_char *)(CFG_MBAR+0x1B000D)) -#define MCFGPTB_GPTFLG1 (*(vu_char *)(CFG_MBAR+0x1B000E)) -#define MCFGPTB_GPTFLG2 (*(vu_char *)(CFG_MBAR+0x1B000F)) -#define MCFGPTB_GPTC0 (*(vu_short *)(CFG_MBAR+0x1B0010)) -#define MCFGPTB_GPTC1 (*(vu_short *)(CFG_MBAR+0x1B0012)) -#define MCFGPTB_GPTC2 (*(vu_short *)(CFG_MBAR+0x1B0014)) -#define MCFGPTB_GPTC3 (*(vu_short *)(CFG_MBAR+0x1B0016)) -#define MCFGPTB_GPTPACTL (*(vu_char *)(CFG_MBAR+0x1B0018)) -#define MCFGPTB_GPTPAFLG (*(vu_char *)(CFG_MBAR+0x1B0019)) -#define MCFGPTB_GPTPACNT (*(vu_short *)(CFG_MBAR+0x1B001A)) -#define MCFGPTB_GPTPORT (*(vu_char *)(CFG_MBAR+0x1B001D)) -#define MCFGPTB_GPTDDR (*(vu_char *)(CFG_MBAR+0x1B001E)) +#define MCFGPTA_GPTIOS (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0000)) +#define MCFGPTA_GPTCFORC (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0001)) +#define MCFGPTA_GPTOC3M (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0002)) +#define MCFGPTA_GPTOC3D (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0003)) +#define MCFGPTA_GPTCNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0004)) +#define MCFGPTA_GPTSCR1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0006)) +#define MCFGPTA_GPTTOV (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0008)) +#define MCFGPTA_GPTCTL1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0009)) +#define MCFGPTA_GPTCTL2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000B)) +#define MCFGPTA_GPTIE (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000C)) +#define MCFGPTA_GPTSCR2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000D)) +#define MCFGPTA_GPTFLG1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000E)) +#define MCFGPTA_GPTFLG2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000F)) +#define MCFGPTA_GPTC0 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0010)) +#define MCFGPTA_GPTC1 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0012)) +#define MCFGPTA_GPTC2 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0014)) +#define MCFGPTA_GPTC3 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0016)) +#define MCFGPTA_GPTPACTL (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0018)) +#define MCFGPTA_GPTPAFLG (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0019)) +#define MCFGPTA_GPTPACNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1A001A)) +#define MCFGPTA_GPTPORT (*(vu_char *)(CONFIG_SYS_MBAR+0x1A001D)) +#define MCFGPTA_GPTDDR (*(vu_char *)(CONFIG_SYS_MBAR+0x1A001E)) + +#define MCFGPTB_GPTIOS (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0000)) +#define MCFGPTB_GPTCFORC (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0001)) +#define MCFGPTB_GPTOC3M (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0002)) +#define MCFGPTB_GPTOC3D (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0003)) +#define MCFGPTB_GPTCNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0004)) +#define MCFGPTB_GPTSCR1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0006)) +#define MCFGPTB_GPTTOV (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0008)) +#define MCFGPTB_GPTCTL1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0009)) +#define MCFGPTB_GPTCTL2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000B)) +#define MCFGPTB_GPTIE (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000C)) +#define MCFGPTB_GPTSCR2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000D)) +#define MCFGPTB_GPTFLG1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000E)) +#define MCFGPTB_GPTFLG2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000F)) +#define MCFGPTB_GPTC0 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0010)) +#define MCFGPTB_GPTC1 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0012)) +#define MCFGPTB_GPTC2 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0014)) +#define MCFGPTB_GPTC3 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0016)) +#define MCFGPTB_GPTPACTL (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0018)) +#define MCFGPTB_GPTPAFLG (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0019)) +#define MCFGPTB_GPTPACNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1B001A)) +#define MCFGPTB_GPTPORT (*(vu_char *)(CONFIG_SYS_MBAR+0x1B001D)) +#define MCFGPTB_GPTDDR (*(vu_char *)(CONFIG_SYS_MBAR+0x1B001E)) /* Bit level definitions and macros */ #define MCFGPT_GPTIOS_IOS3 (0x08) @@ -596,7 +596,7 @@ /* Coldfire Flash Module CFM */ -#define MCFCFM_MCR (*(vu_short *)(CFG_MBAR+0x1D0000)) +#define MCFCFM_MCR (*(vu_short *)(CONFIG_SYS_MBAR+0x1D0000)) #define MCFCFM_MCR_LOCK (0x0400) #define MCFCFM_MCR_PVIE (0x0200) #define MCFCFM_MCR_AEIE (0x0100) @@ -604,23 +604,23 @@ #define MCFCFM_MCR_CCIE (0x0040) #define MCFCFM_MCR_KEYACC (0x0020) -#define MCFCFM_CLKD (*(vu_char *)(CFG_MBAR+0x1D0002)) +#define MCFCFM_CLKD (*(vu_char *)(CONFIG_SYS_MBAR+0x1D0002)) -#define MCFCFM_SEC (*(vu_long*) (CFG_MBAR+0x1D0008)) +#define MCFCFM_SEC (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0008)) #define MCFCFM_SEC_KEYEN (0x80000000) #define MCFCFM_SEC_SECSTAT (0x40000000) -#define MCFCFM_PROT (*(vu_long*) (CFG_MBAR+0x1D0010)) -#define MCFCFM_SACC (*(vu_long*) (CFG_MBAR+0x1D0014)) -#define MCFCFM_DACC (*(vu_long*) (CFG_MBAR+0x1D0018)) -#define MCFCFM_USTAT (*(vu_char*) (CFG_MBAR+0x1D0020)) +#define MCFCFM_PROT (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0010)) +#define MCFCFM_SACC (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0014)) +#define MCFCFM_DACC (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0018)) +#define MCFCFM_USTAT (*(vu_char*) (CONFIG_SYS_MBAR+0x1D0020)) #define MCFCFM_USTAT_CBEIF 0x80 #define MCFCFM_USTAT_CCIF 0x40 #define MCFCFM_USTAT_PVIOL 0x20 #define MCFCFM_USTAT_ACCERR 0x10 #define MCFCFM_USTAT_BLANK 0x04 -#define MCFCFM_CMD (*(vu_char*) (CFG_MBAR+0x1D0024)) +#define MCFCFM_CMD (*(vu_char*) (CONFIG_SYS_MBAR+0x1D0024)) #define MCFCFM_CMD_ERSVER 0x05 #define MCFCFM_CMD_PGERSVER 0x06 #define MCFCFM_CMD_PGM 0x20 -- cgit v1.1