From 82102d3fdeae0dcd79d9b3ab7daa96bebd5ad290 Mon Sep 17 00:00:00 2001 From: Anish Trivedi Date: Wed, 22 Jun 2011 17:49:45 -0500 Subject: ENGR00139206 MX6 USDHC eMMC 4.4 support New bit definitions in USDHC. Added is_usdhc variable to fsl_esdhc_cfg to distinguish between ESDHC and USDHC. Enabled DDR mode support in USDHC. Created a config to customize target delay for DDR mode. Modified USDHC pad settings to make DDR mode work for all emmcs at 50 MHz. Signed-off-by: Anish Trivedi --- include/asm-arm/arch-mx6/mx6_pins.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include/asm-arm/arch-mx6') diff --git a/include/asm-arm/arch-mx6/mx6_pins.h b/include/asm-arm/arch-mx6/mx6_pins.h index 2cc7114..f64473a 100644 --- a/include/asm-arm/arch-mx6/mx6_pins.h +++ b/include/asm-arm/arch-mx6/mx6_pins.h @@ -48,8 +48,8 @@ typedef enum iomux_config { PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) #define MX6Q_USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) #define MX6Q_ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ -- cgit v1.1