From d9abba8254c3e6b9a1d5c2e52c2d8088bbeb520f Mon Sep 17 00:00:00 2001 From: C Nauman Date: Tue, 26 Oct 2010 23:04:31 +0900 Subject: Add generic support for samsung s3c2440 This patch adds generic support for the Samsung s3c2440 processor. Global s3c24x0 changes to struct members converting from upper case to lower case. Signed-off-by: Craig Nauman Cc: kevin.morfitt@fearnside-systems.co.uk Signed-off-by: Minkyu Kang --- drivers/i2c/s3c24x0_i2c.c | 102 ++++++++++++++++++++-------------------- drivers/mtd/nand/s3c2410_nand.c | 25 +++++----- drivers/rtc/s3c24x0_rtc.c | 52 ++++++++++---------- drivers/serial/serial_s3c24x0.c | 26 +++++----- 4 files changed, 103 insertions(+), 102 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c index c8371cf..ba6f39b 100644 --- a/drivers/i2c/s3c24x0_i2c.c +++ b/drivers/i2c/s3c24x0_i2c.c @@ -58,10 +58,10 @@ static int GetI2CSDA(void) struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); #ifdef CONFIG_S3C2410 - return (readl(&gpio->GPEDAT) & 0x8000) >> 15; + return (readl(&gpio->gpedat) & 0x8000) >> 15; #endif #ifdef CONFIG_S3C2400 - return (readl(&gpio->PGDAT) & 0x0020) >> 5; + return (readl(&gpio->pgdat) & 0x0020) >> 5; #endif } @@ -77,10 +77,10 @@ static void SetI2CSCL(int x) struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); #ifdef CONFIG_S3C2410 - writel((readl(&gpio->GPEDAT) & ~0x4000) | (x & 1) << 14, &gpio->GPEDAT); + writel((readl(&gpio->gpedat) & ~0x4000) | (x & 1) << 14, &gpio->gpedat); #endif #ifdef CONFIG_S3C2400 - writel((readl(&gpio->PGDAT) & ~0x0040) | (x & 1) << 6, &gpio->PGDAT); + writel((readl(&gpio->pgdat) & ~0x0040) | (x & 1) << 6, &gpio->pgdat); #endif } @@ -90,26 +90,26 @@ static int WaitForXfer(void) int i; i = I2C_TIMEOUT * 10000; - while (!(readl(&i2c->IICCON) & I2CCON_IRPND) && (i > 0)) { + while (!(readl(&i2c->iiccon) & I2CCON_IRPND) && (i > 0)) { udelay(100); i--; } - return (readl(&i2c->IICCON) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT; + return (readl(&i2c->iiccon) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT; } static int IsACK(void) { struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c(); - return !(readl(&i2c->IICSTAT) & I2CSTAT_NACK); + return !(readl(&i2c->iicstat) & I2CSTAT_NACK); } static void ReadWriteByte(void) { struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c(); - writel(readl(&i2c->IICCON) & ~I2CCON_IRPND, &i2c->IICCON); + writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon); } void i2c_init(int speed, int slaveadd) @@ -122,30 +122,30 @@ void i2c_init(int speed, int slaveadd) /* wait for some time to give previous transfer a chance to finish */ i = I2C_TIMEOUT * 1000; - while ((readl(&i2c->IICSTAT) && I2CSTAT_BSY) && (i > 0)) { + while ((readl(&i2c->iicstat) && I2CSTAT_BSY) && (i > 0)) { udelay(1000); i--; } - if ((readl(&i2c->IICSTAT) & I2CSTAT_BSY) || GetI2CSDA() == 0) { + if ((readl(&i2c->iicstat) & I2CSTAT_BSY) || GetI2CSDA() == 0) { #ifdef CONFIG_S3C2410 - ulong old_gpecon = readl(&gpio->GPECON); + ulong old_gpecon = readl(&gpio->gpecon); #endif #ifdef CONFIG_S3C2400 - ulong old_gpecon = readl(&gpio->PGCON); + ulong old_gpecon = readl(&gpio->pgcon); #endif /* bus still busy probably by (most) previously interrupted transfer */ #ifdef CONFIG_S3C2410 /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */ - writel((readl(&gpio->GPECON) & ~0xF0000000) | 0x10000000, - &gpio->GPECON); + writel((readl(&gpio->gpecon) & ~0xF0000000) | 0x10000000, + &gpio->gpecon); #endif #ifdef CONFIG_S3C2400 /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */ - writel((readl(&gpio->PGCON) & ~0x00003c00) | 0x00001000, - &gpio->PGCON); + writel((readl(&gpio->pgcon) & ~0x00003c00) | 0x00001000, + &gpio->pgcon); #endif /* toggle I2CSCL until bus idle */ @@ -164,10 +164,10 @@ void i2c_init(int speed, int slaveadd) /* restore pin functions */ #ifdef CONFIG_S3C2410 - writel(old_gpecon, &gpio->GPECON); + writel(old_gpecon, &gpio->gpecon); #endif #ifdef CONFIG_S3C2400 - writel(old_gpecon, &gpio->PGCON); + writel(old_gpecon, &gpio->pgcon); #endif } @@ -183,13 +183,13 @@ void i2c_init(int speed, int slaveadd) /* set prescaler, divisor according to freq, also set * ACKGEN, IRQ */ - writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->IICCON); + writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon); /* init to SLAVE REVEIVE and set slaveaddr */ - writel(0, &i2c->IICSTAT); - writel(slaveadd, &i2c->IICADD); + writel(0, &i2c->iicstat); + writel(slaveadd, &i2c->iicadd); /* program Master Transmit (and implicit STOP) */ - writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->IICSTAT); + writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat); } @@ -218,47 +218,47 @@ int i2c_transfer(unsigned char cmd_type, /* Check I2C bus idle */ i = I2C_TIMEOUT * 1000; - while ((readl(&i2c->IICSTAT) & I2CSTAT_BSY) && (i > 0)) { + while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) { udelay(1000); i--; } - if (readl(&i2c->IICSTAT) & I2CSTAT_BSY) + if (readl(&i2c->iicstat) & I2CSTAT_BSY) return I2C_NOK_TOUT; - writel(readl(&i2c->IICCON) | 0x80, &i2c->IICCON); + writel(readl(&i2c->iiccon) | 0x80, &i2c->iiccon); result = I2C_OK; switch (cmd_type) { case I2C_WRITE: if (addr && addr_len) { - writel(chip, &i2c->IICDS); + writel(chip, &i2c->iicds); /* send START */ writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP, - &i2c->IICSTAT); + &i2c->iicstat); i = 0; while ((i < addr_len) && (result == I2C_OK)) { result = WaitForXfer(); - writel(addr[i], &i2c->IICDS); + writel(addr[i], &i2c->iicds); ReadWriteByte(); i++; } i = 0; while ((i < data_len) && (result == I2C_OK)) { result = WaitForXfer(); - writel(data[i], &i2c->IICDS); + writel(data[i], &i2c->iicds); ReadWriteByte(); i++; } } else { - writel(chip, &i2c->IICDS); + writel(chip, &i2c->iicds); /* send START */ writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP, - &i2c->IICSTAT); + &i2c->iicstat); i = 0; while ((i < data_len) && (result = I2C_OK)) { result = WaitForXfer(); - writel(data[i], &i2c->IICDS); + writel(data[i], &i2c->iicds); ReadWriteByte(); i++; } @@ -268,42 +268,42 @@ int i2c_transfer(unsigned char cmd_type, result = WaitForXfer(); /* send STOP */ - writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT); + writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat); ReadWriteByte(); break; case I2C_READ: if (addr && addr_len) { - writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->IICSTAT); - writel(chip, &i2c->IICDS); + writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat); + writel(chip, &i2c->iicds); /* send START */ - writel(readl(&i2c->IICSTAT) | I2C_START_STOP, - &i2c->IICSTAT); + writel(readl(&i2c->iicstat) | I2C_START_STOP, + &i2c->iicstat); result = WaitForXfer(); if (IsACK()) { i = 0; while ((i < addr_len) && (result == I2C_OK)) { - writel(addr[i], &i2c->IICDS); + writel(addr[i], &i2c->iicds); ReadWriteByte(); result = WaitForXfer(); i++; } - writel(chip, &i2c->IICDS); + writel(chip, &i2c->iicds); /* resend START */ writel(I2C_MODE_MR | I2C_TXRX_ENA | - I2C_START_STOP, &i2c->IICSTAT); + I2C_START_STOP, &i2c->iicstat); ReadWriteByte(); result = WaitForXfer(); i = 0; while ((i < data_len) && (result == I2C_OK)) { /* disable ACK for final READ */ if (i == data_len - 1) - writel(readl(&i2c->IICCON) - & ~0x80, &i2c->IICCON); + writel(readl(&i2c->iiccon) + & ~0x80, &i2c->iiccon); ReadWriteByte(); result = WaitForXfer(); - data[i] = readl(&i2c->IICDS); + data[i] = readl(&i2c->iicds); i++; } } else { @@ -311,11 +311,11 @@ int i2c_transfer(unsigned char cmd_type, } } else { - writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT); - writel(chip, &i2c->IICDS); + writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat); + writel(chip, &i2c->iicds); /* send START */ - writel(readl(&i2c->IICSTAT) | I2C_START_STOP, - &i2c->IICSTAT); + writel(readl(&i2c->iicstat) | I2C_START_STOP, + &i2c->iicstat); result = WaitForXfer(); if (IsACK()) { @@ -323,11 +323,11 @@ int i2c_transfer(unsigned char cmd_type, while ((i < data_len) && (result == I2C_OK)) { /* disable ACK for final READ */ if (i == data_len - 1) - writel(readl(&i2c->IICCON) & - ~0x80, &i2c->IICCON); + writel(readl(&i2c->iiccon) & + ~0x80, &i2c->iiccon); ReadWriteByte(); result = WaitForXfer(); - data[i] = readl(&i2c->IICDS); + data[i] = readl(&i2c->iicds); i++; } } else { @@ -336,7 +336,7 @@ int i2c_transfer(unsigned char cmd_type, } /* send STOP */ - writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT); + writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat); ReadWriteByte(); break; diff --git a/drivers/mtd/nand/s3c2410_nand.c b/drivers/mtd/nand/s3c2410_nand.c index a27d47e..f70daef 100644 --- a/drivers/mtd/nand/s3c2410_nand.c +++ b/drivers/mtd/nand/s3c2410_nand.c @@ -69,11 +69,11 @@ static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) chip->IO_ADDR_W = (void *)IO_ADDR_W; if (ctrl & NAND_NCE) - writel(readl(&nand->NFCONF) & ~S3C2410_NFCONF_nFCE, - &nand->NFCONF); + writel(readl(&nand->nfconf) & ~S3C2410_NFCONF_nFCE, + &nand->nfconf); else - writel(readl(&nand->NFCONF) | S3C2410_NFCONF_nFCE, - &nand->NFCONF); + writel(readl(&nand->nfconf) | S3C2410_NFCONF_nFCE, + &nand->nfconf); } if (cmd != NAND_CMD_NONE) @@ -84,7 +84,7 @@ static int s3c2410_dev_ready(struct mtd_info *mtd) { struct s3c2410_nand *nand = s3c2410_get_base_nand(); debugX(1, "dev_ready\n"); - return readl(&nand->NFSTAT) & 0x01; + return readl(&nand->nfstat) & 0x01; } #ifdef CONFIG_S3C2410_NAND_HWECC @@ -92,16 +92,16 @@ void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode) { struct s3c2410_nand *nand = s3c2410_get_base_nand(); debugX(1, "s3c2410_nand_enable_hwecc(%p, %d)\n", mtd, mode); - writel(readl(&nand->NFCONF) | S3C2410_NFCONF_INITECC, &nand->NFCONF); + writel(readl(&nand->nfconf) | S3C2410_NFCONF_INITECC, &nand->nfconf); } static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) { struct s3c2410_nand *nand = s3c2410_get_base_nand(); - ecc_code[0] = readb(&nand->NFECC); - ecc_code[1] = readb(&nand->NFECC + 1); - ecc_code[2] = readb(&nand->NFECC + 2); + ecc_code[0] = readb(&nand->nfecc); + ecc_code[1] = readb(&nand->nfecc + 1); + ecc_code[2] = readb(&nand->nfecc + 2); debugX(1, "s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n", mtd , ecc_code[0], ecc_code[1], ecc_code[2]); @@ -130,7 +130,7 @@ int board_nand_init(struct nand_chip *nand) debugX(1, "board_nand_init()\n"); - writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON); + writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon); /* initialize hardware */ twrph0 = 3; @@ -141,10 +141,11 @@ int board_nand_init(struct nand_chip *nand) cfg |= S3C2410_NFCONF_TACLS(tacls - 1); cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1); cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1); - writel(cfg, &nand_reg->NFCONF); + writel(cfg, &nand_reg->nfconf); /* initialize nand_chip data structure */ - nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)&nand_reg->NFDATA; + nand->IO_ADDR_R = (void *)&nand_reg->nfdata; + nand->IO_ADDR_W = (void *)&nand_reg->nfdata; nand->select_chip = NULL; diff --git a/drivers/rtc/s3c24x0_rtc.c b/drivers/rtc/s3c24x0_rtc.c index 04de5ca..7f02f05 100644 --- a/drivers/rtc/s3c24x0_rtc.c +++ b/drivers/rtc/s3c24x0_rtc.c @@ -49,11 +49,11 @@ static inline void SetRTC_Access(RTC_ACCESS a) switch (a) { case RTC_ENABLE: - writeb(readb(&rtc->RTCCON) | 0x01, &rtc->RTCCON); + writeb(readb(&rtc->rtccon) | 0x01, &rtc->rtccon); break; case RTC_DISABLE: - writeb(readb(&rtc->RTCCON) & ~0x01, &rtc->RTCCON); + writeb(readb(&rtc->rtccon) & ~0x01, &rtc->rtccon); break; } } @@ -71,23 +71,23 @@ int rtc_get(struct rtc_time *tmp) /* read RTC registers */ do { - sec = readb(&rtc->BCDSEC); - min = readb(&rtc->BCDMIN); - hour = readb(&rtc->BCDHOUR); - mday = readb(&rtc->BCDDATE); - wday = readb(&rtc->BCDDAY); - mon = readb(&rtc->BCDMON); - year = readb(&rtc->BCDYEAR); - } while (sec != readb(&rtc->BCDSEC)); + sec = readb(&rtc->bcdsec); + min = readb(&rtc->bcdmin); + hour = readb(&rtc->bcdhour); + mday = readb(&rtc->bcddate); + wday = readb(&rtc->bcdday); + mon = readb(&rtc->bcdmon); + year = readb(&rtc->bcdyear); + } while (sec != readb(&rtc->bcdsec)); /* read ALARM registers */ - a_sec = readb(&rtc->ALMSEC); - a_min = readb(&rtc->ALMMIN); - a_hour = readb(&rtc->ALMHOUR); - a_date = readb(&rtc->ALMDATE); - a_mon = readb(&rtc->ALMMON); - a_year = readb(&rtc->ALMYEAR); - a_armed = readb(&rtc->RTCALM); + a_sec = readb(&rtc->almsec); + a_min = readb(&rtc->almmin); + a_hour = readb(&rtc->almhour); + a_date = readb(&rtc->almdate); + a_mon = readb(&rtc->almmon); + a_year = readb(&rtc->almyear); + a_armed = readb(&rtc->rtcalm); /* disable access to RTC registers */ SetRTC_Access(RTC_DISABLE); @@ -145,13 +145,13 @@ int rtc_set(struct rtc_time *tmp) SetRTC_Access(RTC_ENABLE); /* write RTC registers */ - writeb(sec, &rtc->BCDSEC); - writeb(min, &rtc->BCDMIN); - writeb(hour, &rtc->BCDHOUR); - writeb(mday, &rtc->BCDDATE); - writeb(wday, &rtc->BCDDAY); - writeb(mon, &rtc->BCDMON); - writeb(year, &rtc->BCDYEAR); + writeb(sec, &rtc->bcdsec); + writeb(min, &rtc->bcdmin); + writeb(hour, &rtc->bcdhour); + writeb(mday, &rtc->bcddate); + writeb(wday, &rtc->bcdday); + writeb(mon, &rtc->bcdmon); + writeb(year, &rtc->bcdyear); /* disable access to RTC registers */ SetRTC_Access(RTC_DISABLE); @@ -163,8 +163,8 @@ void rtc_reset(void) { struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc(); - writeb((readb(&rtc->RTCCON) & ~0x06) | 0x08, &rtc->RTCCON); - writeb(readb(&rtc->RTCCON) & ~(0x08 | 0x01), &rtc->RTCCON); + writeb((readb(&rtc->rtccon) & ~0x06) | 0x08, &rtc->rtccon); + writeb(readb(&rtc->rtccon) & ~(0x08 | 0x01), &rtc->rtccon); } #endif diff --git a/drivers/serial/serial_s3c24x0.c b/drivers/serial/serial_s3c24x0.c index 8a3e302..f42b15e 100644 --- a/drivers/serial/serial_s3c24x0.c +++ b/drivers/serial/serial_s3c24x0.c @@ -101,7 +101,7 @@ void _serial_setbrg(const int dev_index) /* value is calculated so : (int)(PCLK/16./baudrate) -1 */ reg = get_PCLK() / (16 * gd->baudrate) - 1; - writel(reg, &uart->UBRDIV); + writel(reg, &uart->ubrdiv); for (i = 0; i < 100; i++) /* Delay */ ; } @@ -131,26 +131,26 @@ static int serial_init_dev(const int dev_index) #endif /* FIFO enable, Tx/Rx FIFO clear */ - writel(0x07, &uart->UFCON); - writel(0x0, &uart->UMCON); + writel(0x07, &uart->ufcon); + writel(0x0, &uart->umcon); /* Normal,No parity,1 stop,8 bit */ - writel(0x3, &uart->ULCON); + writel(0x3, &uart->ulcon); /* * tx=level,rx=edge,disable timeout int.,enable rx error int., * normal,interrupt or polling */ - writel(0x245, &uart->UCON); + writel(0x245, &uart->ucon); #ifdef CONFIG_HWFLOW - writel(0x1, &uart->UMCON); /* RTS up */ + writel(0x1, &uart->umcon); /* rts up */ #endif /* FIXME: This is sooooooooooooooooooo ugly */ #if defined(CONFIG_ARCH_GTA02_v1) || defined(CONFIG_ARCH_GTA02_v2) /* we need auto hw flow control on the gsm and gps port */ if (dev_index == 0 || dev_index == 1) - writel(0x10, &uart->UMCON); + writel(0x10, &uart->umcon); #endif _serial_setbrg(dev_index); @@ -176,10 +176,10 @@ int _serial_getc(const int dev_index) { struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index); - while (!(readl(&uart->UTRSTAT) & 0x1)) + while (!(readl(&uart->utrstat) & 0x1)) /* wait for character to arrive */ ; - return readb(&uart->URXH) & 0xff; + return readb(&uart->urxh) & 0xff; } #if defined(CONFIG_SERIAL_MULTI) @@ -237,15 +237,15 @@ void _serial_putc(const char c, const int dev_index) return; #endif - while (!(readl(&uart->UTRSTAT) & 0x2)) + while (!(readl(&uart->utrstat) & 0x2)) /* wait for room in the tx FIFO */ ; #ifdef CONFIG_HWFLOW - while (hwflow && !(readl(&uart->UMSTAT) & 0x1)) + while (hwflow && !(readl(&uart->umstat) & 0x1)) /* Wait for CTS up */ ; #endif - writeb(c, &uart->UTXH); + writeb(c, &uart->utxh); /* If \n, also do \r */ if (c == '\n') @@ -272,7 +272,7 @@ int _serial_tstc(const int dev_index) { struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index); - return readl(&uart->UTRSTAT) & 0x1; + return readl(&uart->utrstat) & 0x1; } #if defined(CONFIG_SERIAL_MULTI) -- cgit v1.1