From cca07417d594fcae589463d1678d639810f986cd Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Fri, 17 Dec 2010 15:25:09 -0500 Subject: Blackfin: BF50x: new processor port Signed-off-by: Mike Frysinger --- drivers/mmc/bfin_sdh.c | 2 +- drivers/spi/bfin_spi.c | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mmc/bfin_sdh.c b/drivers/mmc/bfin_sdh.c index 27d9bf6..5670939 100644 --- a/drivers/mmc/bfin_sdh.c +++ b/drivers/mmc/bfin_sdh.c @@ -19,7 +19,7 @@ #include #include -#if defined(__ADSPBF51x__) +#if defined(__ADSPBF50x__) || defined(__ADSPBF51x__) # define bfin_read_SDH_PWR_CTL bfin_read_RSI_PWR_CONTROL # define bfin_write_SDH_PWR_CTL bfin_write_RSI_PWR_CONTROL # define bfin_read_SDH_CLK_CTL bfin_read_RSI_CLK_CONTROL diff --git a/drivers/spi/bfin_spi.c b/drivers/spi/bfin_spi.c index d7e1474..e8a4de5 100644 --- a/drivers/spi/bfin_spi.c +++ b/drivers/spi/bfin_spi.c @@ -248,6 +248,8 @@ void spi_release_bus(struct spi_slave *slave) #elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__) || \ defined(__ADSPBF52x__) || defined(__ADSPBF51x__) # define SPI_DMA_BASE DMA7_NEXT_DESC_PTR +# elif defined(__ADSPBF50x__) +# define SPI_DMA_BASE DMA6_NEXT_DESC_PTR #else # error "Please provide SPI DMA channel defines" #endif -- cgit v1.1 From 1fd2d792a248916de23dc7644b54694c709465f1 Mon Sep 17 00:00:00 2001 From: Cliff Cai Date: Mon, 7 Dec 2009 06:12:11 +0000 Subject: Blackfin: bfin_sdh: set all timer bits before transfer The timer register is 32bits, not 16bit, so 0xFFFF won't fill it. Write out -1 to make sure to fill the whole thing. Signed-off-by: Cliff Cai Signed-off-by: Mike Frysinger --- drivers/mmc/bfin_sdh.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mmc/bfin_sdh.c b/drivers/mmc/bfin_sdh.c index 5670939..f9da6a3 100644 --- a/drivers/mmc/bfin_sdh.c +++ b/drivers/mmc/bfin_sdh.c @@ -123,7 +123,7 @@ static int sdh_setup_data(struct mmc *mmc, struct mmc_data *data) bfin_write_SDH_DATA_CTL(data_ctl); dma_cfg = WDSIZE_32 | RESTART | WNR | DMAEN; - bfin_write_SDH_DATA_TIMER(0xFFFF); + bfin_write_SDH_DATA_TIMER(-1); blackfin_dcache_flush_invalidate_range(data->dest, data->dest + data->blocksize); -- cgit v1.1 From 21a50374d5925927128f8984b10447235e198144 Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Thu, 30 Dec 2010 08:38:00 +0000 Subject: Blackfin: bfin_sdh: add support for multiblock operations Don't forget to count full data size for the multiblock operation request. Signed-off-by: Sonic Zhang Signed-off-by: Mike Frysinger --- drivers/mmc/bfin_sdh.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/bfin_sdh.c b/drivers/mmc/bfin_sdh.c index f9da6a3..31b6459 100644 --- a/drivers/mmc/bfin_sdh.c +++ b/drivers/mmc/bfin_sdh.c @@ -114,11 +114,12 @@ static int sdh_setup_data(struct mmc *mmc, struct mmc_data *data) u16 data_ctl = 0; u16 dma_cfg = 0; int ret = 0; + unsigned long data_size = data->blocksize * data->blocks; /* Don't support write yet. */ if (data->flags & MMC_DATA_WRITE) return UNUSABLE_ERR; - data_ctl |= ((ffs(data->blocksize) - 1) << 4); + data_ctl |= ((ffs(data_size) - 1) << 4); data_ctl |= DTX_DIR; bfin_write_SDH_DATA_CTL(data_ctl); dma_cfg = WDSIZE_32 | RESTART | WNR | DMAEN; @@ -126,13 +127,13 @@ static int sdh_setup_data(struct mmc *mmc, struct mmc_data *data) bfin_write_SDH_DATA_TIMER(-1); blackfin_dcache_flush_invalidate_range(data->dest, - data->dest + data->blocksize); + data->dest + data_size); /* configure DMA */ bfin_write_DMA_START_ADDR(data->dest); - bfin_write_DMA_X_COUNT(data->blocksize / 4); + bfin_write_DMA_X_COUNT(data_size / 4); bfin_write_DMA_X_MODIFY(4); bfin_write_DMA_CONFIG(dma_cfg); - bfin_write_SDH_DATA_LGTH(data->blocksize); + bfin_write_SDH_DATA_LGTH(data_size); /* kick off transfer */ bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E); -- cgit v1.1