From 9035edbae9dd3c10751d78bf80a1b2bc225cda4f Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Mon, 20 Jul 2015 20:49:25 +0300 Subject: gpio: sh-pfc: fix gpio input read Fix gpio_read: gpio input (INDT) and gpio output (OUTDT) registers have different offset. gpio_read must be performed from INDT. Signed-off-by: Vladimir Barinov Signed-off-by: Nobuhiro Iwamatsu --- drivers/gpio/sh_pfc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpio/sh_pfc.c b/drivers/gpio/sh_pfc.c index 7a5af20..a0eac13 100644 --- a/drivers/gpio/sh_pfc.c +++ b/drivers/gpio/sh_pfc.c @@ -75,7 +75,8 @@ static int gpio_read_bit(struct pinmux_data_reg *dr, debug("read_bit: addr = %lx, pos = %ld, " "r_width = %ld\n", dr->reg, pos, dr->reg_width); - return (gpio_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1; + return + (gpio_read_raw_reg(dr->mapped_reg + 0x4, dr->reg_width) >> pos) & 1; } static void gpio_write_bit(struct pinmux_data_reg *dr, -- cgit v1.1 From 53be7bf2a536c3b0c260993e51bb0803938d21f5 Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Mon, 20 Jul 2015 20:49:39 +0300 Subject: serial: serial-sh: SCIFA interface for R-Car Gen2 SoCs Add SCIFA console interface for R-Car Gen2 SoCs. SCIFA has different registers offsets and sizes then SCI. Hence it needs to put it's macro definitions separately. Signed-off-by: Vladimir Barinov Signed-off-by: Nobuhiro Iwamatsu --- drivers/serial/serial_sh.h | 43 ++++++++++++++++++++++++++++++++++--------- 1 file changed, 34 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h index 941e6ed..cbc2929 100644 --- a/drivers/serial/serial_sh.h +++ b/drivers/serial/serial_sh.h @@ -226,7 +226,11 @@ struct uart_port { # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) -# define SCIF_ORER 0x0001 +# if defined(CONFIG_SCIF_A) +# define SCIF_ORER 0x0200 +# else +# define SCIF_ORER 0x0001 +# endif # define SCSCR_INIT(port) (port->clk_mode == EXT_CLK ? 0x32 : 0x30) /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */ #else @@ -306,7 +310,11 @@ struct uart_port { #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) -# define SCIF_RFDC_MASK 0x003f +# if defined(CONFIG_SCIF_A) +# define SCIF_RFDC_MASK 0x007f +# else +# define SCIF_RFDC_MASK 0x001f +# endif #else # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) # define SCIF_RFDC_MASK 0x001f @@ -557,6 +565,25 @@ SCIF_FNS(SCFCR, 0x18, 16) SCIF_FNS(SCFDR, 0x1c, 16) SCIF_FNS(SCLSR, 0x24, 16) SCIF_FNS(DL, 0x00, 0) /* dummy */ +#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ + defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) +/* SCIFA and SCIF register offsets and size */ +SCIx_FNS(SCSMR, 0, 0, 0x00, 16, 0, 0, 0x00, 16, 0, 0) +SCIx_FNS(SCBRR, 0, 0, 0x04, 8, 0, 0, 0x04, 8, 0, 0) +SCIx_FNS(SCSCR, 0, 0, 0x08, 16, 0, 0, 0x08, 16, 0, 0) +SCIx_FNS(SCxTDR, 0, 0, 0x20, 8, 0, 0, 0x0C, 8, 0, 0) +SCIx_FNS(SCxSR, 0, 0, 0x14, 16, 0, 0, 0x10, 16, 0, 0) +SCIx_FNS(SCxRDR, 0, 0, 0x24, 8, 0, 0, 0x14, 8, 0, 0) +SCIF_FNS(SCFCR, 0, 0, 0x18, 16) +SCIF_FNS(SCFDR, 0, 0, 0x1C, 16) +SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) +SCIF_FNS(DL, 0, 0, 0x30, 16) +SCIF_FNS(CKS, 0, 0, 0x34, 16) +#if defined(CONFIG_SCIF_A) +SCIF_FNS(SCLSR, 0, 0, 0x14, 16) +#else +SCIF_FNS(SCLSR, 0, 0, 0x24, 16) +#endif #else /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/ /* name off sz off sz off sz off sz off sz*/ @@ -594,14 +621,8 @@ SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) #endif SCIF_FNS(SCLSR, 0, 0, 0x24, 16) #endif -#if defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ - defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) -SCIF_FNS(DL, 0, 0, 0x30, 16) -SCIF_FNS(CKS, 0, 0, 0x34, 16) -#else SCIF_FNS(DL, 0, 0, 0x0, 0) /* dummy */ #endif -#endif #define sci_in(port, reg) sci_##reg##_in(port) #define sci_out(port, reg, value) sci_##reg##_out(port, value) @@ -743,7 +764,11 @@ static inline int scbrr_calc(struct uart_port *port, int bps, int clk) #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) #define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */ -#define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */ + #if defined(CONFIG_SCIF_A) + #define SCBRR_VALUE(bps, clk) (clk / bps / 16 - 1) /* Internal Clock */ + #else + #define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */ + #endif #else /* Generic SH */ #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) #endif -- cgit v1.1