From ac135f66992f65959fcf8245f2ea8a9109a4a913 Mon Sep 17 00:00:00 2001 From: Michael Heimpold Date: Sun, 3 Nov 2013 22:59:26 +0100 Subject: mxs_gpio: fix the handling in gpio_direction_output() Setting the direction and an output value should be done by 1) set the desired output value, 2) switch to output. If this is done in the inverse order, there can be a glitch on the GPIO line. This patch fixes this by using the order as described above. Signed-off-by: Michael Heimpold Acked-by: Stefano Babic --- drivers/gpio/mxs_gpio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpio/mxs_gpio.c b/drivers/gpio/mxs_gpio.c index d9a7a3a..da0199b 100644 --- a/drivers/gpio/mxs_gpio.c +++ b/drivers/gpio/mxs_gpio.c @@ -95,10 +95,10 @@ int gpio_direction_output(unsigned gpio, int value) struct mxs_register_32 *reg = (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset); - writel(1 << PAD_PIN(gpio), ®->reg_set); - gpio_set_value(gpio, value); + writel(1 << PAD_PIN(gpio), ®->reg_set); + return 0; } -- cgit v1.1 From 79e5f27b09023410916e71c281259aa097982514 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 12 Oct 2013 20:36:25 +0200 Subject: Net: FEC: Fix huge memory leak The fec_halt() never free'd both RX and TX DMA descriptors that were allocated in fec_init(), nor did it free the RX buffers. Rework the FEC driver so that these descriptors and buffers are allocated only once in fec_probe(). Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Stefano Babic --- drivers/net/fec_mxc.c | 177 ++++++++++++++++++++++++++++---------------------- 1 file changed, 99 insertions(+), 78 deletions(-) (limited to 'drivers') diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 107cd6e..3b2b995 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -270,49 +270,34 @@ static int fec_tx_task_disable(struct fec_priv *fec) * @param[in] dsize desired size of each receive buffer * @return 0 on success * - * For this task we need additional memory for the data buffers. And each - * data buffer requires some alignment. Thy must be aligned to a specific - * boundary each. + * Init all RX descriptors to default values. */ -static int fec_rbd_init(struct fec_priv *fec, int count, int dsize) +static void fec_rbd_init(struct fec_priv *fec, int count, int dsize) { uint32_t size; + uint8_t *data; int i; /* - * Allocate memory for the buffers. This allocation respects the - * alignment + * Reload the RX descriptors with default values and wipe + * the RX buffers. */ size = roundup(dsize, ARCH_DMA_MINALIGN); for (i = 0; i < count; i++) { - uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer); - if (data_ptr == 0) { - uint8_t *data = memalign(ARCH_DMA_MINALIGN, - size); - if (!data) { - printf("%s: error allocating rxbuf %d\n", - __func__, i); - goto err; - } - writel((uint32_t)data, &fec->rbd_base[i].data_pointer); - } /* needs allocation */ - writew(FEC_RBD_EMPTY, &fec->rbd_base[i].status); - writew(0, &fec->rbd_base[i].data_length); + data = (uint8_t *)fec->rbd_base[i].data_pointer; + memset(data, 0, dsize); + flush_dcache_range((uint32_t)data, (uint32_t)data + size); + + fec->rbd_base[i].status = FEC_RBD_EMPTY; + fec->rbd_base[i].data_length = 0; } /* Mark the last RBD to close the ring. */ - writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[i - 1].status); + fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY; fec->rbd_index = 0; - return 0; - -err: - for (; i >= 0; i--) { - uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer); - free((void *)data_ptr); - } - - return -ENOMEM; + flush_dcache_range((unsigned)fec->rbd_base, + (unsigned)fec->rbd_base + size); } /** @@ -332,10 +317,12 @@ static void fec_tbd_init(struct fec_priv *fec) unsigned addr = (unsigned)fec->tbd_base; unsigned size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); - writew(0x0000, &fec->tbd_base[0].status); - writew(FEC_TBD_WRAP, &fec->tbd_base[1].status); + + memset(fec->tbd_base, 0, size); + fec->tbd_base[0].status = 0; + fec->tbd_base[1].status = FEC_TBD_WRAP; fec->tbd_index = 0; - flush_dcache_range(addr, addr+size); + flush_dcache_range(addr, addr + size); } /** @@ -527,51 +514,18 @@ static int fec_init(struct eth_device *dev, bd_t* bd) { struct fec_priv *fec = (struct fec_priv *)dev->priv; uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop; - uint32_t size; - int i, ret; + int i; /* Initialize MAC address */ fec_set_hwaddr(dev); /* - * Allocate transmit descriptors, there are two in total. This - * allocation respects cache alignment. + * Setup transmit descriptors, there are two in total. */ - if (!fec->tbd_base) { - size = roundup(2 * sizeof(struct fec_bd), - ARCH_DMA_MINALIGN); - fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size); - if (!fec->tbd_base) { - ret = -ENOMEM; - goto err1; - } - memset(fec->tbd_base, 0, size); - fec_tbd_init(fec); - } + fec_tbd_init(fec); - /* - * Allocate receive descriptors. This allocation respects cache - * alignment. - */ - if (!fec->rbd_base) { - size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), - ARCH_DMA_MINALIGN); - fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size); - if (!fec->rbd_base) { - ret = -ENOMEM; - goto err2; - } - memset(fec->rbd_base, 0, size); - /* - * Initialize RxBD ring - */ - if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) { - ret = -ENOMEM; - goto err3; - } - flush_dcache_range((unsigned)fec->rbd_base, - (unsigned)fec->rbd_base + size); - } + /* Setup receive descriptors. */ + fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE); fec_reg_setup(fec); @@ -608,13 +562,6 @@ static int fec_init(struct eth_device *dev, bd_t* bd) #endif fec_open(dev); return 0; - -err3: - free(fec->rbd_base); -err2: - free(fec->tbd_base); -err1: - return ret; } /** @@ -907,6 +854,74 @@ static void fec_set_dev_name(char *dest, int dev_id) sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id); } +static int fec_alloc_descs(struct fec_priv *fec) +{ + unsigned int size; + int i; + uint8_t *data; + + /* Allocate TX descriptors. */ + size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); + fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size); + if (!fec->tbd_base) + goto err_tx; + + /* Allocate RX descriptors. */ + size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); + fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size); + if (!fec->rbd_base) + goto err_rx; + + memset(fec->rbd_base, 0, size); + + /* Allocate RX buffers. */ + + /* Maximum RX buffer size. */ + size = roundup(FEC_MAX_PKT_SIZE, ARCH_DMA_MINALIGN); + for (i = 0; i < FEC_RBD_NUM; i++) { + data = memalign(ARCH_DMA_MINALIGN, size); + if (!data) { + printf("%s: error allocating rxbuf %d\n", __func__, i); + goto err_ring; + } + + memset(data, 0, size); + + fec->rbd_base[i].data_pointer = (uint32_t)data; + fec->rbd_base[i].status = FEC_RBD_EMPTY; + fec->rbd_base[i].data_length = 0; + /* Flush the buffer to memory. */ + flush_dcache_range((uint32_t)data, (uint32_t)data + size); + } + + /* Mark the last RBD to close the ring. */ + fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY; + + fec->rbd_index = 0; + fec->tbd_index = 0; + + return 0; + +err_ring: + for (; i >= 0; i--) + free((void *)fec->rbd_base[i].data_pointer); + free(fec->rbd_base); +err_rx: + free(fec->tbd_base); +err_tx: + return -ENOMEM; +} + +static void fec_free_descs(struct fec_priv *fec) +{ + int i; + + for (i = 0; i < FEC_RBD_NUM; i++) + free((void *)fec->rbd_base[i].data_pointer); + free(fec->rbd_base); + free(fec->tbd_base); +} + #ifdef CONFIG_PHYLIB int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, struct mii_dev *bus, struct phy_device *phydev) @@ -939,6 +954,10 @@ static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, memset(edev, 0, sizeof(*edev)); memset(fec, 0, sizeof(*fec)); + ret = fec_alloc_descs(fec); + if (ret) + goto err3; + edev->priv = fec; edev->init = fec_init; edev->send = fec_send; @@ -957,7 +976,7 @@ static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) { if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { printf("FEC MXC: Timeout reseting chip\n"); - goto err3; + goto err4; } udelay(10); } @@ -984,6 +1003,8 @@ static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, eth_setenv_enetaddr("ethaddr", ethaddr); } return ret; +err4: + fec_free_descs(fec); err3: free(fec); err2: -- cgit v1.1 From 839f4d4e87f40e68de5d57ccff502fe97513d1fa Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 20 Nov 2013 20:26:06 -0200 Subject: power: power_fsl: Pass p->bus in the same way for SPI and I2C cases There is no need to pass p->bus differently when the PMIC is connected via SPI or via I2C. Handle the both cases in the same way. Signed-off-by: Fabio Estevam --- drivers/power/power_fsl.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/power/power_fsl.c b/drivers/power/power_fsl.c index ed778f3..ac0b541 100644 --- a/drivers/power/power_fsl.c +++ b/drivers/power/power_fsl.c @@ -36,10 +36,10 @@ int pmic_init(unsigned char bus) p->name = name; p->number_of_regs = PMIC_NUM_OF_REGS; + p->bus = bus; #if defined(CONFIG_POWER_SPI) p->interface = PMIC_SPI; - p->bus = CONFIG_FSL_PMIC_BUS; p->hw.spi.cs = CONFIG_FSL_PMIC_CS; p->hw.spi.clk = CONFIG_FSL_PMIC_CLK; p->hw.spi.mode = CONFIG_FSL_PMIC_MODE; @@ -50,7 +50,6 @@ int pmic_init(unsigned char bus) p->interface = PMIC_I2C; p->hw.i2c.addr = CONFIG_SYS_FSL_PMIC_I2C_ADDR; p->hw.i2c.tx_num = FSL_PMIC_I2C_LENGTH; - p->bus = bus; #else #error "You must select CONFIG_POWER_SPI or CONFIG_PMIC_I2C" #endif -- cgit v1.1 From ac2ff538cde458a100da71974bdca8c2142e9e19 Mon Sep 17 00:00:00 2001 From: Alban Bedel Date: Wed, 13 Nov 2013 17:27:19 +0100 Subject: i2c: tegra: Add the fifth bus on SoC with more than 4 buses Create the i2c adapter object for the fifth bus on SoC with more than 4 buses. This allow using all the bus available on T30. Signed-off-by: Alban Bedel Acked-by: Heiko Schocher Signed-off-by: Tom Warren --- drivers/i2c/tegra_i2c.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'drivers') diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c index 9847cf1..594e5dd 100644 --- a/drivers/i2c/tegra_i2c.c +++ b/drivers/i2c/tegra_i2c.c @@ -629,3 +629,8 @@ U_BOOT_I2C_ADAP_COMPLETE(tegra2, tegra_i2c_init, tegra_i2c_probe, U_BOOT_I2C_ADAP_COMPLETE(tegra3, tegra_i2c_init, tegra_i2c_probe, tegra_i2c_read, tegra_i2c_write, tegra_i2c_set_bus_speed, 100000, 0, 3) +#if TEGRA_I2C_NUM_CONTROLLERS > 4 +U_BOOT_I2C_ADAP_COMPLETE(tegra4, tegra_i2c_init, tegra_i2c_probe, + tegra_i2c_read, tegra_i2c_write, + tegra_i2c_set_bus_speed, 100000, 0, 4) +#endif -- cgit v1.1 From 4611d5bab26f93471b84f6f33967cef69b3f723a Mon Sep 17 00:00:00 2001 From: Sergey Alyoshin Date: Tue, 17 Dec 2013 23:24:54 +0400 Subject: arm: mx5: Add fuse supply enable in fsl_iim MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable fuse supply before fuse programming and disable after. Signed-off-by: Sergey Alyoshin Reviewed-by: Benoît Thébaudeau --- drivers/misc/fsl_iim.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/misc/fsl_iim.c b/drivers/misc/fsl_iim.c index 44ae7b1..36433a7 100644 --- a/drivers/misc/fsl_iim.c +++ b/drivers/misc/fsl_iim.c @@ -16,6 +16,9 @@ #ifndef CONFIG_MPC512X #include #endif +#if defined(CONFIG_MX51) || defined(CONFIG_MX53) +#include +#endif /* FSL IIM-specific constants */ #define STAT_BUSY 0x80 @@ -93,6 +96,10 @@ struct fsl_iim { } bank[8]; }; +#if !defined(CONFIG_MX51) && !defined(CONFIG_MX53) +#define enable_efuse_prog_supply(enable) +#endif + static int prepare_access(struct fsl_iim **regs, u32 bank, u32 word, int assert, const char *caller) { @@ -237,12 +244,16 @@ int fuse_prog(u32 bank, u32 word, u32 val) if (ret) return ret; + enable_efuse_prog_supply(1); for (bit = 0; val; bit++, val >>= 1) if (val & 0x01) { ret = prog_bit(regs, bank, word, bit); - if (ret) + if (ret) { + enable_efuse_prog_supply(0); return ret; + } } + enable_efuse_prog_supply(0); return 0; } -- cgit v1.1 From 456ccfdf0d5eefc153b143bd13731a59e2d71585 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 20 Dec 2013 11:19:33 -0500 Subject: TI:omap3: Drop omap3_zoom2 The omap3_zoom2 board has not been updated for a correct CONFIG_SYS_HZ and Tom Rix's email has long been bouncing. Signed-off-by: Tom Rini --- drivers/serial/ns16550.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 181c818..fbc37b2 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -56,9 +56,8 @@ void NS16550_init(NS16550_t com_port, int baud_divisor) ; serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier); -#if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \ - defined(CONFIG_AM33XX) || defined(CONFIG_TI81XX) || \ - defined(CONFIG_AM43XX) +#if defined(CONFIG_OMAP) || defined(CONFIG_AM33XX) || \ + defined(CONFIG_TI81XX) || defined(CONFIG_AM43XX) serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/ #endif serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr); -- cgit v1.1