From 26f50fbed2f19edf0c4a2eb80e7fa12941764660 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 5 Oct 2016 20:42:09 -0600 Subject: Revert "x86: broadwell: gpio: Remove the codes to set up pin control" This makes the assumption that setting up pinctrl in cpu_init_r() is safe. On samus we need GPIOs before relocation in order to support power control. This commit fixes the following message on boot: initcall sequence ffe5c6f4 failed at call ffe01d3d (err=-1) ### ERROR ### Please RESET the board ### In any case it seems better to leave init to driver model, so that it can pick up the GPIO driver when it needs it. Since pinctrl is a dependency of the GPIO driver, we may as well put the dependency there and avoid these problems. This reverts commit 9769e05bcf79939bad23a719982dd1f85a110f3c. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- drivers/gpio/intel_broadwell_gpio.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers') diff --git a/drivers/gpio/intel_broadwell_gpio.c b/drivers/gpio/intel_broadwell_gpio.c index 8b50900..81ce446 100644 --- a/drivers/gpio/intel_broadwell_gpio.c +++ b/drivers/gpio/intel_broadwell_gpio.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -118,6 +119,12 @@ static int broadwell_gpio_probe(struct udevice *dev) struct broadwell_bank_platdata *plat = dev_get_platdata(dev); struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); struct broadwell_bank_priv *priv = dev_get_priv(dev); + struct udevice *pinctrl; + int ret; + + /* Set up pin control if available */ + ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &pinctrl); + debug("%s, pinctrl=%p, ret=%d\n", __func__, pinctrl, ret); uc_priv->gpio_count = GPIO_PER_BANK; uc_priv->bank_name = plat->bank_name; -- cgit v1.1 From 0a5f6f869f1c2c6e9f75d83203754937014cbe47 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 5 Oct 2016 20:42:13 -0600 Subject: dm: core: Add a function to get a uclass name It is useful in debug() statements to display the name of the uclass for a device. Add a simple function to provide this. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- drivers/core/uclass.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'drivers') diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c index de602ae..60610e5 100644 --- a/drivers/core/uclass.c +++ b/drivers/core/uclass.c @@ -148,6 +148,15 @@ int uclass_get(enum uclass_id id, struct uclass **ucp) return 0; } +const char *uclass_get_name(enum uclass_id id) +{ + struct uclass *uc; + + if (uclass_get(id, &uc)) + return NULL; + return uc->uc_drv->name; +} + int uclass_find_device(enum uclass_id id, int index, struct udevice **devp) { struct uclass *uc; -- cgit v1.1 From 1df912762815df8a1254e4629dfb62e1845c15dd Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 5 Oct 2016 20:42:14 -0600 Subject: x86: video: Fix typo in broadwell Kconfig 'enabled' should be 'enables'. Fix it. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- drivers/video/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 8361a71..97dbb64 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -366,7 +366,7 @@ config VIDEO_BROADWELL_IGD bool "Enable Intel Broadwell integrated graphics device" depends on X86 help - This enabled support for integrated graphics on Intel broadwell + This enables support for integrated graphics on Intel broadwell devices. Initialisation is mostly performed by a VGA boot ROM, with some setup handled by U-Boot itself. The graphics adaptor works as a VESA device and supports LCD panels, eDP and LVDS outputs. -- cgit v1.1 From ee87ee82e1c9052d59e44c5c29448f4545ab59e7 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 5 Oct 2016 20:42:17 -0600 Subject: dm: video: Add driver-model support to vesa graphics Provide a function to run the Vesa BIOS for a given PCI device and obtain the resulting configuration (e.g. display size) for use by the video uclass. This makes it easier to write a video driver that uses vesa and supports driver model. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- drivers/pci/pci_rom.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) (limited to 'drivers') diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index 399055b..21ed17c 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include @@ -348,3 +349,57 @@ err: free(ram); return ret; } + +#ifdef CONFIG_DM_VIDEO +static int vbe_setup_video_priv(struct vesa_mode_info *vesa, + struct video_priv *uc_priv, + struct video_uc_platdata *plat) +{ + if (!vesa->x_resolution) + return -ENXIO; + uc_priv->xsize = vesa->x_resolution; + uc_priv->ysize = vesa->y_resolution; + switch (vesa->bits_per_pixel) { + case 32: + case 24: + uc_priv->bpix = VIDEO_BPP32; + break; + case 16: + uc_priv->bpix = VIDEO_BPP16; + break; + default: + return -EPROTONOSUPPORT; + } + plat->base = vesa->phys_base_ptr; + plat->size = vesa->bytes_per_scanline * vesa->y_resolution; + + return 0; +} + +int vbe_setup_video(struct udevice *dev, int (*int15_handler)(void)) +{ + struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); + struct video_priv *uc_priv = dev_get_uclass_priv(dev); + int ret; + + /* If we are running from EFI or coreboot, this can't work */ + if (!ll_boot_init()) + return -EPERM; + bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display"); + ret = dm_pci_run_vga_bios(dev, int15_handler, PCI_ROM_USE_NATIVE | + PCI_ROM_ALLOW_FALLBACK); + bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD); + if (ret) { + debug("failed to run video BIOS: %d\n", ret); + return ret; + } + + ret = vbe_setup_video_priv(&mode_info.vesa, uc_priv, plat); + if (ret) { + debug("No video mode configured\n"); + return ret; + } + + return 0; +} +#endif -- cgit v1.1 From 2c943804afdff8817387aa828ef9218efcf1d590 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 5 Oct 2016 20:42:15 -0600 Subject: dm: x86: video: Add a driver-model driver for ivybridge graphics At present we use the legacy vesa driver for graphics. Add a driver which supports driver model. This can be probed only when needed, removing the need to start up the display if it is not used. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- drivers/video/Kconfig | 12 + drivers/video/Makefile | 1 + drivers/video/ivybridge_igd.c | 843 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 856 insertions(+) create mode 100644 drivers/video/ivybridge_igd.c (limited to 'drivers') diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 97dbb64..fd26690 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -374,6 +374,18 @@ config VIDEO_BROADWELL_IGD a special tool which configures the VGA ROM, but the graphics resolution can be selected in U-Boot. +config VIDEO_IVYBRIDGE_IGD + bool "Enable Intel Ivybridge integration graphics support" + depends on X86 + help + This enables support for integrated graphics on Intel ivybridge + devices. Initialisation is mostly performed by a VGA boot ROM, with + some setup handled by U-Boot itself. The graphics adaptor works as + a VESA device and supports LCD panels, eDP and LVDS outputs. + Configuration of most aspects of device operation is performed using + a special tool which configures the VGA ROM, but the graphics + resolution can be selected in U-Boot. + config VIDEO_ROCKCHIP bool "Enable Rockchip video support" depends on DM_VIDEO diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 3f045fe..b888e99 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_CONSOLE_TRUETYPE) += console_truetype.o fonts/ endif obj-$(CONFIG_VIDEO_BROADWELL_IGD) += broadwell_igd.o +obj-$(CONFIG_VIDEO_IVYBRIDGE_IGD) += ivybridge_igd.o obj-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o diff --git a/drivers/video/ivybridge_igd.c b/drivers/video/ivybridge_igd.c new file mode 100644 index 0000000..94db3dd --- /dev/null +++ b/drivers/video/ivybridge_igd.c @@ -0,0 +1,843 @@ +/* + * Copyright (C) 2016 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct gt_powermeter { + u16 reg; + u32 value; +}; + +/* These are magic values - unfortunately the meaning is unknown */ +static const struct gt_powermeter snb_pm_gt1[] = { + { 0xa200, 0xcc000000 }, + { 0xa204, 0x07000040 }, + { 0xa208, 0x0000fe00 }, + { 0xa20c, 0x00000000 }, + { 0xa210, 0x17000000 }, + { 0xa214, 0x00000021 }, + { 0xa218, 0x0817fe19 }, + { 0xa21c, 0x00000000 }, + { 0xa220, 0x00000000 }, + { 0xa224, 0xcc000000 }, + { 0xa228, 0x07000040 }, + { 0xa22c, 0x0000fe00 }, + { 0xa230, 0x00000000 }, + { 0xa234, 0x17000000 }, + { 0xa238, 0x00000021 }, + { 0xa23c, 0x0817fe19 }, + { 0xa240, 0x00000000 }, + { 0xa244, 0x00000000 }, + { 0xa248, 0x8000421e }, + { 0 } +}; + +static const struct gt_powermeter snb_pm_gt2[] = { + { 0xa200, 0x330000a6 }, + { 0xa204, 0x402d0031 }, + { 0xa208, 0x00165f83 }, + { 0xa20c, 0xf1000000 }, + { 0xa210, 0x00000000 }, + { 0xa214, 0x00160016 }, + { 0xa218, 0x002a002b }, + { 0xa21c, 0x00000000 }, + { 0xa220, 0x00000000 }, + { 0xa224, 0x330000a6 }, + { 0xa228, 0x402d0031 }, + { 0xa22c, 0x00165f83 }, + { 0xa230, 0xf1000000 }, + { 0xa234, 0x00000000 }, + { 0xa238, 0x00160016 }, + { 0xa23c, 0x002a002b }, + { 0xa240, 0x00000000 }, + { 0xa244, 0x00000000 }, + { 0xa248, 0x8000421e }, + { 0 } +}; + +static const struct gt_powermeter ivb_pm_gt1[] = { + { 0xa800, 0x00000000 }, + { 0xa804, 0x00021c00 }, + { 0xa808, 0x00000403 }, + { 0xa80c, 0x02001700 }, + { 0xa810, 0x05000200 }, + { 0xa814, 0x00000000 }, + { 0xa818, 0x00690500 }, + { 0xa81c, 0x0000007f }, + { 0xa820, 0x01002501 }, + { 0xa824, 0x00000300 }, + { 0xa828, 0x01000331 }, + { 0xa82c, 0x0000000c }, + { 0xa830, 0x00010016 }, + { 0xa834, 0x01100101 }, + { 0xa838, 0x00010103 }, + { 0xa83c, 0x00041300 }, + { 0xa840, 0x00000b30 }, + { 0xa844, 0x00000000 }, + { 0xa848, 0x7f000000 }, + { 0xa84c, 0x05000008 }, + { 0xa850, 0x00000001 }, + { 0xa854, 0x00000004 }, + { 0xa858, 0x00000007 }, + { 0xa85c, 0x00000000 }, + { 0xa860, 0x00010000 }, + { 0xa248, 0x0000221e }, + { 0xa900, 0x00000000 }, + { 0xa904, 0x00001c00 }, + { 0xa908, 0x00000000 }, + { 0xa90c, 0x06000000 }, + { 0xa910, 0x09000200 }, + { 0xa914, 0x00000000 }, + { 0xa918, 0x00590000 }, + { 0xa91c, 0x00000000 }, + { 0xa920, 0x04002501 }, + { 0xa924, 0x00000100 }, + { 0xa928, 0x03000410 }, + { 0xa92c, 0x00000000 }, + { 0xa930, 0x00020000 }, + { 0xa934, 0x02070106 }, + { 0xa938, 0x00010100 }, + { 0xa93c, 0x00401c00 }, + { 0xa940, 0x00000000 }, + { 0xa944, 0x00000000 }, + { 0xa948, 0x10000e00 }, + { 0xa94c, 0x02000004 }, + { 0xa950, 0x00000001 }, + { 0xa954, 0x00000004 }, + { 0xa960, 0x00060000 }, + { 0xaa3c, 0x00001c00 }, + { 0xaa54, 0x00000004 }, + { 0xaa60, 0x00060000 }, + { 0 } +}; + +static const struct gt_powermeter ivb_pm_gt2[] = { + { 0xa800, 0x10000000 }, + { 0xa804, 0x00033800 }, + { 0xa808, 0x00000902 }, + { 0xa80c, 0x0c002f00 }, + { 0xa810, 0x12000400 }, + { 0xa814, 0x00000000 }, + { 0xa818, 0x00d20800 }, + { 0xa81c, 0x00000002 }, + { 0xa820, 0x03004b02 }, + { 0xa824, 0x00000600 }, + { 0xa828, 0x07000773 }, + { 0xa82c, 0x00000000 }, + { 0xa830, 0x00010032 }, + { 0xa834, 0x1520040d }, + { 0xa838, 0x00020105 }, + { 0xa83c, 0x00083700 }, + { 0xa840, 0x0000151d }, + { 0xa844, 0x00000000 }, + { 0xa848, 0x20001b00 }, + { 0xa84c, 0x0a000010 }, + { 0xa850, 0x00000000 }, + { 0xa854, 0x00000008 }, + { 0xa858, 0x00000008 }, + { 0xa85c, 0x00000000 }, + { 0xa860, 0x00020000 }, + { 0xa248, 0x0000221e }, + { 0xa900, 0x00000000 }, + { 0xa904, 0x00003500 }, + { 0xa908, 0x00000000 }, + { 0xa90c, 0x0c000000 }, + { 0xa910, 0x12000500 }, + { 0xa914, 0x00000000 }, + { 0xa918, 0x00b20000 }, + { 0xa91c, 0x00000000 }, + { 0xa920, 0x08004b02 }, + { 0xa924, 0x00000200 }, + { 0xa928, 0x07000820 }, + { 0xa92c, 0x00000000 }, + { 0xa930, 0x00030000 }, + { 0xa934, 0x050f020d }, + { 0xa938, 0x00020300 }, + { 0xa93c, 0x00903900 }, + { 0xa940, 0x00000000 }, + { 0xa944, 0x00000000 }, + { 0xa948, 0x20001b00 }, + { 0xa94c, 0x0a000010 }, + { 0xa950, 0x00000000 }, + { 0xa954, 0x00000008 }, + { 0xa960, 0x00110000 }, + { 0xaa3c, 0x00003900 }, + { 0xaa54, 0x00000008 }, + { 0xaa60, 0x00110000 }, + { 0 } +}; + +static const struct gt_powermeter ivb_pm_gt2_17w[] = { + { 0xa800, 0x20000000 }, + { 0xa804, 0x000e3800 }, + { 0xa808, 0x00000806 }, + { 0xa80c, 0x0c002f00 }, + { 0xa810, 0x0c000800 }, + { 0xa814, 0x00000000 }, + { 0xa818, 0x00d20d00 }, + { 0xa81c, 0x000000ff }, + { 0xa820, 0x03004b02 }, + { 0xa824, 0x00000600 }, + { 0xa828, 0x07000773 }, + { 0xa82c, 0x00000000 }, + { 0xa830, 0x00020032 }, + { 0xa834, 0x1520040d }, + { 0xa838, 0x00020105 }, + { 0xa83c, 0x00083700 }, + { 0xa840, 0x000016ff }, + { 0xa844, 0x00000000 }, + { 0xa848, 0xff000000 }, + { 0xa84c, 0x0a000010 }, + { 0xa850, 0x00000002 }, + { 0xa854, 0x00000008 }, + { 0xa858, 0x0000000f }, + { 0xa85c, 0x00000000 }, + { 0xa860, 0x00020000 }, + { 0xa248, 0x0000221e }, + { 0xa900, 0x00000000 }, + { 0xa904, 0x00003800 }, + { 0xa908, 0x00000000 }, + { 0xa90c, 0x0c000000 }, + { 0xa910, 0x12000800 }, + { 0xa914, 0x00000000 }, + { 0xa918, 0x00b20000 }, + { 0xa91c, 0x00000000 }, + { 0xa920, 0x08004b02 }, + { 0xa924, 0x00000300 }, + { 0xa928, 0x01000820 }, + { 0xa92c, 0x00000000 }, + { 0xa930, 0x00030000 }, + { 0xa934, 0x15150406 }, + { 0xa938, 0x00020300 }, + { 0xa93c, 0x00903900 }, + { 0xa940, 0x00000000 }, + { 0xa944, 0x00000000 }, + { 0xa948, 0x20001b00 }, + { 0xa94c, 0x0a000010 }, + { 0xa950, 0x00000000 }, + { 0xa954, 0x00000008 }, + { 0xa960, 0x00110000 }, + { 0xaa3c, 0x00003900 }, + { 0xaa54, 0x00000008 }, + { 0xaa60, 0x00110000 }, + { 0 } +}; + +static const struct gt_powermeter ivb_pm_gt2_35w[] = { + { 0xa800, 0x00000000 }, + { 0xa804, 0x00030400 }, + { 0xa808, 0x00000806 }, + { 0xa80c, 0x0c002f00 }, + { 0xa810, 0x0c000300 }, + { 0xa814, 0x00000000 }, + { 0xa818, 0x00d20d00 }, + { 0xa81c, 0x000000ff }, + { 0xa820, 0x03004b02 }, + { 0xa824, 0x00000600 }, + { 0xa828, 0x07000773 }, + { 0xa82c, 0x00000000 }, + { 0xa830, 0x00020032 }, + { 0xa834, 0x1520040d }, + { 0xa838, 0x00020105 }, + { 0xa83c, 0x00083700 }, + { 0xa840, 0x000016ff }, + { 0xa844, 0x00000000 }, + { 0xa848, 0xff000000 }, + { 0xa84c, 0x0a000010 }, + { 0xa850, 0x00000001 }, + { 0xa854, 0x00000008 }, + { 0xa858, 0x00000008 }, + { 0xa85c, 0x00000000 }, + { 0xa860, 0x00020000 }, + { 0xa248, 0x0000221e }, + { 0xa900, 0x00000000 }, + { 0xa904, 0x00003800 }, + { 0xa908, 0x00000000 }, + { 0xa90c, 0x0c000000 }, + { 0xa910, 0x12000800 }, + { 0xa914, 0x00000000 }, + { 0xa918, 0x00b20000 }, + { 0xa91c, 0x00000000 }, + { 0xa920, 0x08004b02 }, + { 0xa924, 0x00000300 }, + { 0xa928, 0x01000820 }, + { 0xa92c, 0x00000000 }, + { 0xa930, 0x00030000 }, + { 0xa934, 0x15150406 }, + { 0xa938, 0x00020300 }, + { 0xa93c, 0x00903900 }, + { 0xa940, 0x00000000 }, + { 0xa944, 0x00000000 }, + { 0xa948, 0x20001b00 }, + { 0xa94c, 0x0a000010 }, + { 0xa950, 0x00000000 }, + { 0xa954, 0x00000008 }, + { 0xa960, 0x00110000 }, + { 0xaa3c, 0x00003900 }, + { 0xaa54, 0x00000008 }, + { 0xaa60, 0x00110000 }, + { 0 } +}; + +static inline u32 gtt_read(void *bar, u32 reg) +{ + return readl(bar + reg); +} + +static inline void gtt_write(void *bar, u32 reg, u32 data) +{ + writel(data, bar + reg); +} + +static void gtt_write_powermeter(void *bar, const struct gt_powermeter *pm) +{ + for (; pm && pm->reg; pm++) + gtt_write(bar, pm->reg, pm->value); +} + +#define GTT_RETRY 1000 +static int gtt_poll(void *bar, u32 reg, u32 mask, u32 value) +{ + unsigned try = GTT_RETRY; + u32 data; + + while (try--) { + data = gtt_read(bar, reg); + if ((data & mask) == value) + return 1; + udelay(10); + } + + printf("GT init timeout\n"); + return 0; +} + +static int gma_pm_init_pre_vbios(void *gtt_bar, int rev) +{ + u32 reg32; + + debug("GT Power Management Init, silicon = %#x\n", rev); + + if (rev < IVB_STEP_C0) { + /* 1: Enable force wake */ + gtt_write(gtt_bar, 0xa18c, 0x00000001); + gtt_poll(gtt_bar, 0x130090, (1 << 0), (1 << 0)); + } else { + gtt_write(gtt_bar, 0xa180, 1 << 5); + gtt_write(gtt_bar, 0xa188, 0xffff0001); + gtt_poll(gtt_bar, 0x130040, (1 << 0), (1 << 0)); + } + + if ((rev & BASE_REV_MASK) == BASE_REV_SNB) { + /* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */ + reg32 = gtt_read(gtt_bar, 0x42004); + reg32 |= (1 << 14) | (1 << 15); + gtt_write(gtt_bar, 0x42004, reg32); + } + + if (rev >= IVB_STEP_A0) { + /* Display Reset Acknowledge Settings */ + reg32 = gtt_read(gtt_bar, 0x45010); + reg32 |= (1 << 1) | (1 << 0); + gtt_write(gtt_bar, 0x45010, reg32); + } + + /* 2: Get GT SKU from GTT+0x911c[13] */ + reg32 = gtt_read(gtt_bar, 0x911c); + if ((rev & BASE_REV_MASK) == BASE_REV_SNB) { + if (reg32 & (1 << 13)) { + debug("SNB GT1 Power Meter Weights\n"); + gtt_write_powermeter(gtt_bar, snb_pm_gt1); + } else { + debug("SNB GT2 Power Meter Weights\n"); + gtt_write_powermeter(gtt_bar, snb_pm_gt2); + } + } else { + u32 unit = readl(MCHBAR_REG(0x5938)) & 0xf; + + if (reg32 & (1 << 13)) { + /* GT1 SKU */ + debug("IVB GT1 Power Meter Weights\n"); + gtt_write_powermeter(gtt_bar, ivb_pm_gt1); + } else { + /* GT2 SKU */ + u32 tdp = readl(MCHBAR_REG(0x5930)) & 0x7fff; + tdp /= (1 << unit); + + if (tdp <= 17) { + /* <=17W ULV */ + debug("IVB GT2 17W Power Meter Weights\n"); + gtt_write_powermeter(gtt_bar, ivb_pm_gt2_17w); + } else if ((tdp >= 25) && (tdp <= 35)) { + /* 25W-35W */ + debug("IVB GT2 25W-35W Power Meter Weights\n"); + gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w); + } else { + /* All others */ + debug("IVB GT2 35W Power Meter Weights\n"); + gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w); + } + } + } + + /* 3: Gear ratio map */ + gtt_write(gtt_bar, 0xa004, 0x00000010); + + /* 4: GFXPAUSE */ + gtt_write(gtt_bar, 0xa000, 0x00070020); + + /* 5: Dynamic EU trip control */ + gtt_write(gtt_bar, 0xa080, 0x00000004); + + /* 6: ECO bits */ + reg32 = gtt_read(gtt_bar, 0xa180); + reg32 |= (1 << 26) | (1 << 31); + /* (bit 20=1 for SNB step D1+ / IVB A0+) */ + if (rev >= SNB_STEP_D1) + reg32 |= (1 << 20); + gtt_write(gtt_bar, 0xa180, reg32); + + /* 6a: for SnB step D2+ only */ + if (((rev & BASE_REV_MASK) == BASE_REV_SNB) && + (rev >= SNB_STEP_D2)) { + reg32 = gtt_read(gtt_bar, 0x9400); + reg32 |= (1 << 7); + gtt_write(gtt_bar, 0x9400, reg32); + + reg32 = gtt_read(gtt_bar, 0x941c); + reg32 &= 0xf; + reg32 |= (1 << 1); + gtt_write(gtt_bar, 0x941c, reg32); + gtt_poll(gtt_bar, 0x941c, (1 << 1), (0 << 1)); + } + + if ((rev & BASE_REV_MASK) == BASE_REV_IVB) { + reg32 = gtt_read(gtt_bar, 0x907c); + reg32 |= (1 << 16); + gtt_write(gtt_bar, 0x907c, reg32); + + /* 6b: Clocking reset controls */ + gtt_write(gtt_bar, 0x9424, 0x00000001); + } else { + /* 6b: Clocking reset controls */ + gtt_write(gtt_bar, 0x9424, 0x00000000); + } + + /* 7 */ + if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31))) { + gtt_write(gtt_bar, 0x138128, 0x00000029); /* Mailbox Data */ + /* Mailbox Cmd for RC6 VID */ + gtt_write(gtt_bar, 0x138124, 0x80000004); + if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31))) + gtt_write(gtt_bar, 0x138124, 0x8000000a); + gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31)); + } + + /* 8 */ + gtt_write(gtt_bar, 0xa090, 0x00000000); /* RC Control */ + gtt_write(gtt_bar, 0xa098, 0x03e80000); /* RC1e Wake Rate Limit */ + gtt_write(gtt_bar, 0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */ + gtt_write(gtt_bar, 0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */ + gtt_write(gtt_bar, 0xa0a8, 0x0001e848); /* RC Evaluation Interval */ + gtt_write(gtt_bar, 0xa0ac, 0x00000019); /* RC Idle Hysteresis */ + + /* 9 */ + gtt_write(gtt_bar, 0x2054, 0x0000000a); /* Render Idle Max Count */ + gtt_write(gtt_bar, 0x12054, 0x0000000a); /* Video Idle Max Count */ + gtt_write(gtt_bar, 0x22054, 0x0000000a); /* Blitter Idle Max Count */ + + /* 10 */ + gtt_write(gtt_bar, 0xa0b0, 0x00000000); /* Unblock Ack to Busy */ + gtt_write(gtt_bar, 0xa0b4, 0x000003e8); /* RC1e Threshold */ + gtt_write(gtt_bar, 0xa0b8, 0x0000c350); /* RC6 Threshold */ + gtt_write(gtt_bar, 0xa0bc, 0x000186a0); /* RC6p Threshold */ + gtt_write(gtt_bar, 0xa0c0, 0x0000fa00); /* RC6pp Threshold */ + + /* 11 */ + gtt_write(gtt_bar, 0xa010, 0x000f4240); /* RP Down Timeout */ + gtt_write(gtt_bar, 0xa014, 0x12060000); /* RP Interrupt Limits */ + gtt_write(gtt_bar, 0xa02c, 0x00015f90); /* RP Up Threshold */ + gtt_write(gtt_bar, 0xa030, 0x000186a0); /* RP Down Threshold */ + gtt_write(gtt_bar, 0xa068, 0x000186a0); /* RP Up EI */ + gtt_write(gtt_bar, 0xa06c, 0x000493e0); /* RP Down EI */ + gtt_write(gtt_bar, 0xa070, 0x0000000a); /* RP Idle Hysteresis */ + + /* 11a: Enable Render Standby (RC6) */ + if ((rev & BASE_REV_MASK) == BASE_REV_IVB) { + /* + * IvyBridge should also support DeepRenderStandby. + * + * Unfortunately it does not work reliably on all SKUs so + * disable it here and it can be enabled by the kernel. + */ + gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */ + } else { + gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */ + } + + /* 12: Normal Frequency Request */ + /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 (8 bits!? use 7) */ + reg32 = readl(MCHBAR_REG(0x5998)); + reg32 >>= 16; + reg32 &= 0xef; + reg32 <<= 25; + gtt_write(gtt_bar, 0xa008, reg32); + + /* 13: RP Control */ + gtt_write(gtt_bar, 0xa024, 0x00000592); + + /* 14: Enable PM Interrupts */ + gtt_write(gtt_bar, 0x4402c, 0x03000076); + + /* Clear 0x6c024 [8:6] */ + reg32 = gtt_read(gtt_bar, 0x6c024); + reg32 &= ~0x000001c0; + gtt_write(gtt_bar, 0x6c024, reg32); + + return 0; +} + +static int gma_pm_init_post_vbios(struct udevice *dev, int rev, void *gtt_bar) +{ + const void *blob = gd->fdt_blob; + int node = dev->of_offset; + u32 reg32, cycle_delay; + + debug("GT Power Management Init (post VBIOS)\n"); + + /* 15: Deassert Force Wake */ + if (rev < IVB_STEP_C0) { + gtt_write(gtt_bar, 0xa18c, gtt_read(gtt_bar, 0xa18c) & ~1); + gtt_poll(gtt_bar, 0x130090, (1 << 0), (0 << 0)); + } else { + gtt_write(gtt_bar, 0xa188, 0x1fffe); + if (gtt_poll(gtt_bar, 0x130040, (1 << 0), (0 << 0))) { + gtt_write(gtt_bar, 0xa188, + gtt_read(gtt_bar, 0xa188) | 1); + } + } + + /* 16: SW RC Control */ + gtt_write(gtt_bar, 0xa094, 0x00060000); + + /* Setup Digital Port Hotplug */ + reg32 = gtt_read(gtt_bar, 0xc4030); + if (!reg32) { + u32 dp_hotplug[3]; + + if (fdtdec_get_int_array(blob, node, "intel,dp_hotplug", + dp_hotplug, ARRAY_SIZE(dp_hotplug))) + return -EINVAL; + + reg32 = (dp_hotplug[0] & 0x7) << 2; + reg32 |= (dp_hotplug[0] & 0x7) << 10; + reg32 |= (dp_hotplug[0] & 0x7) << 18; + gtt_write(gtt_bar, 0xc4030, reg32); + } + + /* Setup Panel Power On Delays */ + reg32 = gtt_read(gtt_bar, 0xc7208); + if (!reg32) { + reg32 = (unsigned)fdtdec_get_int(blob, node, + "panel-port-select", 0) << 30; + reg32 |= fdtdec_get_int(blob, node, "panel-power-up-delay", 0) + << 16; + reg32 |= fdtdec_get_int(blob, node, + "panel-power-backlight-on-delay", 0); + gtt_write(gtt_bar, 0xc7208, reg32); + } + + /* Setup Panel Power Off Delays */ + reg32 = gtt_read(gtt_bar, 0xc720c); + if (!reg32) { + reg32 = fdtdec_get_int(blob, node, "panel-power-down-delay", 0) + << 16; + reg32 |= fdtdec_get_int(blob, node, + "panel-power-backlight-off-delay", 0); + gtt_write(gtt_bar, 0xc720c, reg32); + } + + /* Setup Panel Power Cycle Delay */ + cycle_delay = fdtdec_get_int(blob, node, + "intel,panel-power-cycle-delay", 0); + if (cycle_delay) { + reg32 = gtt_read(gtt_bar, 0xc7210); + reg32 &= ~0xff; + reg32 |= cycle_delay; + gtt_write(gtt_bar, 0xc7210, reg32); + } + + /* Enable Backlight if needed */ + reg32 = fdtdec_get_int(blob, node, "intel,cpu-backlight", 0); + if (reg32) { + gtt_write(gtt_bar, 0x48250, (1 << 31)); + gtt_write(gtt_bar, 0x48254, reg32); + } + reg32 = fdtdec_get_int(blob, node, "intel,pch-backlight", 0); + if (reg32) { + gtt_write(gtt_bar, 0xc8250, (1 << 31)); + gtt_write(gtt_bar, 0xc8254, reg32); + } + + return 0; +} + +/* + * Some vga option roms are used for several chipsets but they only have one + * PCI ID in their header. If we encounter such an option rom, we need to do + * the mapping ourselves. + */ + +uint32_t board_map_oprom_vendev(uint32_t vendev) +{ + switch (vendev) { + case 0x80860102: /* GT1 Desktop */ + case 0x8086010a: /* GT1 Server */ + case 0x80860112: /* GT2 Desktop */ + case 0x80860116: /* GT2 Mobile */ + case 0x80860122: /* GT2 Desktop >=1.3GHz */ + case 0x80860126: /* GT2 Mobile >=1.3GHz */ + case 0x80860156: /* IVB */ + case 0x80860166: /* IVB */ + return 0x80860106; /* GT1 Mobile */ + } + + return vendev; +} + +static int int15_handler(void) +{ + int res = 0; + + debug("%s: INT15 function %04x!\n", __func__, M.x86.R_AX); + + switch (M.x86.R_AX) { + case 0x5f34: + /* + * Set Panel Fitting Hook: + * bit 2 = Graphics Stretching + * bit 1 = Text Stretching + * bit 0 = Centering (do not set with bit1 or bit2) + * 0 = video bios default + */ + M.x86.R_AX = 0x005f; + M.x86.R_CL = 0x00; /* Use video bios default */ + res = 1; + break; + case 0x5f35: + /* + * Boot Display Device Hook: + * bit 0 = CRT + * bit 1 = TV (eDP) + * bit 2 = EFP + * bit 3 = LFP + * bit 4 = CRT2 + * bit 5 = TV2 (eDP) + * bit 6 = EFP2 + * bit 7 = LFP2 + */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = 0x0000; /* Use video bios default */ + res = 1; + break; + case 0x5f51: + /* + * Hook to select active LFP configuration: + * 00h = No LVDS, VBIOS does not enable LVDS + * 01h = Int-LVDS, LFP driven by integrated LVDS decoder + * 02h = SVDO-LVDS, LFP driven by SVDO decoder + * 03h = eDP, LFP Driven by Int-DisplayPort encoder + */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = 0x0003; /* eDP */ + res = 1; + break; + case 0x5f70: + switch (M.x86.R_CH) { + case 0: + /* Get Mux */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = 0x0000; + res = 1; + break; + case 1: + /* Set Mux */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = 0x0000; + res = 1; + break; + case 2: + /* Get SG/Non-SG mode */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = 0x0000; + res = 1; + break; + default: + /* Interrupt was not handled */ + debug("Unknown INT15 5f70 function: 0x%02x\n", + M.x86.R_CH); + break; + } + break; + case 0x5fac: + res = 1; + break; + default: + debug("Unknown INT15 function %04x!\n", M.x86.R_AX); + break; + } + return res; +} + +static void sandybridge_setup_graphics(struct udevice *dev, + struct udevice *video_dev) +{ + u32 reg32; + u16 reg16; + u8 reg8; + + dm_pci_read_config16(video_dev, PCI_DEVICE_ID, ®16); + switch (reg16) { + case 0x0102: /* GT1 Desktop */ + case 0x0106: /* GT1 Mobile */ + case 0x010a: /* GT1 Server */ + case 0x0112: /* GT2 Desktop */ + case 0x0116: /* GT2 Mobile */ + case 0x0122: /* GT2 Desktop >=1.3GHz */ + case 0x0126: /* GT2 Mobile >=1.3GHz */ + case 0x0156: /* IvyBridge */ + case 0x0166: /* IvyBridge */ + break; + default: + debug("Graphics not supported by this CPU/chipset\n"); + return; + } + + debug("Initialising Graphics\n"); + + /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */ + dm_pci_read_config16(dev, GGC, ®16); + reg16 &= ~0x00f8; + reg16 |= 1 << 3; + /* Program GTT memory by setting GGC[9:8] = 2MB */ + reg16 &= ~0x0300; + reg16 |= 2 << 8; + /* Enable VGA decode */ + reg16 &= ~0x0002; + dm_pci_write_config16(dev, GGC, reg16); + + /* Enable 256MB aperture */ + dm_pci_read_config8(video_dev, MSAC, ®8); + reg8 &= ~0x06; + reg8 |= 0x02; + dm_pci_write_config8(video_dev, MSAC, reg8); + + /* Erratum workarounds */ + reg32 = readl(MCHBAR_REG(0x5f00)); + reg32 |= (1 << 9) | (1 << 10); + writel(reg32, MCHBAR_REG(0x5f00)); + + /* Enable SA Clock Gating */ + reg32 = readl(MCHBAR_REG(0x5f00)); + writel(reg32 | 1, MCHBAR_REG(0x5f00)); + + /* GPU RC6 workaround for sighting 366252 */ + reg32 = readl(MCHBAR_REG(0x5d14)); + reg32 |= (1 << 31); + writel(reg32, MCHBAR_REG(0x5d14)); + + /* VLW */ + reg32 = readl(MCHBAR_REG(0x6120)); + reg32 &= ~(1 << 0); + writel(reg32, MCHBAR_REG(0x6120)); + + reg32 = readl(MCHBAR_REG(0x5418)); + reg32 |= (1 << 4) | (1 << 5); + writel(reg32, MCHBAR_REG(0x5418)); +} + +static int gma_func0_init(struct udevice *dev) +{ + struct udevice *nbridge; + void *gtt_bar; + ulong base; + u32 reg32; + int ret; + int rev; + + /* Enable PCH Display Port */ + writew(0x0010, RCB_REG(DISPBDF)); + setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF); + + ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &nbridge); + if (ret) + return ret; + rev = bridge_silicon_revision(nbridge); + sandybridge_setup_graphics(nbridge, dev); + + /* IGD needs to be Bus Master */ + dm_pci_read_config32(dev, PCI_COMMAND, ®32); + reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + dm_pci_write_config32(dev, PCI_COMMAND, reg32); + + /* Use write-combining for the graphics memory, 256MB */ + base = dm_pci_read_bar32(dev, 2); + mtrr_add_request(MTRR_TYPE_WRCOMB, base, 256 << 20); + mtrr_commit(true); + + gtt_bar = (void *)dm_pci_read_bar32(dev, 0); + debug("GT bar %p\n", gtt_bar); + ret = gma_pm_init_pre_vbios(gtt_bar, rev); + if (ret) + return ret; + + return rev; +} + +static int bd82x6x_video_probe(struct udevice *dev) +{ + void *gtt_bar; + int ret, rev; + + rev = gma_func0_init(dev); + if (rev < 0) + return rev; + ret = vbe_setup_video(dev, int15_handler); + if (ret) + return ret; + + /* Post VBIOS init */ + gtt_bar = (void *)dm_pci_read_bar32(dev, 0); + ret = gma_pm_init_post_vbios(dev, rev, gtt_bar); + if (ret) + return ret; + + return 0; +} + +static const struct udevice_id bd82x6x_video_ids[] = { + { .compatible = "intel,gma" }, + { } +}; + +U_BOOT_DRIVER(bd82x6x_video) = { + .name = "bd82x6x_video", + .id = UCLASS_VIDEO, + .of_match = bd82x6x_video_ids, + .probe = bd82x6x_video_probe, +}; -- cgit v1.1 From 443ffe509c7bedca440fbd37e3853895c8fe31f2 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 5 Oct 2016 20:42:19 -0600 Subject: dm: x86: Move samus to use new driver model support Update the samus driver to avoid the direct call to the video BIOS setup. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- drivers/video/broadwell_igd.c | 39 +++++++-------------------------------- 1 file changed, 7 insertions(+), 32 deletions(-) (limited to 'drivers') diff --git a/drivers/video/broadwell_igd.c b/drivers/video/broadwell_igd.c index 4286fd0..beef770 100644 --- a/drivers/video/broadwell_igd.c +++ b/drivers/video/broadwell_igd.c @@ -9,10 +9,8 @@ #include #include #include -#include #include #include -#include #include #include #include @@ -20,11 +18,9 @@ #include #include #include -#include #include "i915_reg.h" struct broadwell_igd_priv { - GraphicDevice ctfb; u8 *regs; }; @@ -664,10 +660,7 @@ static int broadwell_igd_probe(struct udevice *dev) { struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); struct video_priv *uc_priv = dev_get_uclass_priv(dev); - struct broadwell_igd_priv *priv = dev_get_priv(dev); bool is_broadwell; - GraphicDevice *gdev = &priv->ctfb; - int bits_per_pixel; int ret; if (!ll_boot_init()) { @@ -683,13 +676,9 @@ static int broadwell_igd_probe(struct udevice *dev) debug("%s: is_broadwell=%d\n", __func__, is_broadwell); ret = igd_pre_init(dev, is_broadwell); if (!ret) { - ret = dm_pci_run_vga_bios(dev, broadwell_igd_int15_handler, - PCI_ROM_USE_NATIVE | - PCI_ROM_ALLOW_FALLBACK); - if (ret) { - printf("failed to run video BIOS: %d\n", ret); - ret = -EIO; - } + ret = vbe_setup_video(dev, broadwell_igd_int15_handler); + if (ret) + debug("failed to run video BIOS: %d\n", ret); } if (!ret) ret = igd_post_init(dev, is_broadwell); @@ -697,13 +686,8 @@ static int broadwell_igd_probe(struct udevice *dev) if (ret) return ret; - if (vbe_get_video_info(gdev)) { - printf("No video mode configured\n"); - return -ENXIO; - } - - /* Use write-through for the graphics memory, 256MB */ - ret = mtrr_add_request(MTRR_TYPE_WRTHROUGH, gdev->pciBase, 256 << 20); + /* Use write-combining for the graphics memory, 256MB */ + ret = mtrr_add_request(MTRR_TYPE_WRCOMB, plat->base, 256 << 20); if (!ret) ret = mtrr_commit(true); if (ret && ret != -ENOSYS) { @@ -711,17 +695,8 @@ static int broadwell_igd_probe(struct udevice *dev) ret); } - bits_per_pixel = gdev->gdfBytesPP * 8; - sprintf(gdev->modeIdent, "%dx%dx%d", gdev->winSizeX, gdev->winSizeY, - bits_per_pixel); - printf("%s\n", gdev->modeIdent); - uc_priv->xsize = gdev->winSizeX; - uc_priv->ysize = gdev->winSizeY; - uc_priv->bpix = ilog2(bits_per_pixel); - plat->base = gdev->pciBase; - plat->size = gdev->memSize; - debug("fb=%x, size %x, display size=%d %d %d\n", gdev->pciBase, - gdev->memSize, uc_priv->xsize, uc_priv->ysize, uc_priv->bpix); + debug("fb=%lx, size %x, display size=%d %d %d\n", plat->base, + plat->size, uc_priv->xsize, uc_priv->ysize, uc_priv->bpix); return 0; } -- cgit v1.1 From 2cd11a23c8e01503032df34b99d563603a54f4d9 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 25 Sep 2016 21:33:06 -0600 Subject: bios_emulator: Fix cast for 64-bit compilation Fix a cast that causes warnings on 64-bit machines. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- drivers/bios_emulator/atibios.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/bios_emulator/atibios.c b/drivers/bios_emulator/atibios.c index 7717246..2d5b5dc 100644 --- a/drivers/bios_emulator/atibios.c +++ b/drivers/bios_emulator/atibios.c @@ -599,7 +599,7 @@ int biosemu_run(pci_dev_t pcidev, uchar *bios_rom, int bios_len, if (clean_up) { BE_exit(); if (vga_info->BIOSImage && - (u32)(vga_info->BIOSImage) != 0xc0000) + (ulong)(vga_info->BIOSImage) != 0xc0000) free(vga_info->BIOSImage); free(vga_info); vga_info = NULL; -- cgit v1.1 From 3f14f814e79f5160e91a107fcac56d577867feac Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 25 Sep 2016 21:33:11 -0600 Subject: rtc: Use CONFIG_X86 instead of __I386__ For 64-bit x86, __I386__ should perhaps not be defined. It is not clear from the definition, but let's use CONFIG_X86 to be sure. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- drivers/rtc/mc146818.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/rtc/mc146818.c b/drivers/rtc/mc146818.c index da804d5..4df9eda 100644 --- a/drivers/rtc/mc146818.c +++ b/drivers/rtc/mc146818.c @@ -14,7 +14,7 @@ #include #include -#if defined(__I386__) || defined(CONFIG_MALTA) +#if defined(CONFIG_X86) || defined(CONFIG_MALTA) #include #define in8(p) inb(p) #define out8(p, v) outb(v, p) -- cgit v1.1 From 22230e916e1d57364c524058275befa380faabc3 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 25 Sep 2016 21:33:20 -0600 Subject: tpm: Tidy up use of size_t We should consistently use %z with size_t, and avoid passing a uint32_t as a size_t value. Fix these issues to avoid warnings on 64-bit machines. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- drivers/tpm/tpm_tis_lpc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/tpm/tpm_tis_lpc.c b/drivers/tpm/tpm_tis_lpc.c index 257d035..b4efbb5 100644 --- a/drivers/tpm/tpm_tis_lpc.c +++ b/drivers/tpm/tpm_tis_lpc.c @@ -204,7 +204,7 @@ static int tis_senddata(struct udevice *dev, const u8 *data, size_t len) /* Wait till the device is ready to accept more data. */ while (!burst) { if (max_cycles++ == MAX_DELAY_US) { - printf("%s:%d failed to feed %d bytes of %d\n", + printf("%s:%d failed to feed %zd bytes of %zd\n", __FILE__, __LINE__, len - offset, len); return -ETIMEDOUT; } @@ -224,7 +224,7 @@ static int tis_senddata(struct udevice *dev, const u8 *data, size_t len) * changes to zero exactly after the last byte is fed into the * FIFO. */ - count = min((u32)burst, len - offset - 1); + count = min((size_t)burst, len - offset - 1); while (count--) tpm_write_byte(priv, data[offset++], ®s[locality].data); -- cgit v1.1 From b11e2984401ff8a4f53d6d4c6363af4c9a4ec336 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 25 Sep 2016 21:33:21 -0600 Subject: usb: pci: Fix cast for 64-bit compilation Fix a cast that causes warnings on 64-bit machines. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- drivers/usb/host/ehci-pci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c index 6fc2479..f20fc33 100644 --- a/drivers/usb/host/ehci-pci.c +++ b/drivers/usb/host/ehci-pci.c @@ -32,8 +32,8 @@ static void ehci_pci_init(struct udevice *dev, struct ehci_hccr **ret_hccr, hcor = (struct ehci_hcor *)((uintptr_t) hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); - debug("EHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n", - (u32)hccr, (u32)hcor, + debug("EHCI-PCI init hccr %#lx and hcor %#lx hc_length %d\n", + (ulong)hccr, (ulong)hcor, (u32)HC_LENGTH(ehci_readl(&hccr->cr_capbase))); *ret_hccr = hccr; -- cgit v1.1 From fac3e796b915226e2dc92363826824be1589c3ef Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 25 Sep 2016 21:33:30 -0600 Subject: x86: i2c: Fix cast of address to 32-bit value This gives a build warning on 64-bit x86. Fix it. Signed-off-by: Simon Glass Acked-by: Heiko Schocher Reviewed-by: Bin Meng --- drivers/i2c/intel_i2c.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/intel_i2c.c b/drivers/i2c/intel_i2c.c index a0182dc..550a728 100644 --- a/drivers/i2c/intel_i2c.c +++ b/drivers/i2c/intel_i2c.c @@ -248,11 +248,11 @@ static int intel_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) static int intel_i2c_probe(struct udevice *dev) { struct intel_i2c *priv = dev_get_priv(dev); - u32 base; + ulong base; /* Save base address from PCI BAR */ - priv->base = (u32)dm_pci_map_bar(dev, PCI_BASE_ADDRESS_4, - PCI_REGION_IO); + priv->base = (ulong)dm_pci_map_bar(dev, PCI_BASE_ADDRESS_4, + PCI_REGION_IO); base = priv->base; /* Set SMBus enable. */ -- cgit v1.1 From 02c57abd5079dec2311cf51e785bd2090b7bb440 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 9 Oct 2016 04:14:11 -0700 Subject: dm: video: Add driver for VESA-compatible device This adds a DM driver for VESA-compatible device. Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- drivers/video/vesa.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 drivers/video/vesa.c (limited to 'drivers') diff --git a/drivers/video/vesa.c b/drivers/video/vesa.c new file mode 100644 index 0000000..ddf8df8 --- /dev/null +++ b/drivers/video/vesa.c @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2016, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +static int vesa_video_probe(struct udevice *dev) +{ + return vbe_setup_video(dev, NULL); +} + +static const struct udevice_id vesa_video_ids[] = { + { .compatible = "vesa-fb" }, + { } +}; + +U_BOOT_DRIVER(vesa_video) = { + .name = "vesa_video", + .id = UCLASS_VIDEO, + .of_match = vesa_video_ids, + .probe = vesa_video_probe, +}; + +static struct pci_device_id vesa_video_supported[] = { + { PCI_DEVICE_CLASS(PCI_CLASS_DISPLAY_VGA << 8, ~0) }, + { }, +}; + +U_BOOT_PCI_DEVICE(vesa_video, vesa_video_supported); -- cgit v1.1 From f0920e4a4498294bf8328db37638f47bccf04b3f Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 9 Oct 2016 04:14:12 -0700 Subject: dm: video: Output verbose information in vbe_setup_video() With DM conversion, information like "Video: 1024x768x16" is not shown anymore. Now add these verbose output back. Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- drivers/pci/pci_rom.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index 21ed17c..5746c3d 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -382,9 +382,13 @@ int vbe_setup_video(struct udevice *dev, int (*int15_handler)(void)) struct video_priv *uc_priv = dev_get_uclass_priv(dev); int ret; + printf("Video: "); + /* If we are running from EFI or coreboot, this can't work */ - if (!ll_boot_init()) + if (!ll_boot_init()) { + printf("Not available (previous bootloader prevents it)\n"); return -EPERM; + } bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display"); ret = dm_pci_run_vga_bios(dev, int15_handler, PCI_ROM_USE_NATIVE | PCI_ROM_ALLOW_FALLBACK); @@ -400,6 +404,9 @@ int vbe_setup_video(struct udevice *dev, int (*int15_handler)(void)) return ret; } + printf("%dx%dx%d\n", uc_priv->xsize, uc_priv->ysize, + mode_info.vesa.bits_per_pixel); + return 0; } #endif -- cgit v1.1 From fcda8c388699d8602158aa16a1e9c607dac93df9 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 9 Oct 2016 04:14:13 -0700 Subject: x86: Convert to use DM VESA video driver At present only chromebook boards are converted to DM video. Other x86 boards are still using the legacy cfb_console driver. This switches to use DM version drivers. Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- drivers/video/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/video/Makefile b/drivers/video/Makefile index b888e99..8a99d24 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -58,7 +58,7 @@ obj-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o videomodes.o obj-$(CONFIG_VIDEO_TEGRA20) += tegra.o obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o -obj-$(CONFIG_VIDEO_VESA) += vesa_fb.o +obj-$(CONFIG_VIDEO_VESA) += vesa.o obj-$(CONFIG_FORMIKE) += formike.o obj-$(CONFIG_LG4573) += lg4573.o obj-$(CONFIG_AM335X_LCD) += am335x-fb.o -- cgit v1.1 From 5f6ad029f31e897fa8bd62d3f42092e051932bc2 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 9 Oct 2016 04:14:15 -0700 Subject: vbe: Make vbe_setup_video_priv() public vbe_setup_video_priv() might be useful to other drivers. Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- drivers/pci/pci_rom.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index 5746c3d..cd083f7 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -351,9 +351,9 @@ err: } #ifdef CONFIG_DM_VIDEO -static int vbe_setup_video_priv(struct vesa_mode_info *vesa, - struct video_priv *uc_priv, - struct video_uc_platdata *plat) +int vbe_setup_video_priv(struct vesa_mode_info *vesa, + struct video_priv *uc_priv, + struct video_uc_platdata *plat) { if (!vesa->x_resolution) return -ENXIO; -- cgit v1.1 From 13b2bfce5104ad7b4243025554a354a2000b352b Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 9 Oct 2016 04:14:16 -0700 Subject: dm: video: Add driver for coreboot framebuffer device This adds a DM driver for coreboot framebuffer device. Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- drivers/video/Kconfig | 9 ++++++ drivers/video/coreboot.c | 79 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 88 insertions(+) create mode 100644 drivers/video/coreboot.c (limited to 'drivers') diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index fd26690..86db0da 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -101,6 +101,15 @@ config VIDCONSOLE_AS_LCD to update the environment, the breakage may be confusing for users. This option will be removed around the end of 2016. +config VIDEO_COREBOOT + bool "Enable coreboot framebuffer driver support" + depends on X86 && SYS_COREBOOT + help + Turn on this option to enable a framebuffer driver when U-Boot is + loaded by coreboot where the graphics device is configured by + coreboot already. This can in principle be used with any platform + that coreboot supports. + config VIDEO_VESA bool "Enable VESA video driver support" default n diff --git a/drivers/video/coreboot.c b/drivers/video/coreboot.c new file mode 100644 index 0000000..3a94aa1 --- /dev/null +++ b/drivers/video/coreboot.c @@ -0,0 +1,79 @@ +/* + * Copyright (C) 2016, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +static int save_vesa_mode(struct cb_framebuffer *fb, + struct vesa_mode_info *vesa) +{ + /* + * If there is no framebuffer structure, bail out and keep + * running on the serial console. + */ + if (!fb) + return -ENXIO; + + vesa->x_resolution = fb->x_resolution; + vesa->y_resolution = fb->y_resolution; + vesa->bits_per_pixel = fb->bits_per_pixel; + vesa->bytes_per_scanline = fb->bytes_per_line; + vesa->phys_base_ptr = fb->physical_address; + vesa->red_mask_size = fb->red_mask_size; + vesa->red_mask_pos = fb->red_mask_pos; + vesa->green_mask_size = fb->green_mask_size; + vesa->green_mask_pos = fb->green_mask_pos; + vesa->blue_mask_size = fb->blue_mask_size; + vesa->blue_mask_pos = fb->blue_mask_pos; + vesa->reserved_mask_size = fb->reserved_mask_size; + vesa->reserved_mask_pos = fb->reserved_mask_pos; + + return 0; +} + +static int coreboot_video_probe(struct udevice *dev) +{ + struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); + struct video_priv *uc_priv = dev_get_uclass_priv(dev); + struct cb_framebuffer *fb = lib_sysinfo.framebuffer; + struct vesa_mode_info *vesa = &mode_info.vesa; + int ret; + + printf("Video: "); + + /* Initialize vesa_mode_info structure */ + ret = save_vesa_mode(fb, vesa); + if (ret) + goto err; + + ret = vbe_setup_video_priv(vesa, uc_priv, plat); + if (ret) + goto err; + + printf("%dx%dx%d\n", uc_priv->xsize, uc_priv->ysize, + vesa->bits_per_pixel); + + return 0; + +err: + printf("No video mode configured in coreboot!\n"); + return ret; +} + +static const struct udevice_id coreboot_video_ids[] = { + { .compatible = "coreboot-fb" }, + { } +}; + +U_BOOT_DRIVER(coreboot_video) = { + .name = "coreboot_video", + .id = UCLASS_VIDEO, + .of_match = coreboot_video_ids, + .probe = coreboot_video_probe, +}; -- cgit v1.1 From 3968398eb2d974b4840d7210d8503d7cbd8f4c48 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 9 Oct 2016 04:14:17 -0700 Subject: dm: video: Don't do anything in alloc_fb() when plat->size is zero With DM VESA driver on x86 boards, plat->base/size/align are all zeroes and starting address passed to alloc_fb() happens to be 1MB aligned, so this routine does not trigger any issue. On QEMU with U-Boot as coreboot payload, the starting address is within 1MB range (eg: 0x7fb0000), thus causes failure in video_post_bind(). Actually if plat->size is zero, it makes no sense to do anything in this routine. Add such check there. Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- drivers/video/video-uclass.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c index b6dd0f5..11ca793 100644 --- a/drivers/video/video-uclass.c +++ b/drivers/video/video-uclass.c @@ -54,6 +54,9 @@ static ulong alloc_fb(struct udevice *dev, ulong *addrp) struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); ulong base, align, size; + if (!plat->size) + return 0; + align = plat->align ? plat->align : 1 << 20; base = *addrp - plat->size; base &= ~(align - 1); -- cgit v1.1 From 2d3c573ee6373f4521491f1a38e81245c3a6be57 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 9 Oct 2016 04:14:18 -0700 Subject: x86: coreboot: Convert to use DM coreboot video driver This converts coreboot to use DM framebuffer driver. Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- drivers/video/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 8a99d24..4a42417 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -37,7 +37,7 @@ obj-$(CONFIG_S6E63D6) += s6e63d6.o obj-$(CONFIG_LD9040) += ld9040.o obj-$(CONFIG_SED156X) += sed156x.o obj-$(CONFIG_VIDEO_BCM2835) += bcm2835.o -obj-$(CONFIG_VIDEO_COREBOOT) += coreboot_fb.o +obj-$(CONFIG_VIDEO_COREBOOT) += coreboot.o obj-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o obj-$(CONFIG_VIDEO_IMX25LCDC) += imx25lcdc.o videomodes.o -- cgit v1.1 From 21c9bcebd0e388a7acc2b1a3dc38127e0fd6182c Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 9 Oct 2016 04:14:19 -0700 Subject: video: Remove legacy VESA and coreboot framebuffer drivers Now that all x86 boards have been converted to DM video, drop the legacy drivers. Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- drivers/video/coreboot_fb.c | 108 -------------------------------------------- drivers/video/vesa_fb.c | 63 -------------------------- 2 files changed, 171 deletions(-) delete mode 100644 drivers/video/coreboot_fb.c delete mode 100644 drivers/video/vesa_fb.c (limited to 'drivers') diff --git a/drivers/video/coreboot_fb.c b/drivers/video/coreboot_fb.c deleted file mode 100644 index feb5463..0000000 --- a/drivers/video/coreboot_fb.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * coreboot Framebuffer driver. - * - * Copyright (C) 2011 The Chromium OS authors - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include "videomodes.h" - -/* - * The Graphic Device - */ -GraphicDevice ctfb; - -static void save_vesa_mode(void) -{ - struct vesa_mode_info *vesa = &mode_info.vesa; - struct cb_framebuffer *fb = lib_sysinfo.framebuffer; - - vesa->x_resolution = fb->x_resolution; - vesa->y_resolution = fb->y_resolution; - vesa->bits_per_pixel = fb->bits_per_pixel; - vesa->bytes_per_scanline = fb->bytes_per_line; - vesa->phys_base_ptr = fb->physical_address; - vesa->red_mask_size = fb->red_mask_size; - vesa->red_mask_pos = fb->red_mask_pos; - vesa->green_mask_size = fb->green_mask_size; - vesa->green_mask_pos = fb->green_mask_pos; - vesa->blue_mask_size = fb->blue_mask_size; - vesa->blue_mask_pos = fb->blue_mask_pos; - vesa->reserved_mask_size = fb->reserved_mask_size; - vesa->reserved_mask_pos = fb->reserved_mask_pos; -} - -static int parse_coreboot_table_fb(GraphicDevice *gdev) -{ - struct cb_framebuffer *fb = lib_sysinfo.framebuffer; - - /* If there is no framebuffer structure, bail out and keep - * running on the serial console. - */ - if (!fb) - return 0; - - gdev->winSizeX = fb->x_resolution; - gdev->winSizeY = fb->y_resolution; - - gdev->plnSizeX = fb->x_resolution; - gdev->plnSizeY = fb->y_resolution; - - gdev->gdfBytesPP = fb->bits_per_pixel / 8; - - switch (fb->bits_per_pixel) { - case 24: - gdev->gdfIndex = GDF_32BIT_X888RGB; - break; - case 16: - gdev->gdfIndex = GDF_16BIT_565RGB; - break; - default: - gdev->gdfIndex = GDF__8BIT_INDEX; - break; - } - - gdev->isaBase = CONFIG_SYS_ISA_IO_BASE_ADDRESS; - gdev->pciBase = (unsigned int)fb->physical_address; - - gdev->frameAdrs = (unsigned int)fb->physical_address; - gdev->memSize = fb->bytes_per_line * fb->y_resolution; - - gdev->vprBase = (unsigned int)fb->physical_address; - gdev->cprBase = (unsigned int)fb->physical_address; - - return 1; -} - -void *video_hw_init(void) -{ - GraphicDevice *gdev = &ctfb; - int bits_per_pixel; - - printf("Video: "); - - if (!parse_coreboot_table_fb(gdev)) { - printf("No video mode configured in coreboot!\n"); - return NULL; - } - - bits_per_pixel = gdev->gdfBytesPP * 8; - - /* fill in Graphic device struct */ - sprintf(gdev->modeIdent, "%dx%dx%d", gdev->winSizeX, gdev->winSizeY, - bits_per_pixel); - printf("%s\n", gdev->modeIdent); - - memset((void *)gdev->pciBase, 0, - gdev->winSizeX * gdev->winSizeY * gdev->gdfBytesPP); - - /* Initialize vesa_mode_info structure */ - save_vesa_mode(); - - return (void *)gdev; -} diff --git a/drivers/video/vesa_fb.c b/drivers/video/vesa_fb.c deleted file mode 100644 index 021c1d6..0000000 --- a/drivers/video/vesa_fb.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * VESA frame buffer driver - * - * Copyright (C) 2014 Google, Inc - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -/* - * The Graphic Device - */ -GraphicDevice ctfb; - -void *video_hw_init(void) -{ - GraphicDevice *gdev = &ctfb; - struct udevice *dev; - int bits_per_pixel; - int ret; - - printf("Video: "); - if (!ll_boot_init()) { - /* - * If we are running from EFI or coreboot, this driver can't - * work. - */ - printf("Not available (previous bootloader prevents it)\n"); - return NULL; - } - if (vbe_get_video_info(gdev)) { - ret = dm_pci_find_class(PCI_CLASS_DISPLAY_VGA << 8, 0, &dev); - if (ret) { - printf("no card detected\n"); - return NULL; - } - bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display"); - ret = dm_pci_run_vga_bios(dev, NULL, PCI_ROM_USE_NATIVE | - PCI_ROM_ALLOW_FALLBACK); - bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD); - if (ret) { - printf("failed to run video BIOS: %d\n", ret); - return NULL; - } - } - - if (vbe_get_video_info(gdev)) { - printf("No video mode configured\n"); - return NULL; - } - - bits_per_pixel = gdev->gdfBytesPP * 8; - sprintf(gdev->modeIdent, "%dx%dx%d", gdev->winSizeX, gdev->winSizeY, - bits_per_pixel); - printf("%s\n", gdev->modeIdent); - debug("Frame buffer at %x\n", gdev->pciBase); - - return (void *)gdev; -} -- cgit v1.1