From 959198f7cacea1076b3a43721ec173266f3158af Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Fri, 16 May 2014 13:59:52 +0900 Subject: mmc: exynos_dw_mmc: restore the property into host Restore the platdata(property of dt) into host struct. Then data's information is maintained and reused anywhere. Signed-off-by: Jaehoon Chung Tested-by: Lukasz Majewski Acked-by: Lukasz Majewski Signed-off-by: Minkyu Kang --- drivers/mmc/exynos_dw_mmc.c | 204 ++++++++++++++++++++++++++++---------------- 1 file changed, 131 insertions(+), 73 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index de8cdcc..28941ad 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -13,6 +13,8 @@ #include #include #include +#include +#include #define DWMMC_MAX_CH_NUM 4 #define DWMMC_MAX_FREQ 52000000 @@ -44,7 +46,11 @@ unsigned int exynos_dwmci_get_clk(struct dwmci_host *host) & DWMCI_DIVRATIO_MASK) + 1; sclk = get_mmc_clk(host->dev_index); - return sclk / clk_div; + /* + * Assume to know divider value. + * When clock unit is broken, need to set "host->div" + */ + return sclk / clk_div / (host->div + 1); } static void exynos_dwmci_board_init(struct dwmci_host *host) @@ -60,45 +66,32 @@ static void exynos_dwmci_board_init(struct dwmci_host *host) } } -/* - * This function adds the mmc channel to be registered with mmc core. - * index - mmc channel number. - * regbase - register base address of mmc channel specified in 'index'. - * bus_width - operating bus width of mmc channel specified in 'index'. - * clksel - value to be written into CLKSEL register in case of FDT. - * NULL in case od non-FDT. - */ -int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel) +static int exynos_dwmci_core_init(struct dwmci_host *host, int index) { - struct dwmci_host *host = NULL; unsigned int div; unsigned long freq, sclk; - host = malloc(sizeof(struct dwmci_host)); - if (!host) { - printf("dwmci_host malloc fail!\n"); - return 1; - } + + if (host->bus_hz) + freq = host->bus_hz; + else + freq = DWMMC_MAX_FREQ; + /* request mmc clock vlaue of 52MHz. */ - freq = 52000000; sclk = get_mmc_clk(index); div = DIV_ROUND_UP(sclk, freq); /* set the clock divisor for mmc */ set_mmc_clk(index, div); host->name = "EXYNOS DWMMC"; - host->ioaddr = (void *)regbase; - host->buswidth = bus_width; #ifdef CONFIG_EXYNOS5420 host->quirks = DWMCI_QUIRK_DISABLE_SMU; #endif host->board_init = exynos_dwmci_board_init; - if (clksel) { - host->clksel_val = clksel; - } else { - if (0 == index) + if (!host->clksel_val) { + if (index == 0) host->clksel_val = DWMMC_MMC0_CLKSEL_VAL; - if (2 == index) + else if (index == 2) host->clksel_val = DWMMC_MMC2_CLKSEL_VAL; } @@ -113,69 +106,134 @@ int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel) return 0; } +/* + * This function adds the mmc channel to be registered with mmc core. + * index - mmc channel number. + * regbase - register base address of mmc channel specified in 'index'. + * bus_width - operating bus width of mmc channel specified in 'index'. + * clksel - value to be written into CLKSEL register in case of FDT. + * NULL in case od non-FDT. + */ +int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel) +{ + struct dwmci_host *host = NULL; + + host = malloc(sizeof(struct dwmci_host)); + if (!host) { + error("dwmci_host malloc fail!\n"); + return -ENOMEM; + } + + host->ioaddr = (void *)regbase; + host->buswidth = bus_width; + + if (clksel) + host->clksel_val = clksel; + + return exynos_dwmci_core_init(host, index); +} + #ifdef CONFIG_OF_CONTROL -int exynos_dwmmc_init(const void *blob) +static struct dwmci_host dwmci_host[DWMMC_MAX_CH_NUM]; + +static int do_dwmci_init(struct dwmci_host *host) { - int index, bus_width; - int node_list[DWMMC_MAX_CH_NUM]; - int err = 0, dev_id, flag, count, i; - u32 clksel_val, base, timing[3]; + int index, flag, err; - count = fdtdec_find_aliases_for_id(blob, "mmc", - COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list, - DWMMC_MAX_CH_NUM); + index = host->dev_index; - for (i = 0; i < count; i++) { - int node = node_list[i]; + flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE; + err = exynos_pinmux_config(host->dev_id, flag); + if (err) { + debug("DWMMC not configure\n"); + return err; + } - if (node <= 0) - continue; + return exynos_dwmci_core_init(host, index); +} - /* Extract device id for each mmc channel */ - dev_id = pinmux_decode_periph_id(blob, node); +static int exynos_dwmci_get_config(const void *blob, int node, + struct dwmci_host *host) +{ + int err = 0; + u32 base, clksel_val, timing[3]; - /* Get the bus width from the device node */ - bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0); - if (bus_width <= 0) { - debug("DWMMC: Can't get bus-width\n"); - return -1; - } - if (8 == bus_width) - flag = PINMUX_FLAG_8BIT_MODE; - else - flag = PINMUX_FLAG_NONE; + /* Extract device id for each mmc channel */ + host->dev_id = pinmux_decode_periph_id(blob, node); - /* config pinmux for each mmc channel */ - err = exynos_pinmux_config(dev_id, flag); - if (err) { - debug("DWMMC not configured\n"); - return err; - } + /* Get the bus width from the device node */ + host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 0); + if (host->buswidth <= 0) { + debug("DWMMC: Can't get bus-width\n"); + return -EINVAL; + } - index = dev_id - PERIPH_ID_SDMMC0; + host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id); + if (host->dev_index == host->dev_id) + host->dev_index = host->dev_id - PERIPH_ID_SDMMC0; - /* Get the base address from the device node */ - base = fdtdec_get_addr(blob, node, "reg"); - if (!base) { - debug("DWMMC: Can't get base address\n"); - return -1; - } - /* Extract the timing info from the node */ - err = fdtdec_get_int_array(blob, node, "samsung,timing", - timing, 3); + /* Set the base address from the device node */ + base = fdtdec_get_addr(blob, node, "reg"); + if (!base) { + debug("DWMMC: Can't get base address\n"); + return -EINVAL; + } + host->ioaddr = (void *)base; + + /* Extract the timing info from the node */ + err = fdtdec_get_int_array(blob, node, "samsung,timing", timing, 3); + if (err) { + debug("Can't get sdr-timings for devider\n"); + return -EINVAL; + } + + clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) | + DWMCI_SET_DRV_CLK(timing[1]) | + DWMCI_SET_DIV_RATIO(timing[2])); + if (clksel_val) + host->clksel_val = clksel_val; + + host->fifoth_val = fdtdec_get_int(blob, node, "fifoth_val", 0); + host->bus_hz = fdtdec_get_int(blob, node, "bus_hz", 0); + host->div = fdtdec_get_int(blob, node, "div", 0); + + return 0; +} + +static int exynos_dwmci_process_node(const void *blob, + int node_list[], int count) +{ + struct dwmci_host *host; + int i, node, err; + + for (i = 0; i < count; i++) { + node = node_list[i]; + if (node <= 0) + continue; + host = &dwmci_host[i]; + err = exynos_dwmci_get_config(blob, node, host); if (err) { - debug("Can't get sdr-timings for divider\n"); - return -1; + debug("%s: failed to decode dev %d\n", __func__, i); + return err; } - clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) | - DWMCI_SET_DRV_CLK(timing[1]) | - DWMCI_SET_DIV_RATIO(timing[2])); - /* Initialise each mmc channel */ - err = exynos_dwmci_add_port(index, base, bus_width, clksel_val); - if (err) - debug("dwmmc Channel-%d init failed\n", index); + do_dwmci_init(host); } return 0; } + +int exynos_dwmmc_init(const void *blob) +{ + int compat_id; + int node_list[DWMMC_MAX_CH_NUM]; + int err = 0, count; + + compat_id = COMPAT_SAMSUNG_EXYNOS_DWMMC; + + count = fdtdec_find_aliases_for_id(blob, "mmc", + compat_id, node_list, DWMMC_MAX_CH_NUM); + err = exynos_dwmci_process_node(blob, node_list, count); + + return err; +} #endif -- cgit v1.1 From 8caf46d1890b625aafe9cc16114b3c65842dbb98 Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Fri, 16 May 2014 13:59:53 +0900 Subject: mmc: remove the unnecessary define and fix the wrong bit control Signed-off-by: Jaehoon Chung Reviewed-by: Lukasz Majeski Tested-by: Lukasz Majewski Acked-by: Lukasz Majewski Signed-off-by: Minkyu Kang --- drivers/mmc/mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 16051e5..dd6a6ef 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -514,7 +514,7 @@ static int mmc_change_freq(struct mmc *mmc) return 0; /* High Speed is set, there are two types: 52MHz and 26MHz */ - if (cardtype & MMC_HS_52MHZ) + if (cardtype & EXT_CSD_CARD_TYPE_52) mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; else mmc->card_caps |= MMC_MODE_HS; -- cgit v1.1 From d22e3d46a918bde2e6d3bc3f5782548d5ed75358 Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Fri, 16 May 2014 13:59:54 +0900 Subject: mmc: support the DDR mode for eMMC Signed-off-by: Jaehoon Chung Tested-by: Lukasz Majewski Acked-by: Lukasz Majewski Signed-off-by: Minkyu Kang --- drivers/mmc/mmc.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index dd6a6ef..08187d5 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -158,6 +158,9 @@ int mmc_set_blocklen(struct mmc *mmc, int len) { struct mmc_cmd cmd; + if (mmc->card_caps & MMC_MODE_DDR_52MHz) + return 0; + cmd.cmdidx = MMC_CMD_SET_BLOCKLEN; cmd.resp_type = MMC_RSP_R1; cmd.cmdarg = len; @@ -514,10 +517,13 @@ static int mmc_change_freq(struct mmc *mmc) return 0; /* High Speed is set, there are two types: 52MHz and 26MHz */ - if (cardtype & EXT_CSD_CARD_TYPE_52) + if (cardtype & EXT_CSD_CARD_TYPE_52) { + if (cardtype & EXT_CSD_CARD_TYPE_DDR_52) + mmc->card_caps |= MMC_MODE_DDR_52MHz; mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; - else + } else { mmc->card_caps |= MMC_MODE_HS; + } return 0; } @@ -1054,6 +1060,8 @@ static int mmc_startup(struct mmc *mmc) /* An array of possible bus widths in order of preference */ static unsigned ext_csd_bits[] = { + EXT_CSD_DDR_BUS_WIDTH_8, + EXT_CSD_DDR_BUS_WIDTH_4, EXT_CSD_BUS_WIDTH_8, EXT_CSD_BUS_WIDTH_4, EXT_CSD_BUS_WIDTH_1, @@ -1061,13 +1069,15 @@ static int mmc_startup(struct mmc *mmc) /* An array to map CSD bus widths to host cap bits */ static unsigned ext_to_hostcaps[] = { + [EXT_CSD_DDR_BUS_WIDTH_4] = MMC_MODE_DDR_52MHz, + [EXT_CSD_DDR_BUS_WIDTH_8] = MMC_MODE_DDR_52MHz, [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT, [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT, }; /* An array to map chosen bus width to an integer */ static unsigned widths[] = { - 8, 4, 1, + 8, 4, 8, 4, 1, }; for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) { -- cgit v1.1 From 045bdcd0b2ff02effef09d945cee685b88ec521d Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Fri, 16 May 2014 13:59:55 +0900 Subject: mmc: dw_mmc: support the DDR mode Support the DDR mode at dw-mmc controller Signed-off-by: Jaehoon Chung Tested-by: Lukasz Majewski Acked-by: Lukasz Majewski Signed-off-by: Minkyu Kang --- drivers/mmc/dw_mmc.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index eb4e2be..5bf36a0 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -284,8 +284,8 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) static void dwmci_set_ios(struct mmc *mmc) { - struct dwmci_host *host = mmc->priv; - u32 ctype; + struct dwmci_host *host = (struct dwmci_host *)mmc->priv; + u32 ctype, regs; debug("Buswidth = %d, clock: %d\n",mmc->bus_width, mmc->clock); @@ -304,6 +304,14 @@ static void dwmci_set_ios(struct mmc *mmc) dwmci_writel(host, DWMCI_CTYPE, ctype); + regs = dwmci_readl(host, DWMCI_UHS_REG); + if (mmc->card_caps & MMC_MODE_DDR_52MHz) + regs |= DWMCI_DDR_MODE; + else + regs &= DWMCI_DDR_MODE; + + dwmci_writel(host, DWMCI_UHS_REG, regs); + if (host->clksel) host->clksel(host); } -- cgit v1.1 From e09bd85329186015ec1bc663c0d55dd6bec41d2a Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Fri, 16 May 2014 13:59:57 +0900 Subject: mmc: exynos_dw_mmc: enable the DDR mode Set the ddr mode capability by default. Signed-off-by: Jaehoon Chung Tested-by: Lukasz Majewski Acked-by: Lukasz Majewski Signed-off-by: Minkyu Kang --- drivers/mmc/exynos_dw_mmc.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index 28941ad..d96dfe1 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -95,6 +95,7 @@ static int exynos_dwmci_core_init(struct dwmci_host *host, int index) host->clksel_val = DWMMC_MMC2_CLKSEL_VAL; } + host->caps = MMC_MODE_DDR_52MHz; host->clksel = exynos_dwmci_clksel; host->dev_index = index; host->get_mmc_clk = exynos_dwmci_get_clk; -- cgit v1.1 From 9b8c9a3c093afbde1577bd8270904c4d36969ff9 Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Fri, 16 May 2014 13:59:59 +0900 Subject: mmc: s5p_sdhci: add the s5p_sdhci_core_init function To reuse the code, added the s5p_sdhci_core_init function. Before applied this patch, didn't use the 8-bit mode at exynos baord. Because it didn't set "MMC_MODE_8BIT". Signed-off-by: Jaehoon Chung Tested-by: Lukasz Majewski Acked-by: Lukasz Majewski Signed-off-by: Minkyu Kang --- drivers/mmc/s5p_sdhci.c | 42 +++++++++++++++++------------------------- 1 file changed, 17 insertions(+), 25 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c index ccae4cc..2ff0ec2 100644 --- a/drivers/mmc/s5p_sdhci.c +++ b/drivers/mmc/s5p_sdhci.c @@ -65,17 +65,9 @@ static void s5p_sdhci_set_control_reg(struct sdhci_host *host) sdhci_writel(host, ctrl, SDHCI_CONTROL2); } -int s5p_sdhci_init(u32 regbase, int index, int bus_width) +static int s5p_sdhci_core_init(struct sdhci_host *host) { - struct sdhci_host *host = NULL; - host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host)); - if (!host) { - printf("sdhci__host malloc fail!\n"); - return 1; - } - host->name = S5P_NAME; - host->ioaddr = (void *)regbase; host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE | SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR | @@ -85,15 +77,28 @@ int s5p_sdhci_init(u32 regbase, int index, int bus_width) host->set_control_reg = &s5p_sdhci_set_control_reg; host->set_clock = set_mmc_clk; - host->index = index; host->host_caps = MMC_MODE_HC; - if (bus_width == 8) + if (host->bus_width == 8) host->host_caps |= MMC_MODE_8BIT; return add_sdhci(host, 52000000, 400000); } +int s5p_sdhci_init(u32 regbase, int index, int bus_width) +{ + struct sdhci_host *host = malloc(sizeof(struct sdhci_host)); + if (!host) { + printf("sdhci__host malloc fail!\n"); + return 1; + } + host->ioaddr = (void *)regbase; + host->index = index; + host->bus_width = bus_width; + + return s5p_sdhci_core_init(host); +} + #ifdef CONFIG_OF_CONTROL struct sdhci_host sdhci_host[SDHCI_MAX_HOSTS]; @@ -126,20 +131,7 @@ static int do_sdhci_init(struct sdhci_host *host) } } - host->name = S5P_NAME; - - host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE | - SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR | - SDHCI_QUIRK_WAIT_SEND_CMD; - host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; - host->version = sdhci_readw(host, SDHCI_HOST_VERSION); - - host->set_control_reg = &s5p_sdhci_set_control_reg; - host->set_clock = set_mmc_clk; - - host->host_caps = MMC_MODE_HC; - - return add_sdhci(host, 52000000, 400000); + return s5p_sdhci_core_init(host); } static int sdhci_get_config(const void *blob, int node, struct sdhci_host *host) -- cgit v1.1 From 913702ca397755e06fcc126a063ebbf814ac869b Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 20 May 2014 06:01:34 -0600 Subject: power: Rename CONFIG_PMIC_... to CONFIG_POWER_... Commit be3b51aa did this mostly, but several have been added since. Do the job again. Signed-off-by: Simon Glass Acked-by: Lukasz Majewski Signed-off-by: Minkyu Kang --- drivers/power/power_fsl.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/power/power_fsl.c b/drivers/power/power_fsl.c index ac0b541..a64161b 100644 --- a/drivers/power/power_fsl.c +++ b/drivers/power/power_fsl.c @@ -11,9 +11,9 @@ #include #include -#if defined(CONFIG_PMIC_FSL_MC13892) +#if defined(CONFIG_POWER_FSL_MC13892) #define FSL_PMIC_I2C_LENGTH 3 -#elif defined(CONFIG_PMIC_FSL_MC34704) +#elif defined(CONFIG_POWER_FSL_MC34704) #define FSL_PMIC_I2C_LENGTH 1 #endif @@ -51,7 +51,7 @@ int pmic_init(unsigned char bus) p->hw.i2c.addr = CONFIG_SYS_FSL_PMIC_I2C_ADDR; p->hw.i2c.tx_num = FSL_PMIC_I2C_LENGTH; #else -#error "You must select CONFIG_POWER_SPI or CONFIG_PMIC_I2C" +#error "You must select CONFIG_POWER_SPI or CONFIG_POWER_I2C" #endif return 0; -- cgit v1.1 From 78a36c3ef390f7780840db3b42837e55e002829a Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 20 May 2014 06:01:35 -0600 Subject: power: Add PMIC_ prefix to CHARGER_EN/DISABLE This enum should be common across all PMICs rather than having it independently defined with the same name in multiple places. Signed-off-by: Simon Glass Signed-off-by: Minkyu Kang --- drivers/power/battery/bat_trats.c | 4 ++-- drivers/power/battery/bat_trats2.c | 2 +- drivers/power/mfd/pmic_max77693.c | 2 +- drivers/power/pmic/pmic_max8997.c | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/power/battery/bat_trats.c b/drivers/power/battery/bat_trats.c index 41b179f..bfde692 100644 --- a/drivers/power/battery/bat_trats.c +++ b/drivers/power/battery/bat_trats.c @@ -19,7 +19,7 @@ static int power_battery_charge(struct pmic *bat) struct battery *battery = p_bat->bat; int k; - if (bat->chrg->chrg_state(p_bat->chrg, CHARGER_ENABLE, 450)) + if (bat->chrg->chrg_state(p_bat->chrg, PMIC_CHARGER_ENABLE, 450)) return -1; for (k = 0; bat->chrg->chrg_bat_present(p_bat->chrg) && @@ -42,7 +42,7 @@ static int power_battery_charge(struct pmic *bat) } } exit: - bat->chrg->chrg_state(p_bat->chrg, CHARGER_DISABLE, 0); + bat->chrg->chrg_state(p_bat->chrg, PMIC_CHARGER_DISABLE, 0); return 0; } diff --git a/drivers/power/battery/bat_trats2.c b/drivers/power/battery/bat_trats2.c index 94015aa..57221ad 100644 --- a/drivers/power/battery/bat_trats2.c +++ b/drivers/power/battery/bat_trats2.c @@ -17,7 +17,7 @@ static int power_battery_charge(struct pmic *bat) { struct power_battery *p_bat = bat->pbat; - if (bat->chrg->chrg_state(p_bat->chrg, CHARGER_ENABLE, 450)) + if (bat->chrg->chrg_state(p_bat->chrg, PMIC_CHARGER_ENABLE, 450)) return -1; return 0; diff --git a/drivers/power/mfd/pmic_max77693.c b/drivers/power/mfd/pmic_max77693.c index 1a4416b..6b28e28 100644 --- a/drivers/power/mfd/pmic_max77693.c +++ b/drivers/power/mfd/pmic_max77693.c @@ -22,7 +22,7 @@ static int max77693_charger_state(struct pmic *p, int state, int current) val = MAX77693_CHG_UNLOCK; pmic_reg_write(p, MAX77693_CHG_CNFG_06, val); - if (state == CHARGER_DISABLE) { + if (state == PMIC_CHARGER_DISABLE) { puts("Disable the charger.\n"); pmic_reg_read(p, MAX77693_CHG_CNFG_00, &val); val &= ~0x01; diff --git a/drivers/power/pmic/pmic_max8997.c b/drivers/power/pmic/pmic_max8997.c index ba01692..a36a9a0 100644 --- a/drivers/power/pmic/pmic_max8997.c +++ b/drivers/power/pmic/pmic_max8997.c @@ -35,7 +35,7 @@ static int pmic_charger_state(struct pmic *p, int state, int current) if (pmic_probe(p)) return -1; - if (state == CHARGER_DISABLE) { + if (state == PMIC_CHARGER_DISABLE) { puts("Disable the charger.\n"); pmic_reg_read(p, MAX8997_REG_MBCCTRL2, &val); val &= ~(MBCHOSTEN | VCHGR_FC); -- cgit v1.1 From ac1058fdb72b8a6dade7c81be31b22760099ee91 Mon Sep 17 00:00:00 2001 From: Tom Wai-Hong Tam Date: Tue, 20 May 2014 06:01:36 -0600 Subject: power: Add support for TPS65090 PMU chip. This adds driver support for the TPS65090 PMU. Support includes hooking into the pmic infrastructure so that the pmic commands can be used on the console. The TPS65090 supports the following functionality: - fet enable/disable/querying - getting and setting of charge state Even though it is connected to the pmic infrastructure it does not hook into the pmic charging charging infrastructure. The device tree binding is from Linux, but only a small subset of functionality is supported. Signed-off-by: Tom Wai-Hong Tam Signed-off-by: Hatim Ali Signed-off-by: Katie Roberts-Hoffman Signed-off-by: Rong Chang Signed-off-by: Sean Paul Signed-off-by: Vincent Palatin Signed-off-by: Aaron Durbin Signed-off-by: Simon Glass Signed-off-by: Minkyu Kang --- drivers/power/pmic/Makefile | 1 + drivers/power/pmic/pmic_tps65090.c | 310 +++++++++++++++++++++++++++++++++++++ 2 files changed, 311 insertions(+) create mode 100644 drivers/power/pmic/pmic_tps65090.c (limited to 'drivers') diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index 4129bda..3244f69 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -10,5 +10,6 @@ obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o +obj-$(CONFIG_POWER_TPS65090) += pmic_tps65090.o obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o diff --git a/drivers/power/pmic/pmic_tps65090.c b/drivers/power/pmic/pmic_tps65090.c new file mode 100644 index 0000000..c5b3966 --- /dev/null +++ b/drivers/power/pmic/pmic_tps65090.c @@ -0,0 +1,310 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define TPS65090_NAME "TPS65090_PMIC" + +/* TPS65090 register addresses */ +enum { + REG_IRQ1 = 0, + REG_CG_CTRL0 = 4, + REG_CG_STATUS1 = 0xa, + REG_FET1_CTRL = 0x0f, + REG_FET2_CTRL, + REG_FET3_CTRL, + REG_FET4_CTRL, + REG_FET5_CTRL, + REG_FET6_CTRL, + REG_FET7_CTRL, + TPS65090_NUM_REGS, +}; + +enum { + IRQ1_VBATG = 1 << 3, + CG_CTRL0_ENC_MASK = 0x01, + + MAX_FET_NUM = 7, + MAX_CTRL_READ_TRIES = 5, + + /* TPS65090 FET_CTRL register values */ + FET_CTRL_TOFET = 1 << 7, /* Timeout, startup, overload */ + FET_CTRL_PGFET = 1 << 4, /* Power good for FET status */ + FET_CTRL_WAIT = 3 << 2, /* Overcurrent timeout max */ + FET_CTRL_ADENFET = 1 << 1, /* Enable output auto discharge */ + FET_CTRL_ENFET = 1 << 0, /* Enable FET */ +}; + +/** + * Checks for a valid FET number + * + * @param fet_id FET number to check + * @return 0 if ok, -EINVAL if FET value is out of range + */ +static int tps65090_check_fet(unsigned int fet_id) +{ + if (fet_id == 0 || fet_id > MAX_FET_NUM) { + debug("parameter fet_id is out of range, %u not in 1 ~ %u\n", + fet_id, MAX_FET_NUM); + return -EINVAL; + } + + return 0; +} + +/** + * Set the power state for a FET + * + * @param pmic pmic structure for the tps65090 + * @param fet_id Fet number to set (1..MAX_FET_NUM) + * @param set 1 to power on FET, 0 to power off + * @return -EIO if we got a comms error, -EAGAIN if the FET failed to + * change state. If all is ok, returns 0. + */ +static int tps65090_fet_set(struct pmic *pmic, int fet_id, bool set) +{ + int retry; + u32 reg, value; + + value = FET_CTRL_ADENFET | FET_CTRL_WAIT; + if (set) + value |= FET_CTRL_ENFET; + + if (pmic_reg_write(pmic, REG_FET1_CTRL + fet_id - 1, value)) + return -EIO; + + /* Try reading until we get a result */ + for (retry = 0; retry < MAX_CTRL_READ_TRIES; retry++) { + if (pmic_reg_read(pmic, REG_FET1_CTRL + fet_id - 1, ®)) + return -EIO; + + /* Check that the fet went into the expected state */ + if (!!(reg & FET_CTRL_PGFET) == set) + return 0; + + /* If we got a timeout, there is no point in waiting longer */ + if (reg & FET_CTRL_TOFET) + break; + + mdelay(1); + } + + debug("FET %d: Power good should have set to %d but reg=%#02x\n", + fet_id, set, reg); + return -EAGAIN; +} + +int tps65090_fet_enable(unsigned int fet_id) +{ + struct pmic *pmic; + ulong start; + int loops; + int ret; + + ret = tps65090_check_fet(fet_id); + if (ret) + return ret; + + pmic = pmic_get(TPS65090_NAME); + if (!pmic) + return -EACCES; + + start = get_timer(0); + for (loops = 0;; loops++) { + ret = tps65090_fet_set(pmic, fet_id, true); + if (!ret) + break; + + if (get_timer(start) > 100) + break; + + /* Turn it off and try again until we time out */ + tps65090_fet_set(pmic, fet_id, false); + } + + if (ret) + debug("%s: FET%d failed to power on: time=%lums, loops=%d\n", + __func__, fet_id, get_timer(start), loops); + else if (loops) + debug("%s: FET%d powered on after %lums, loops=%d\n", + __func__, fet_id, get_timer(start), loops); + + /* + * Unfortunately, there are some conditions where the power + * good bit will be 0, but the fet still comes up. One such + * case occurs with the lcd backlight. We'll just return 0 here + * and assume that the fet will eventually come up. + */ + if (ret == -EAGAIN) + ret = 0; + + return ret; +} + +int tps65090_fet_disable(unsigned int fet_id) +{ + struct pmic *pmic; + int ret; + + ret = tps65090_check_fet(fet_id); + if (ret) + return ret; + + pmic = pmic_get(TPS65090_NAME); + if (!pmic) + return -EACCES; + ret = tps65090_fet_set(pmic, fet_id, false); + + return ret; +} + +int tps65090_fet_is_enabled(unsigned int fet_id) +{ + struct pmic *pmic; + u32 reg; + int ret; + + ret = tps65090_check_fet(fet_id); + if (ret) + return ret; + + pmic = pmic_get(TPS65090_NAME); + if (!pmic) + return -ENODEV; + ret = pmic_reg_read(pmic, REG_FET1_CTRL + fet_id - 1, ®); + if (ret) { + debug("fail to read FET%u_CTRL register over I2C", fet_id); + return -EIO; + } + + return reg & FET_CTRL_ENFET; +} + +int tps65090_get_charging(void) +{ + struct pmic *pmic; + u32 val; + int ret; + + pmic = pmic_get(TPS65090_NAME); + if (!pmic) + return -EACCES; + + ret = pmic_reg_read(pmic, REG_CG_CTRL0, &val); + if (ret) + return ret; + + return !!(val & CG_CTRL0_ENC_MASK); +} + +static int tps65090_charger_state(struct pmic *pmic, int state, + int current) +{ + u32 val; + int ret; + + ret = pmic_reg_read(pmic, REG_CG_CTRL0, &val); + if (!ret) { + if (state == PMIC_CHARGER_ENABLE) + val |= CG_CTRL0_ENC_MASK; + else + val &= ~CG_CTRL0_ENC_MASK; + ret = pmic_reg_write(pmic, REG_CG_CTRL0, val); + } + if (ret) { + debug("%s: Failed to read/write register\n", __func__); + return ret; + } + + return 0; +} + +int tps65090_get_status(void) +{ + struct pmic *pmic; + u32 val; + int ret; + + pmic = pmic_get(TPS65090_NAME); + if (!pmic) + return -EACCES; + + ret = pmic_reg_read(pmic, REG_CG_STATUS1, &val); + if (ret) + return ret; + + return val; +} + +static int tps65090_charger_bat_present(struct pmic *pmic) +{ + u32 val; + int ret; + + ret = pmic_reg_read(pmic, REG_IRQ1, &val); + if (ret) + return ret; + + return !!(val & IRQ1_VBATG); +} + +static struct power_chrg power_chrg_pmic_ops = { + .chrg_bat_present = tps65090_charger_bat_present, + .chrg_state = tps65090_charger_state, +}; + +int tps65090_init(void) +{ + struct pmic *p; + int bus; + int addr; + const void *blob = gd->fdt_blob; + int node, parent; + + node = fdtdec_next_compatible(blob, 0, COMPAT_TI_TPS65090); + if (node < 0) { + debug("PMIC: No node for PMIC Chip in device tree\n"); + debug("node = %d\n", node); + return -ENODEV; + } + + parent = fdt_parent_offset(blob, node); + if (parent < 0) { + debug("%s: Cannot find node parent\n", __func__); + return -EINVAL; + } + + bus = i2c_get_bus_num_fdt(parent); + if (p->bus < 0) { + debug("%s: Cannot find I2C bus\n", __func__); + return -ENOENT; + } + addr = fdtdec_get_int(blob, node, "reg", TPS65090_I2C_ADDR); + p = pmic_alloc(); + if (!p) { + printf("%s: POWER allocation error!\n", __func__); + return -ENOMEM; + } + + p->name = TPS65090_NAME; + p->bus = bus; + p->interface = PMIC_I2C; + p->number_of_regs = TPS65090_NUM_REGS; + p->hw.i2c.addr = addr; + p->hw.i2c.tx_num = 1; + p->chrg = &power_chrg_pmic_ops; + + puts("TPS65090 PMIC init\n"); + + return 0; +} -- cgit v1.1 From 0b259dc2e849183dfea604fa137bb616e09b319a Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 20 May 2014 06:01:38 -0600 Subject: power: Explicitly select pmic device's bus The current pmic i2c code assumes the current i2c bus is the same as the pmic device's bus. There is nothing ensuring that to be true. Therefore, select the proper bus before performing a transaction. Signed-off-by: Aaron Durbin Signed-off-by: Simon Glass Acked-by: Heiko Schocher Reviewed-by: Simon Glass Signed-off-by: Minkyu Kang --- drivers/power/power_i2c.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers') diff --git a/drivers/power/power_i2c.c b/drivers/power/power_i2c.c index ac76870..594cd11 100644 --- a/drivers/power/power_i2c.c +++ b/drivers/power/power_i2c.c @@ -23,6 +23,8 @@ int pmic_reg_write(struct pmic *p, u32 reg, u32 val) if (check_reg(p, reg)) return -1; + I2C_SET_BUS(p->bus); + switch (pmic_i2c_tx_num) { case 3: if (p->sensor_byte_order == PMIC_SENSOR_BYTE_ORDER_BIG) { @@ -66,6 +68,8 @@ int pmic_reg_read(struct pmic *p, u32 reg, u32 *val) if (check_reg(p, reg)) return -1; + I2C_SET_BUS(p->bus); + if (i2c_read(pmic_i2c_addr, reg, 1, buf, pmic_i2c_tx_num)) return -1; -- cgit v1.1 From b98c5755c04eb5e15c614efefa7b9a2f3b0cd06c Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Fri, 11 Apr 2014 12:55:29 +0530 Subject: mtd: nand: omap_elm: remove #include omap_gpmc.h There is no dependency of omap_elm.c on omap_gpmc.h Signed-off-by: Pekon Gupta Reviewed-by: Stefan Roese --- drivers/mtd/nand/omap_elm.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/omap_elm.c b/drivers/mtd/nand/omap_elm.c index 47b1f1b..4c65f3b 100644 --- a/drivers/mtd/nand/omap_elm.c +++ b/drivers/mtd/nand/omap_elm.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include -- cgit v1.1 From 41bbe4dd49a3825e024e874ee19c6527860a3f16 Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Fri, 11 Apr 2014 12:55:30 +0530 Subject: mtd: nand: omap_elm: use bch_type instead of nibble count to differentiate between BCH4/BCH8/BCH16 ELM hardware engine support ECC error detection for multiple ECC strengths like +------+------------------------+ |Type | ECC syndrome length | +------+------------------------+ |BCH4 | 6.5 bytes = 13 nibbles | |BCH8 | 13 byte = 26 nibbles | |BCH16 | 26 bytes = 52 nibbles | +------+------------------------+ Current implementation of omap_elm driver uses ECC syndrom length (in 'nibbles') to differentiate between BCH4/BCH8/BCH16. This patch replaces it with 'bch_type' Signed-off-by: Pekon Gupta Reviewed-by: Stefan Roese --- drivers/mtd/nand/omap_elm.c | 20 ++++++++------------ drivers/mtd/nand/omap_gpmc.c | 10 ++-------- 2 files changed, 10 insertions(+), 20 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/omap_elm.c b/drivers/mtd/nand/omap_elm.c index 4c65f3b..afa629a 100644 --- a/drivers/mtd/nand/omap_elm.c +++ b/drivers/mtd/nand/omap_elm.c @@ -24,14 +24,12 @@ struct elm *elm_cfg; /** - * elm_load_syndromes - Load BCH syndromes based on nibble selection + * elm_load_syndromes - Load BCH syndromes based on bch_type selection * @syndrome: BCH syndrome - * @nibbles: + * @bch_type: BCH4/BCH8/BCH16 * @poly: Syndrome Polynomial set to use - * - * Load BCH syndromes based on nibble selection */ -static void elm_load_syndromes(u8 *syndrome, u32 nibbles, u8 poly) +static void elm_load_syndromes(u8 *syndrome, enum bch_level bch_type, u8 poly) { u32 *ptr; u32 val; @@ -47,8 +45,7 @@ static void elm_load_syndromes(u8 *syndrome, u32 nibbles, u8 poly) (syndrome[7] << 24); writel(val, ptr); - /* BCH 8-bit with 26 nibbles (4*8=32) */ - if (nibbles > 13) { + if (bch_type == BCH_8_BIT || bch_type == BCH_16_BIT) { /* reg 2 */ ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[2]; val = syndrome[8] | (syndrome[9] << 8) | (syndrome[10] << 16) | @@ -61,8 +58,7 @@ static void elm_load_syndromes(u8 *syndrome, u32 nibbles, u8 poly) writel(val, ptr); } - /* BCH 16-bit with 52 nibbles (7*8=56) */ - if (nibbles > 26) { + if (bch_type == BCH_16_BIT) { /* reg 4 */ ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[4]; val = syndrome[16] | (syndrome[17] << 8) | @@ -86,7 +82,7 @@ static void elm_load_syndromes(u8 *syndrome, u32 nibbles, u8 poly) /** * elm_check_errors - Check for BCH errors and return error locations * @syndrome: BCH syndrome - * @nibbles: + * @bch_type: BCH4/BCH8/BCH16 * @error_count: Returns number of errrors in the syndrome * @error_locations: Returns error locations (in decimal) in this array * @@ -94,14 +90,14 @@ static void elm_load_syndromes(u8 *syndrome, u32 nibbles, u8 poly) * and locations in the array passed. Returns -1 if error is not correctable, * else returns 0 */ -int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count, +int elm_check_error(u8 *syndrome, enum bch_level bch_type, u32 *error_count, u32 *error_locations) { u8 poly = ELM_DEFAULT_POLY; s8 i; u32 location_status; - elm_load_syndromes(syndrome, nibbles, poly); + elm_load_syndromes(syndrome, bch_type, poly); /* start processing */ writel((readl(&elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6]) diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index bf99b8e..e84bc7b 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -153,7 +153,6 @@ static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat, struct nand_bch_priv { uint8_t mode; uint8_t type; - uint8_t nibbles; struct bch_control *control; enum omap_ecc ecc_scheme; }; @@ -163,11 +162,6 @@ struct nand_bch_priv { #define ECC_BCH8 1 #define ECC_BCH16 2 -/* BCH nibbles for diff bch levels */ -#define ECC_BCH4_NIBBLES 13 -#define ECC_BCH8_NIBBLES 26 -#define ECC_BCH16_NIBBLES 52 - /* * This can be a single instance cause all current users have only one NAND * with nearly the same setup (BCH8, some with ELM and others with sw BCH @@ -176,7 +170,6 @@ struct nand_bch_priv { */ static __maybe_unused struct nand_bch_priv bch_priv = { .type = ECC_BCH8, - .nibbles = ECC_BCH8_NIBBLES, .control = NULL }; @@ -383,7 +376,8 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, } /* use elm module to check for errors */ elm_config((enum bch_level)(bch->type)); - if (elm_check_error(calc_ecc, bch->nibbles, &error_count, error_loc)) { + if (elm_check_error(calc_ecc, (enum bch_level)bch->type, + &error_count, error_loc)) { printf("nand: error: uncorrectable ECC errors\n"); return -EINVAL; } -- cgit v1.1 From d21e77ff84019b17e180b27267b23f51e6d609fa Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Fri, 11 Apr 2014 12:55:32 +0530 Subject: mtd: nand: omap_gpmc: remove unused members of 'struct nand_bch_priv' This patch prepares to refactor 'struct nand_bch_priv' -> 'struct omap_nand_info' And thus performs following clean-ups: - remove nand_bch_priv.type: use nand_bch_priv.ecc_scheme instead - remove nand_bch_priv.mode: Signed-off-by: Pekon Gupta Reviewed-by: Stefan Roese --- drivers/mtd/nand/omap_gpmc.c | 23 ++++++----------------- 1 file changed, 6 insertions(+), 17 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index e84bc7b..1972b0e 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -151,17 +151,10 @@ static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat, * Generic BCH interface */ struct nand_bch_priv { - uint8_t mode; - uint8_t type; struct bch_control *control; enum omap_ecc ecc_scheme; }; -/* bch types */ -#define ECC_BCH4 0 -#define ECC_BCH8 1 -#define ECC_BCH16 2 - /* * This can be a single instance cause all current users have only one NAND * with nearly the same setup (BCH8, some with ELM and others with sw BCH @@ -169,7 +162,6 @@ struct nand_bch_priv { * When some users with other BCH strength will exists this have to change! */ static __maybe_unused struct nand_bch_priv bch_priv = { - .type = ECC_BCH8, .control = NULL }; @@ -342,6 +334,7 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, uint32_t eccbytes = chip->ecc.bytes; uint32_t error_count = 0, error_max; uint32_t error_loc[8]; + enum bch_level bch_type; uint32_t i, ecc_flag = 0; uint8_t count, err = 0; uint32_t byte_pos, bit_pos; @@ -369,22 +362,22 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, */ switch (bch->ecc_scheme) { case OMAP_ECC_BCH8_CODE_HW: + bch_type = BCH_8_BIT; omap_reverse_list(calc_ecc, eccbytes - 1); break; default: return -EINVAL; } /* use elm module to check for errors */ - elm_config((enum bch_level)(bch->type)); - if (elm_check_error(calc_ecc, (enum bch_level)bch->type, - &error_count, error_loc)) { + elm_config(bch_type); + if (elm_check_error(calc_ecc, bch_type, &error_count, error_loc)) { printf("nand: error: uncorrectable ECC errors\n"); return -EINVAL; } /* correct bch error */ for (count = 0; count < error_count; count++) { - switch (bch->type) { - case ECC_BCH8: + switch (bch->ecc_scheme) { + case OMAP_ECC_BCH8_CODE_HW: /* 14th byte in ECC is reserved to match ROM layout */ error_max = SECTOR_BYTES + (eccbytes - 1); break; @@ -562,7 +555,6 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, /* For this ecc-scheme, ecc.bytes, ecc.layout, ... are * initialized in nand_scan_tail(), so just set ecc.mode */ bch_priv.control = NULL; - bch_priv.type = 0; nand->ecc.mode = NAND_ECC_SOFT; nand->ecc.layout = NULL; nand->ecc.size = 0; @@ -578,7 +570,6 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, return -EINVAL; } bch_priv.control = NULL; - bch_priv.type = 0; /* populate ecc specific fields */ memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl)); nand->ecc.mode = NAND_ECC_HW; @@ -617,7 +608,6 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, printf("nand: error: could not init_bch()\n"); return -ENODEV; } - bch_priv.type = ECC_BCH8; /* populate ecc specific fields */ memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl)); nand->ecc.mode = NAND_ECC_HW; @@ -659,7 +649,6 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, } /* intialize ELM for ECC error detection */ elm_init(); - bch_priv.type = ECC_BCH8; /* populate ecc specific fields */ memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl)); nand->ecc.mode = NAND_ECC_HW; -- cgit v1.1 From 9233279f8e33d1b3d21958d8afe10fbc3e46b3f2 Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Fri, 11 Apr 2014 12:55:33 +0530 Subject: mtd: nand: omap_gpmc: rename struct nand_bch_priv to struct omap_nand_info This patch renames 'struct nand_bch_priv' which currently holds private data only for BCH ECC schemes, into 'struct omap_nand_info' so that same can be used for all ECC schemes Signed-off-by: Pekon Gupta Reviewed-by: Stefan Roese --- drivers/mtd/nand/omap_gpmc.c | 58 ++++++++++++++++++++------------------------ 1 file changed, 26 insertions(+), 32 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index 1972b0e..391a268 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -148,9 +148,9 @@ static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat, } /* - * Generic BCH interface + * Driver configurations */ -struct nand_bch_priv { +struct omap_nand_info { struct bch_control *control; enum omap_ecc ecc_scheme; }; @@ -161,7 +161,7 @@ struct nand_bch_priv { * library). * When some users with other BCH strength will exists this have to change! */ -static __maybe_unused struct nand_bch_priv bch_priv = { +static __maybe_unused struct omap_nand_info omap_nand_info = { .control = NULL }; @@ -191,7 +191,7 @@ __maybe_unused static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) { struct nand_chip *nand = mtd->priv; - struct nand_bch_priv *bch = nand->priv; + struct omap_nand_info *info = nand->priv; unsigned int dev_width = (nand->options & NAND_BUSWIDTH_16) ? 1 : 0; unsigned int ecc_algo = 0; unsigned int bch_type = 0; @@ -200,7 +200,7 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) u32 ecc_config_val = 0; /* configure GPMC for specific ecc-scheme */ - switch (bch->ecc_scheme) { + switch (info->ecc_scheme) { case OMAP_ECC_HAM1_CODE_SW: return; case OMAP_ECC_HAM1_CODE_HW: @@ -262,11 +262,11 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, uint8_t *ecc_code) { struct nand_chip *chip = mtd->priv; - struct nand_bch_priv *bch = chip->priv; + struct omap_nand_info *info = chip->priv; uint32_t *ptr, val = 0; int8_t i = 0, j; - switch (bch->ecc_scheme) { + switch (info->ecc_scheme) { case OMAP_ECC_HAM1_CODE_HW: val = readl(&gpmc_cfg->ecc1_result); ecc_code[0] = val & 0xFF; @@ -294,7 +294,7 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, return -EINVAL; } /* ECC scheme specific syndrome customizations */ - switch (bch->ecc_scheme) { + switch (info->ecc_scheme) { case OMAP_ECC_HAM1_CODE_HW: break; #ifdef CONFIG_BCH @@ -330,7 +330,7 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, uint8_t *calc_ecc) { struct nand_chip *chip = mtd->priv; - struct nand_bch_priv *bch = chip->priv; + struct omap_nand_info *info = chip->priv; uint32_t eccbytes = chip->ecc.bytes; uint32_t error_count = 0, error_max; uint32_t error_loc[8]; @@ -360,7 +360,7 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, * while reading ECC result we read it in big endian. * Hence while loading to ELM we have rotate to get the right endian. */ - switch (bch->ecc_scheme) { + switch (info->ecc_scheme) { case OMAP_ECC_BCH8_CODE_HW: bch_type = BCH_8_BIT; omap_reverse_list(calc_ecc, eccbytes - 1); @@ -376,7 +376,7 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, } /* correct bch error */ for (count = 0; count < error_count; count++) { - switch (bch->ecc_scheme) { + switch (info->ecc_scheme) { case OMAP_ECC_BCH8_CODE_HW: /* 14th byte in ECC is reserved to match ROM layout */ error_max = SECTOR_BYTES + (eccbytes - 1); @@ -483,10 +483,10 @@ static int omap_correct_data_bch_sw(struct mtd_info *mtd, u_char *data, /* cannot correct more than 8 errors */ unsigned int errloc[8]; struct nand_chip *chip = mtd->priv; - struct nand_bch_priv *chip_priv = chip->priv; - struct bch_control *bch = chip_priv->control; + struct omap_nand_info *info = chip->priv; - count = decode_bch(bch, NULL, 512, read_ecc, calc_ecc, NULL, errloc); + count = decode_bch(info->control, NULL, 512, read_ecc, calc_ecc, + NULL, errloc); if (count > 0) { /* correct errors */ for (i = 0; i < count; i++) { @@ -522,15 +522,11 @@ static int omap_correct_data_bch_sw(struct mtd_info *mtd, u_char *data, static void __maybe_unused omap_free_bch(struct mtd_info *mtd) { struct nand_chip *chip = mtd->priv; - struct nand_bch_priv *chip_priv = chip->priv; - struct bch_control *bch = NULL; + struct omap_nand_info *info = chip->priv; - if (chip_priv) - bch = chip_priv->control; - - if (bch) { - free_bch(bch); - chip_priv->control = NULL; + if (info->control) { + free_bch(info->control); + info->control = NULL; } } #endif /* CONFIG_BCH */ @@ -544,7 +540,7 @@ static void __maybe_unused omap_free_bch(struct mtd_info *mtd) */ static int omap_select_ecc_scheme(struct nand_chip *nand, enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) { - struct nand_bch_priv *bch = nand->priv; + struct omap_nand_info *info = nand->priv; struct nand_ecclayout *ecclayout = &omap_ecclayout; int eccsteps = pagesize / SECTOR_BYTES; int i; @@ -554,11 +550,10 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, debug("nand: selected OMAP_ECC_HAM1_CODE_SW\n"); /* For this ecc-scheme, ecc.bytes, ecc.layout, ... are * initialized in nand_scan_tail(), so just set ecc.mode */ - bch_priv.control = NULL; + info->control = NULL; nand->ecc.mode = NAND_ECC_SOFT; nand->ecc.layout = NULL; nand->ecc.size = 0; - bch->ecc_scheme = OMAP_ECC_HAM1_CODE_SW; break; case OMAP_ECC_HAM1_CODE_HW: @@ -569,7 +564,7 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, (3 * eccsteps) + BADBLOCK_MARKER_LENGTH)); return -EINVAL; } - bch_priv.control = NULL; + info->control = NULL; /* populate ecc specific fields */ memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl)); nand->ecc.mode = NAND_ECC_HW; @@ -590,7 +585,6 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH; ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes - BADBLOCK_MARKER_LENGTH; - bch->ecc_scheme = OMAP_ECC_HAM1_CODE_HW; break; case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: @@ -603,8 +597,8 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, return -EINVAL; } /* check if BCH S/W library can be used for error detection */ - bch_priv.control = init_bch(13, 8, 0x201b); - if (!bch_priv.control) { + info->control = init_bch(13, 8, 0x201b); + if (!info->control) { printf("nand: error: could not init_bch()\n"); return -ENODEV; } @@ -631,7 +625,6 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH; ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes - BADBLOCK_MARKER_LENGTH; - bch->ecc_scheme = OMAP_ECC_BCH8_CODE_HW_DETECTION_SW; break; #else printf("nand: error: CONFIG_BCH required for ECC\n"); @@ -649,6 +642,7 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, } /* intialize ELM for ECC error detection */ elm_init(); + info->control = NULL; /* populate ecc specific fields */ memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl)); nand->ecc.mode = NAND_ECC_HW; @@ -666,7 +660,6 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH; ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes - BADBLOCK_MARKER_LENGTH; - bch->ecc_scheme = OMAP_ECC_BCH8_CODE_HW; break; #else printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n"); @@ -682,6 +675,7 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, if (ecc_scheme != OMAP_ECC_HAM1_CODE_SW) nand->ecc.layout = ecclayout; + info->ecc_scheme = ecc_scheme; return 0; } @@ -785,7 +779,7 @@ int board_nand_init(struct nand_chip *nand) nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat; nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd; - nand->priv = &bch_priv; + nand->priv = &omap_nand_info; nand->cmd_ctrl = omap_nand_hwcontrol; nand->options |= NAND_NO_PADDING | NAND_CACHEPRG; /* If we are 16 bit dev, our gpmc config tells us that */ -- cgit v1.1 From a09431da381ce8d1b4d48e1cbca5f2b4eea662f4 Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Fri, 11 Apr 2014 12:55:34 +0530 Subject: mtd: nand: omap_gpmc: minor cleanup of omap_correct_data_bch This patch tries to avoid some local pointer dereferences, by using common local variables in omap_correct_data_bch() Signed-off-by: Pekon Gupta Reviewed-by: Stefan Roese --- drivers/mtd/nand/omap_gpmc.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index 391a268..2d893e1 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -331,7 +331,7 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, { struct nand_chip *chip = mtd->priv; struct omap_nand_info *info = chip->priv; - uint32_t eccbytes = chip->ecc.bytes; + struct nand_ecc_ctrl *ecc = &chip->ecc; uint32_t error_count = 0, error_max; uint32_t error_loc[8]; enum bch_level bch_type; @@ -340,7 +340,7 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, uint32_t byte_pos, bit_pos; /* check calculated ecc */ - for (i = 0; i < chip->ecc.bytes && !ecc_flag; i++) { + for (i = 0; i < ecc->bytes && !ecc_flag; i++) { if (calc_ecc[i] != 0x00) ecc_flag = 1; } @@ -349,7 +349,7 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, /* check for whether its a erased-page */ ecc_flag = 0; - for (i = 0; i < chip->ecc.bytes && !ecc_flag; i++) { + for (i = 0; i < ecc->bytes && !ecc_flag; i++) { if (read_ecc[i] != 0xff) ecc_flag = 1; } @@ -363,7 +363,7 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, switch (info->ecc_scheme) { case OMAP_ECC_BCH8_CODE_HW: bch_type = BCH_8_BIT; - omap_reverse_list(calc_ecc, eccbytes - 1); + omap_reverse_list(calc_ecc, ecc->bytes - 1); break; default: return -EINVAL; @@ -379,7 +379,7 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, switch (info->ecc_scheme) { case OMAP_ECC_BCH8_CODE_HW: /* 14th byte in ECC is reserved to match ROM layout */ - error_max = SECTOR_BYTES + (eccbytes - 1); + error_max = SECTOR_BYTES + (ecc->bytes - 1); break; default: return -EINVAL; -- cgit v1.1 From 3f990dc83bc3197b17bd847241671917826152cc Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Fri, 11 Apr 2014 12:55:35 +0530 Subject: mtd: nand: omap: fix error-codes returned from omap-elm driver This patch omap-elm.c: replaces -ve integer value returned during errorneous condition, with proper error-codes. omap-gpmc.c: updates omap-gpmc driver to pass error-codes returned from omap-elm driver to upper layers Signed-off-by: Pekon Gupta Reviewed-by: Stefan Roese --- drivers/mtd/nand/omap_elm.c | 7 +++++-- drivers/mtd/nand/omap_gpmc.c | 8 ++++---- 2 files changed, 9 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/omap_elm.c b/drivers/mtd/nand/omap_elm.c index afa629a..d963e6c 100644 --- a/drivers/mtd/nand/omap_elm.c +++ b/drivers/mtd/nand/omap_elm.c @@ -19,6 +19,7 @@ #include #include +#define DRIVER_NAME "omap-elm" #define ELM_DEFAULT_POLY (0) struct elm *elm_cfg; @@ -113,8 +114,10 @@ int elm_check_error(u8 *syndrome, enum bch_level bch_type, u32 *error_count, /* check if correctable */ location_status = readl(&elm_cfg->error_location[poly].location_status); - if (!(location_status & ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK)) - return -1; + if (!(location_status & ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK)) { + printf("%s: uncorrectable ECC errors\n", DRIVER_NAME); + return -EBADMSG; + } /* get error count */ *error_count = readl(&elm_cfg->error_location[poly].location_status) & diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index 2d893e1..d2fedf9 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -370,10 +370,10 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, } /* use elm module to check for errors */ elm_config(bch_type); - if (elm_check_error(calc_ecc, bch_type, &error_count, error_loc)) { - printf("nand: error: uncorrectable ECC errors\n"); - return -EINVAL; - } + err = elm_check_error(calc_ecc, bch_type, &error_count, error_loc); + if (err) + return err; + /* correct bch error */ for (count = 0; count < error_count; count++) { switch (info->ecc_scheme) { -- cgit v1.1 From b9ae609fdbb7f8149a13bb9c67006b7237cbf83e Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Tue, 6 May 2014 00:46:16 +0530 Subject: mtd: nand: don't use read_buf for 8-bit ONFI transfers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Porting below commit from linux-tree, preserving original authorship & commit log commit bd9c6e99b58255b9de1982711ac9487c9a2f18be Author: Brian Norris mtd: nand: don't use read_buf for 8-bit ONFI transfers Use a repeated read_byte() instead of read_buf(), since for x16 buswidth devices, we need to avoid the upper I/O[16:9] bits. See the following commit for reference: commit 05f7835975dad6b3b517f9e23415985e648fb875 (from linux-tree) Author: Uwe Kleine-König Date: Thu Dec 5 22:22:04 2013 +0100 mtd: nand: don't use {read,write}_buf for 8-bit transfers Now, I think that all barriers to probing ONFI on x16 devices are removed, so remove the check from nand_flash_detect_onfi(). Signed-off-by: Pekon Gupta --- drivers/mtd/nand/nand_base.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 1ce55fd..5d3232c 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2582,7 +2582,7 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, int *busw) { struct nand_onfi_params *p = &chip->onfi_params; - int i; + int i, j; int val; /* Try ONFI for unknown chip or LP */ @@ -2593,7 +2593,8 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); for (i = 0; i < 3; i++) { - chip->read_buf(mtd, (uint8_t *)p, sizeof(*p)); + for (j = 0; j < sizeof(*p); j++) + ((uint8_t *)p)[j] = chip->read_byte(mtd); if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) == le16_to_cpu(p->crc)) { pr_info("ONFI param page %d valid\n", i); -- cgit v1.1 From 27ce9e4290b168a1241699d411678959aaf9649b Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Tue, 6 May 2014 00:46:17 +0530 Subject: mtd: nand: force NAND_CMD_READID onto 8-bit bus As per following Sections in ONFI Spec, NAND_CMD_READID should use only lower 8-bit for transfering command, address and data even on x16 NAND device. *Section: Target Initialization" "The Read ID and Read Parameter Page commands only use the lower 8-bits of the data bus. The host shall not issue commands that use a word data width on x16 devices until the host determines the device supports a 16-bit data bus width in the parameter page." *Section: Bus Width Requirements* "When the host supports a 16-bit bus width, only data is transferred at the 16-bit width. All address and command line transfers shall use only the lower 8-bits of the data bus. During command transfers, the host may place any value on the upper 8-bits of the data bus. During address transfers, the host shall set the upper 8-bits of the data bus to 00h." Thus porting following commit from linux-kernel to ensure that column address is not altered to align to x16 bus when issuing NAND_CMD_READID command. commit 3dad2344e92c6e1aeae42df1c4824f307c51bcc7 mtd: nand: force NAND_CMD_READID onto 8-bit bus Author: Brian Norris (preserving authorship) The NAND command helpers tend to automatically shift the column address for x16 bus devices, since most commands expect a word address, not a byte address. The Read ID command, however, expects an 8-bit address (i.e., 0x00, 0x20, or 0x40 should not be translated to 0x00, 0x10, or 0x20). This fixes the column address for a few drivers which imitate the nand_base defaults. Signed-off-by: Pekon Gupta --- drivers/mtd/nand/am335x_spl_bch.c | 2 +- drivers/mtd/nand/atmel_nand.c | 2 +- drivers/mtd/nand/nand_base.c | 6 ++++-- drivers/mtd/nand/nand_spl_simple.c | 2 +- 4 files changed, 7 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/am335x_spl_bch.c b/drivers/mtd/nand/am335x_spl_bch.c index bd89b06..ce65d8e 100644 --- a/drivers/mtd/nand/am335x_spl_bch.c +++ b/drivers/mtd/nand/am335x_spl_bch.c @@ -55,7 +55,7 @@ static int nand_command(int block, int page, uint32_t offs, } /* Shift the offset from byte addressing to word addressing. */ - if (this->options & NAND_BUSWIDTH_16) + if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd)) offs >>= 1; /* Set ALE and clear CLE to start address cycle */ diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index e1fc48f..e73834d 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -1195,7 +1195,7 @@ static int nand_command(int block, int page, uint32_t offs, u8 cmd) hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE); - if (this->options & NAND_BUSWIDTH_16) + if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd)) offs >>= 1; hwctrl(&mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE); diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 5d3232c..376976d 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -575,7 +575,8 @@ static void nand_command(struct mtd_info *mtd, unsigned int command, /* Serially input address */ if (column != -1) { /* Adjust columns for 16 bit buswidth */ - if (chip->options & NAND_BUSWIDTH_16) + if ((chip->options & NAND_BUSWIDTH_16) && + !nand_opcode_8bits(command)) column >>= 1; chip->cmd_ctrl(mtd, column, ctrl); ctrl &= ~NAND_CTRL_CHANGE; @@ -668,7 +669,8 @@ static void nand_command_lp(struct mtd_info *mtd, unsigned int command, /* Serially input address */ if (column != -1) { /* Adjust columns for 16 bit buswidth */ - if (chip->options & NAND_BUSWIDTH_16) + if ((chip->options & NAND_BUSWIDTH_16) && + !nand_opcode_8bits(command)) column >>= 1; chip->cmd_ctrl(mtd, column, ctrl); ctrl &= ~NAND_CTRL_CHANGE; diff --git a/drivers/mtd/nand/nand_spl_simple.c b/drivers/mtd/nand/nand_spl_simple.c index cead4b5..700ca32 100644 --- a/drivers/mtd/nand/nand_spl_simple.c +++ b/drivers/mtd/nand/nand_spl_simple.c @@ -78,7 +78,7 @@ static int nand_command(int block, int page, uint32_t offs, } /* Shift the offset from byte addressing to word addressing. */ - if (this->options & NAND_BUSWIDTH_16) + if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd)) offs >>= 1; /* Begin command latch cycle */ -- cgit v1.1 From b80a66033856cc89c62886ae3e5ba54a7faf31ae Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Tue, 6 May 2014 00:46:19 +0530 Subject: mtd: nand: omap: add CONFIG_SYS_NAND_BUSWIDTH_16BIT to indicate NAND device bus-width GPMC controller needs to be configured based on bus-width of the NAND device connected to it. Also, dynamic detection of NAND bus-width from on-chip ONFI parameters is not possible in following situations: SPL: SPL NAND drivers does not support ONFI parameter reading. U-boot: GPMC controller iniitalization is done in omap_gpmc.c:board_nand_init() which is called before probing for devices, hence any ONFI parameter information is not available during GPMC initialization. Thus, OMAP NAND driver expected board developers to explicitely write GPMC configurations specific to NAND device attached on board in board files itself. But this was troublesome for board manufacturers as they need to dive into lengthy platform & SoC documents to find details of GPMC registers and appropriate configurations to get NAND device working. This patch instead adds existing CONFIG_SYS_NAND_BUSWIDTH_16BIT to board config hich indicates that connected NAND device has x16 bus-width. And then based on this config GPMC driver itself initializes itself based on NAND bus-width. This keeps board developers free from knowing GPMC controller specific internals. Signed-off-by: Pekon Gupta --- drivers/mtd/nand/omap_gpmc.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index d2fedf9..cdfa6bc 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -782,13 +782,18 @@ int board_nand_init(struct nand_chip *nand) nand->priv = &omap_nand_info; nand->cmd_ctrl = omap_nand_hwcontrol; nand->options |= NAND_NO_PADDING | NAND_CACHEPRG; - /* If we are 16 bit dev, our gpmc config tells us that */ - if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000) - nand->options |= NAND_BUSWIDTH_16; - nand->chip_delay = 100; nand->ecc.layout = &omap_ecclayout; + /* configure driver and controller based on NAND device bus-width */ + gpmc_config = readl(&gpmc_cfg->cs[cs].config1); +#if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT) + nand->options |= NAND_BUSWIDTH_16; + writel(gpmc_config | (0x1 << 12), &gpmc_cfg->cs[cs].config1); +#else + nand->options &= ~NAND_BUSWIDTH_16; + writel(gpmc_config & ~(0x1 << 12), &gpmc_cfg->cs[cs].config1); +#endif /* select ECC scheme */ #if defined(CONFIG_NAND_OMAP_ECCSCHEME) err = omap_select_ecc_scheme(nand, CONFIG_NAND_OMAP_ECCSCHEME, -- cgit v1.1 From 46840f66caf564866d191886d2bd86742f982010 Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Mon, 2 Jun 2014 17:14:42 +0530 Subject: mtd: nand: omap: add support for BCH16_ECC - NAND driver updates This patch add support for BCH16_ECC to omap_gpmc driver. *need to BCH16 ECC scheme* With newer SLC Flash technologies and MLC NAND, and large densities, pagesizes Flash devices have become more suspectible to bit-flips. Thus stronger ECC schemes are required for protecting the data. But stronger ECC schemes have come with larger-sized ECC syndromes which require more space in OOB/Spare. This puts constrains like; (a) BCH16_ECC can correct 16 bit-flips per 512Bytes of data. (b) BCH16_ECC generates 26-bytes of ECC syndrome / 512B. Due to (b) this scheme can only be used with NAND devices which have enough OOB to satisfy following equation: OOBsize per page >= 26 * (page-size / 512) Signed-off-by: Pekon Gupta --- drivers/mtd/nand/omap_gpmc.c | 79 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 78 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index cdfa6bc..1acf06b 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -224,6 +224,19 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) eccsize1 = 2; /* non-ECC bits in nibbles per sector */ } break; + case OMAP_ECC_BCH16_CODE_HW: + ecc_algo = 0x1; + bch_type = 0x2; + if (mode == NAND_ECC_WRITE) { + bch_wrapmode = 0x01; + eccsize0 = 0; /* extra bits in nibbles per sector */ + eccsize1 = 52; /* OOB bits in nibbles per sector */ + } else { + bch_wrapmode = 0x01; + eccsize0 = 52; /* ECC bits in nibbles per sector */ + eccsize1 = 0; /* non-ECC bits in nibbles per sector */ + } + break; default: return; } @@ -290,6 +303,29 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, ptr--; } break; + case OMAP_ECC_BCH16_CODE_HW: + val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[2]); + ecc_code[i++] = (val >> 8) & 0xFF; + ecc_code[i++] = (val >> 0) & 0xFF; + val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[1]); + ecc_code[i++] = (val >> 24) & 0xFF; + ecc_code[i++] = (val >> 16) & 0xFF; + ecc_code[i++] = (val >> 8) & 0xFF; + ecc_code[i++] = (val >> 0) & 0xFF; + val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[0]); + ecc_code[i++] = (val >> 24) & 0xFF; + ecc_code[i++] = (val >> 16) & 0xFF; + ecc_code[i++] = (val >> 8) & 0xFF; + ecc_code[i++] = (val >> 0) & 0xFF; + for (j = 3; j >= 0; j--) { + val = readl(&gpmc_cfg->bch_result_0_3[0].bch_result_x[j] + ); + ecc_code[i++] = (val >> 24) & 0xFF; + ecc_code[i++] = (val >> 16) & 0xFF; + ecc_code[i++] = (val >> 8) & 0xFF; + ecc_code[i++] = (val >> 0) & 0xFF; + } + break; default: return -EINVAL; } @@ -308,6 +344,8 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, case OMAP_ECC_BCH8_CODE_HW: ecc_code[chip->ecc.bytes - 1] = 0x00; break; + case OMAP_ECC_BCH16_CODE_HW: + break; default: return -EINVAL; } @@ -333,7 +371,7 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, struct omap_nand_info *info = chip->priv; struct nand_ecc_ctrl *ecc = &chip->ecc; uint32_t error_count = 0, error_max; - uint32_t error_loc[8]; + uint32_t error_loc[ELM_MAX_ERROR_COUNT]; enum bch_level bch_type; uint32_t i, ecc_flag = 0; uint8_t count, err = 0; @@ -365,6 +403,10 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, bch_type = BCH_8_BIT; omap_reverse_list(calc_ecc, ecc->bytes - 1); break; + case OMAP_ECC_BCH16_CODE_HW: + bch_type = BCH_16_BIT; + omap_reverse_list(calc_ecc, ecc->bytes); + break; default: return -EINVAL; } @@ -381,6 +423,9 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, /* 14th byte in ECC is reserved to match ROM layout */ error_max = SECTOR_BYTES + (ecc->bytes - 1); break; + case OMAP_ECC_BCH16_CODE_HW: + error_max = SECTOR_BYTES + ecc->bytes; + break; default: return -EINVAL; } @@ -666,6 +711,38 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, return -EINVAL; #endif + case OMAP_ECC_BCH16_CODE_HW: +#ifdef CONFIG_NAND_OMAP_ELM + debug("nand: using OMAP_ECC_BCH16_CODE_HW\n"); + /* check ecc-scheme requirements before updating ecc info */ + if ((26 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) { + printf("nand: error: insufficient OOB: require=%d\n", ( + (26 * eccsteps) + BADBLOCK_MARKER_LENGTH)); + return -EINVAL; + } + /* intialize ELM for ECC error detection */ + elm_init(); + /* populate ecc specific fields */ + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.size = SECTOR_BYTES; + nand->ecc.bytes = 26; + nand->ecc.strength = 16; + nand->ecc.hwctl = omap_enable_hwecc; + nand->ecc.correct = omap_correct_data_bch; + nand->ecc.calculate = omap_calculate_ecc; + nand->ecc.read_page = omap_read_page_bch; + /* define ecc-layout */ + ecclayout->eccbytes = nand->ecc.bytes * eccsteps; + for (i = 0; i < ecclayout->eccbytes; i++) + ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH; + ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH; + ecclayout->oobfree[0].length = oobsize - nand->ecc.bytes - + BADBLOCK_MARKER_LENGTH; + break; +#else + printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n"); + return -EINVAL; +#endif default: debug("nand: error: ecc scheme not enabled or supported\n"); return -EINVAL; -- cgit v1.1 From ce3cc8ecf52f798cc980a2c49bdc5cbca6b3be29 Mon Sep 17 00:00:00 2001 From: Sourav Poddar Date: Mon, 19 May 2014 16:53:38 -0400 Subject: ti: qspi: populate slave device to set flash quad bit. The patch populates the slave data which will be used by flash driver to set the flash quad enable bit. Signed-off-by: Sourav Poddar --- drivers/spi/ti_qspi.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index c5d2245..fd7fea8 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -106,6 +106,7 @@ static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave) slave->memory_map = (void *)MMAP_START_ADDR_DRA; #else slave->memory_map = (void *)MMAP_START_ADDR_AM43x; + slave->op_mode_rx = 8; #endif memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES | -- cgit v1.1 From 86db550b3864bcb3c9567fbdb67b49a244f5263e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 5 Jun 2014 11:15:29 -0400 Subject: power: Add support for the TPS65218 PMIC Add a driver for the TPS65218 PMIC which is used by TI AM43xx SoCs and may be used by TI AM335x SoCs. Signed-off-by: Tom Rini --- drivers/power/pmic/Makefile | 1 + drivers/power/pmic/pmic_tps65218.c | 97 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 98 insertions(+) create mode 100644 drivers/power/pmic/pmic_tps65218.c (limited to 'drivers') diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index 9a8bfe0..a472f61 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -13,4 +13,5 @@ obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o obj-$(CONFIG_POWER_TPS65090) += pmic_tps65090.o obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o +obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o diff --git a/drivers/power/pmic/pmic_tps65218.c b/drivers/power/pmic/pmic_tps65218.c new file mode 100644 index 0000000..0952456 --- /dev/null +++ b/drivers/power/pmic/pmic_tps65218.c @@ -0,0 +1,97 @@ +/* + * (C) Copyright 2011-2013 + * Texas Instruments, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +/** + * tps65218_reg_write() - Generic function that can write a TPS65218 PMIC + * register or bit field regardless of protection + * level. + * + * @prot_level: Register password protection. Use + * TPS65218_PROT_LEVEL_NONE, + * TPS65218_PROT_LEVEL_1 or TPS65218_PROT_LEVEL_2 + * @dest_reg: Register address to write. + * @dest_val: Value to write. + * @mask: Bit mask (8 bits) to be applied. Function will only + * change bits that are set in the bit mask. + * + * @return: 0 for success, not 0 on failure, as per the i2c API + */ +int tps65218_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val, + uchar mask) +{ + uchar read_val; + uchar xor_reg; + int ret; + + /* + * If we are affecting only a bit field, read dest_reg and apply the + * mask + */ + if (mask != TPS65218_MASK_ALL_BITS) { + ret = i2c_read(TPS65218_CHIP_PM, dest_reg, 1, &read_val, 1); + if (ret) + return ret; + read_val &= (~mask); + read_val |= (dest_val & mask); + dest_val = read_val; + } + + if (prot_level > 0) { + xor_reg = dest_reg ^ TPS65218_PASSWORD_UNLOCK; + ret = i2c_write(TPS65218_CHIP_PM, TPS65218_PASSWORD, 1, + &xor_reg, 1); + if (ret) + return ret; + } + + ret = i2c_write(TPS65218_CHIP_PM, dest_reg, 1, &dest_val, 1); + if (ret) + return ret; + + if (prot_level == TPS65218_PROT_LEVEL_2) { + ret = i2c_write(TPS65218_CHIP_PM, TPS65218_PASSWORD, 1, + &xor_reg, 1); + if (ret) + return ret; + + ret = i2c_write(TPS65218_CHIP_PM, dest_reg, 1, &dest_val, 1); + if (ret) + return ret; + } + + return 0; +} + +/** + * tps65218_voltage_update() - Function to change a voltage level, as this + * is a multi-step process. + * @dc_cntrl_reg: DC voltage control register to change. + * @volt_sel: New value for the voltage register + * @return: 0 for success, not 0 on failure. + */ +int tps65218_voltage_update(uchar dc_cntrl_reg, uchar volt_sel) +{ + if ((dc_cntrl_reg != TPS65218_DCDC1) && + (dc_cntrl_reg != TPS65218_DCDC2)) + return 1; + + /* set voltage level */ + if (tps65218_reg_write(TPS65218_PROT_LEVEL_2, dc_cntrl_reg, volt_sel, + TPS65218_MASK_ALL_BITS)) + return 1; + + /* set GO bit to initiate voltage transition */ + if (tps65218_reg_write(TPS65218_PROT_LEVEL_2, TPS65218_SLEW, + TPS65218_DCDC_GO, TPS65218_DCDC_GO)) + return 1; + + return 0; +} -- cgit v1.1