From ce47eb402c5e29a025399dc282246414fc492940 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Tue, 16 Sep 2008 10:04:47 -0500 Subject: Support for multiple SGMII/TBI interfaces for TSEC ethernet Fix TBI PHY accesses to use the proper offset in CPU register space. The previous code would incorrectly access the TBI PHY by reading/writing to CPU register space at the same location as would be used to access external PHYs. Signed-off-by: Peter Tyser Acked-by: Andy Fleming --- drivers/net/tsec.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index f81211a..8ab6d07 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -283,11 +283,13 @@ uint tsec_local_mdio_read(volatile tsec_t *phyregs, uint phyid, uint regnum) /* Configure the TBI for SGMII operation */ static void tsec_configure_serdes(struct tsec_private *priv) { - tsec_local_mdio_write(priv->phyregs, CFG_TBIPA_VALUE, TBI_ANA, + /* Access TBI PHY registers at given TSEC register offset as opposed to the + * register offset used for external PHY accesses */ + tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_ANA, TBIANA_SETTINGS); - tsec_local_mdio_write(priv->phyregs, CFG_TBIPA_VALUE, TBI_TBICON, + tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_TBICON, TBICON_CLK_SELECT); - tsec_local_mdio_write(priv->phyregs, CFG_TBIPA_VALUE, TBI_CR, + tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_CR, TBICR_SETTINGS); } -- cgit v1.1 From a03c09c5fdb8430fe2ae6a03f88a0cf7bcc0aa57 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Wed, 17 Sep 2008 11:45:26 +0900 Subject: sh: Fix typo in SH serial driver Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- drivers/serial/serial_sh.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index 61c2b82..f30532b 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -76,7 +76,7 @@ # define FIFOLEVEL_MASK 0xFF # endif #elif defined(CONFIG_CPU_SH7723) -# if defined(CONIFG_SCIF_A) +# if defined(CONFIG_SCIF_A) # define SCLSR SCFSR # define LSR_ORER 0x0200 # define FIFOLEVEL_MASK 0x3F -- cgit v1.1 From b5d10a13525c07ec6374adf840d7c87553b5f189 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 18 Sep 2008 19:34:36 +0900 Subject: sh: Fix compile warning Signed-off-by: Nobuhiro Iwamatsu --- drivers/pci/pci_sh7751.c | 24 ++++++++++++++---------- drivers/pci/pci_sh7780.c | 15 ++++++++------- 2 files changed, 22 insertions(+), 17 deletions(-) (limited to 'drivers') diff --git a/drivers/pci/pci_sh7751.c b/drivers/pci/pci_sh7751.c index a058e1d..e3a0ea0 100644 --- a/drivers/pci/pci_sh7751.c +++ b/drivers/pci/pci_sh7751.c @@ -23,18 +23,19 @@ */ #include +#include #include #include -#include +#include /* Register addresses and such */ #define SH7751_BCR1 (vu_long *)0xFF800000 -#define SH7751_BCR2 (vu_short*)0xFF800004 +#define SH7751_BCR2 (vu_short *)0xFF800004 #define SH7751_WCR1 (vu_long *)0xFF800008 #define SH7751_WCR2 (vu_long *)0xFF80000C #define SH7751_WCR3 (vu_long *)0xFF800010 #define SH7751_MCR (vu_long *)0xFF800014 -#define SH7751_BCR3 (vu_short*)0xFF800050 +#define SH7751_BCR3 (vu_short *)0xFF800050 #define SH7751_PCICONF0 (vu_long *)0xFE200000 #define SH7751_PCICONF1 (vu_long *)0xFE200004 #define SH7751_PCICONF2 (vu_long *)0xFE200008 @@ -87,12 +88,12 @@ #define SH7751_PCIPAR (vu_long *)0xFE2001C0 #define SH7751_PCIPDR (vu_long *)0xFE200220 -#define p4_in(addr) *(addr) -#define p4_out(data,addr) *(addr) = (data) +#define p4_in(addr) (*addr) +#define p4_out(data, addr) (*addr) = (data) /* Double word */ int pci_sh4_read_config_dword(struct pci_controller *hose, - pci_dev_t dev, int offset, u32 * value) + pci_dev_t dev, int offset, u32 *value) { u32 par_data = 0x80000000 | dev; @@ -103,7 +104,7 @@ int pci_sh4_read_config_dword(struct pci_controller *hose, } int pci_sh4_write_config_dword(struct pci_controller *hose, - pci_dev_t dev, int offset, u32 * value) + pci_dev_t dev, int offset, u32 value) { u32 par_data = 0x80000000 | dev; @@ -126,15 +127,18 @@ int pci_sh7751_init(struct pci_controller *hose) /* Double-check some BSC config settings */ /* (Area 3 non-MPX 32-bit, PCI bus pins) */ if ((p4_in(SH7751_BCR1) & 0x20008) == 0x20000) { - printf("SH7751_BCR1 0x%08X\n", p4_in(SH7751_BCR1)); + printf("SH7751_BCR1 value is wrong(0x%08X)\n", + (unsigned int)p4_in(SH7751_BCR1)); return 2; } if ((p4_in(SH7751_BCR2) & 0xC0) != 0xC0) { - printf("SH7751_BCR2 0x%08X\n", p4_in(SH7751_BCR2)); + printf("SH7751_BCR2 value is wrong(0x%08X)\n", + (unsigned int)p4_in(SH7751_BCR2)); return 3; } if (p4_in(SH7751_BCR2) & 0x01) { - printf("SH7751_BCR2 0x%08X\n", p4_in(SH7751_BCR2)); + printf("SH7751_BCR2 value is wrong(0x%08X)\n", + (unsigned int)p4_in(SH7751_BCR2)); return 4; } diff --git a/drivers/pci/pci_sh7780.c b/drivers/pci/pci_sh7780.c index 2d04b4f..7555d96 100644 --- a/drivers/pci/pci_sh7780.c +++ b/drivers/pci/pci_sh7780.c @@ -25,9 +25,10 @@ #include +#include #include +#include #include -#include #define SH7780_VENDOR_ID 0x1912 #define SH7780_DEVICE_ID 0x0002 @@ -41,10 +42,10 @@ #define SH7780_PCICR_PRST 0x00000002 #define SH7780_PCICR_CFIN 0x00000001 -#define p4_in(addr) *((vu_long *)addr) -#define p4_out(data,addr) *(vu_long *)(addr) = (data) -#define p4_inw(addr) *((vu_short *)addr) -#define p4_outw(data,addr) *(vu_short *)(addr) = (data) +#define p4_in(addr) (*(vu_long *)addr) +#define p4_out(data, addr) (*(vu_long *)addr) = (data) +#define p4_inw(addr) (*(vu_short *)addr) +#define p4_outw(data, addr) (*(vu_short *)addr) = (data) int pci_sh4_read_config_dword(struct pci_controller *hose, pci_dev_t dev, int offset, u32 *value) @@ -72,9 +73,9 @@ int pci_sh7780_init(struct pci_controller *hose) p4_out(0x01, SH7780_PCIECR); if (p4_inw(SH7780_PCIVID) != SH7780_VENDOR_ID - && p4_inw(SH7780_PCIDID) != SH7780_DEVICE_ID){ + && p4_inw(SH7780_PCIDID) != SH7780_DEVICE_ID) { printf("PCI: Unknown PCI host bridge.\n"); - return; + return -1; } printf("PCI: SH7780 PCI host bridge found.\n"); -- cgit v1.1 From 2215987e100d2a841ae6d48a7cc9bb83fcf22737 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 2 Oct 2008 01:55:38 -0400 Subject: cfi_flash: do not reset flash when probe fails The CFI flash driver starts at flash_init() which calls down into flash_get_size(). This starts by calling flash_detect_cfi(). If said function fails, flash_get_size() finishes by attempting to reset the flash. Unfortunately, it does this with an info->portwidth set to 0x10 which filters down into flash_make_cmd() and that happily smashes the stack by sticking info->portwidth bytes into a cfiword_t variable that lives on the stack. On a 64bit system you probably won't notice, but killing the last 8 bytes on a 32bit system usually leads to a corrupt return address. Which is what happens on a Blackfin system. Signed-off-by: Mike Frysinger Signed-off-by: Stefan Roese --- drivers/mtd/cfi_flash.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 0d1ee8a..72d063a 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -1932,9 +1932,10 @@ ulong flash_get_size (ulong base, int banknum) /* XXX - Need to test on x8/x16 in parallel. */ info->portwidth >>= 1; } + + flash_write_cmd (info, 0, 0, info->cmd_reset); } - flash_write_cmd (info, 0, 0, info->cmd_reset); return (info->size); } -- cgit v1.1 From 0d01f66d235118515b5086b88f82498bc0695d6a Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Thu, 9 Oct 2008 01:26:36 -0500 Subject: CFI: cfi_flash write fix for AMD legacy The flash_unlock_seq requires a sector for AMD_LEGACY. Fix a retcode check typeo. Signed-off-by: Ed Swarthout Signed-off-by: Stefan Roese --- drivers/mtd/cfi_flash.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 72d063a..7bfdc43 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -681,7 +681,7 @@ static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_EXTENDED: case CFI_CMDSET_INTEL_STANDARD: - if ((retcode == ERR_OK) + if ((retcode != ERR_OK) && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) { retcode = ERR_INVAL; printf ("Flash %s error at address %lx\n", prompt, @@ -777,6 +777,7 @@ static int flash_write_cfiword (flash_info_t * info, ulong dest, { void *dstaddr; int flag; + flash_sect_t sect; dstaddr = map_physmem(dest, info->portwidth, MAP_NOCACHE); @@ -818,8 +819,9 @@ static int flash_write_cfiword (flash_info_t * info, ulong dest, #ifdef CONFIG_FLASH_CFI_LEGACY case CFI_CMDSET_AMD_LEGACY: #endif - flash_unlock_seq (info, 0); - flash_write_cmd (info, 0, info->addr_unlock1, AMD_CMD_WRITE); + sect = find_sector(info, dest); + flash_unlock_seq (info, sect); + flash_write_cmd (info, sect, info->addr_unlock1, AMD_CMD_WRITE); break; } -- cgit v1.1 From 6df0efd5c86ca1689deeb2738b46b7d83ce228ef Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Wed, 8 Oct 2008 23:38:00 -0500 Subject: fsl_pci_init do not scan bus when configured as an end-point Signed-off-by: Ed Swarthout Acked-by: Andy Fleming --- drivers/pci/fsl_pci_init.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index bb2813f..38a16e5 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -168,8 +168,21 @@ fsl_pci_init(struct pci_controller *hose) } #ifndef CONFIG_PCI_NOSCAN - printf (" Scanning PCI bus %02x\n", hose->current_busno); - hose->last_busno = pci_hose_scan_bus(hose,hose->current_busno); + pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &temp8); + + /* Programming Interface (PCI_CLASS_PROG) + * 0 == pci host or pcie root-complex, + * 1 == pci agent or pcie end-point + */ + if (!temp8) { + printf(" Scanning PCI bus %02x\n", + hose->current_busno); + hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno); + } else { + debug(" Not scanning PCI bus %02x. PI=%x\n", + hose->current_busno, temp8); + hose->last_busno = hose->current_busno; + } if ( bridge ) { /* update limit regs and subordinate busno */ pciauto_postscan_setup_bridge(hose, dev, hose->last_busno); -- cgit v1.1 From 702c85b0e876d587c11acdbb55738ee52acd54f4 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 30 Sep 2008 15:02:53 +0900 Subject: net: ne2000: Divided a function of NE2000 driver get_prom function was used __attriute__ , but it is not enable. ax88796.o does not do link besides ne2000.o. When ld is carried out, get_prom function of ax88796.c is ignored. This problem is a thing by specifications of ld. I checked and test this patch on SuperH and MIPS. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Ben Warren --- drivers/net/Makefile | 6 +- drivers/net/ax88796.c | 2 +- drivers/net/ne2000.c | 719 +------------------------------------------ drivers/net/ne2000_base.c | 757 ++++++++++++++++++++++++++++++++++++++++++++++ drivers/net/ne2000_base.h | 36 ++- 5 files changed, 797 insertions(+), 723 deletions(-) create mode 100644 drivers/net/ne2000_base.c (limited to 'drivers') diff --git a/drivers/net/Makefile b/drivers/net/Makefile index a084000..a4ea3a2 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -44,10 +44,8 @@ COBJS-$(CONFIG_MCFFEC) += mcffec.o COBJS-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o COBJS-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o COBJS-$(CONFIG_NATSEMI) += natsemi.o -ifeq ($(CONFIG_DRIVER_NE2000),y) -COBJS-y += ne2000.o -COBJS-$(CONFIG_DRIVER_AX88796L) += ax88796.o -endif +COBJS-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o +COBJS-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o COBJS-$(CONFIG_DRIVER_NETARMETH) += netarm_eth.o COBJS-$(CONFIG_NETCONSOLE) += netconsole.o COBJS-$(CONFIG_DRIVER_NS7520_ETHERNET) += ns7520_eth.o diff --git a/drivers/net/ax88796.c b/drivers/net/ax88796.c index 39cd101..2089141 100644 --- a/drivers/net/ax88796.c +++ b/drivers/net/ax88796.c @@ -143,7 +143,7 @@ static void ax88796_mac_read(u8 *buff) } } -int get_prom(u8* mac_addr) +int get_prom(u8* mac_addr, u8* base_addr) { u8 prom[32]; int i; diff --git a/drivers/net/ne2000.c b/drivers/net/ne2000.c index ec92485..ab5eec7 100644 --- a/drivers/net/ne2000.c +++ b/drivers/net/ne2000.c @@ -74,600 +74,11 @@ Add SNMP #include #include -#include -#include - -#define mdelay(n) udelay((n)*1000) -/* forward definition of function used for the uboot interface */ -void uboot_push_packet_len(int len); -void uboot_push_tx_done(int key, int val); - -/* - * Debugging details - * - * Set to perms of: - * 0 disables all debug output - * 1 for process debug output - * 2 for added data IO output: get_reg, put_reg - * 4 for packet allocation/free output - * 8 for only startup status, so we can tell we're installed OK - */ -#if 0 -#define DEBUG 0xf -#else -#define DEBUG 0 -#endif - -#if DEBUG & 1 -#define DEBUG_FUNCTION() do { printf("%s\n", __FUNCTION__); } while (0) -#define DEBUG_LINE() do { printf("%d\n", __LINE__); } while (0) -#define PRINTK(args...) printf(args) -#else -#define DEBUG_FUNCTION() do {} while(0) -#define DEBUG_LINE() do {} while(0) -#define PRINTK(args...) -#endif /* NE2000 base header file */ #include "ne2000_base.h" -#if defined(CONFIG_DRIVER_AX88796L) -/* AX88796L support */ -#include "ax88796.h" -#else -/* Basic NE2000 chip support */ -#include "ne2000.h" -#endif - -static dp83902a_priv_data_t nic; /* just one instance of the card supported */ - -static bool -dp83902a_init(void) -{ - dp83902a_priv_data_t *dp = &nic; - u8* base; -#if defined(NE2000_BASIC_INIT) - int i; -#endif - - DEBUG_FUNCTION(); - - base = dp->base; - if (!base) - return false; /* No device found */ - - DEBUG_LINE(); - -#if defined(NE2000_BASIC_INIT) - /* AX88796L doesn't need */ - /* Prepare ESA */ - DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1); /* Select page 1 */ - /* Use the address from the serial EEPROM */ - for (i = 0; i < 6; i++) - DP_IN(base, DP_P1_PAR0+i, dp->esa[i]); - DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0); /* Select page 0 */ - - printf("NE2000 - %s ESA: %02x:%02x:%02x:%02x:%02x:%02x\n", - "eeprom", - dp->esa[0], - dp->esa[1], - dp->esa[2], - dp->esa[3], - dp->esa[4], - dp->esa[5] ); - -#endif /* NE2000_BASIC_INIT */ - return true; -} - -static void -dp83902a_stop(void) -{ - dp83902a_priv_data_t *dp = &nic; - u8 *base = dp->base; - - DEBUG_FUNCTION(); - - DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_STOP); /* Brutal */ - DP_OUT(base, DP_ISR, 0xFF); /* Clear any pending interrupts */ - DP_OUT(base, DP_IMR, 0x00); /* Disable all interrupts */ - - dp->running = false; -} - -/* - * This function is called to "start up" the interface. It may be called - * multiple times, even when the hardware is already running. It will be - * called whenever something "hardware oriented" changes and should leave - * the hardware ready to send/receive packets. - */ -static void -dp83902a_start(u8 * enaddr) -{ - dp83902a_priv_data_t *dp = &nic; - u8 *base = dp->base; - int i; - - DEBUG_FUNCTION(); - - DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_STOP); /* Brutal */ - DP_OUT(base, DP_DCR, DP_DCR_INIT); - DP_OUT(base, DP_RBCH, 0); /* Remote byte count */ - DP_OUT(base, DP_RBCL, 0); - DP_OUT(base, DP_RCR, DP_RCR_MON); /* Accept no packets */ - DP_OUT(base, DP_TCR, DP_TCR_LOCAL); /* Transmitter [virtually] off */ - DP_OUT(base, DP_TPSR, dp->tx_buf1); /* Transmitter start page */ - dp->tx1 = dp->tx2 = 0; - dp->tx_next = dp->tx_buf1; - dp->tx_started = false; - dp->running = true; - DP_OUT(base, DP_PSTART, dp->rx_buf_start); /* Receive ring start page */ - DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1); /* Receive ring boundary */ - DP_OUT(base, DP_PSTOP, dp->rx_buf_end); /* Receive ring end page */ - dp->rx_next = dp->rx_buf_start - 1; - dp->running = true; - DP_OUT(base, DP_ISR, 0xFF); /* Clear any pending interrupts */ - DP_OUT(base, DP_IMR, DP_IMR_All); /* Enable all interrupts */ - DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1 | DP_CR_STOP); /* Select page 1 */ - DP_OUT(base, DP_P1_CURP, dp->rx_buf_start); /* Current page - next free page for Rx */ - dp->running = true; - for (i = 0; i < ETHER_ADDR_LEN; i++) { - /* FIXME */ - /*((vu_short*)( base + ((DP_P1_PAR0 + i) * 2) + - * 0x1400)) = enaddr[i];*/ - DP_OUT(base, DP_P1_PAR0+i, enaddr[i]); - } - /* Enable and start device */ - DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START); - DP_OUT(base, DP_TCR, DP_TCR_NORMAL); /* Normal transmit operations */ - DP_OUT(base, DP_RCR, DP_RCR_AB); /* Accept broadcast, no errors, no multicast */ - dp->running = true; -} - -/* - * This routine is called to start the transmitter. It is split out from the - * data handling routine so it may be called either when data becomes first - * available or when an Tx interrupt occurs - */ - -static void -dp83902a_start_xmit(int start_page, int len) -{ - dp83902a_priv_data_t *dp = (dp83902a_priv_data_t *) &nic; - u8 *base = dp->base; - - DEBUG_FUNCTION(); - -#if DEBUG & 1 - printf("Tx pkt %d len %d\n", start_page, len); - if (dp->tx_started) - printf("TX already started?!?\n"); -#endif - - DP_OUT(base, DP_ISR, (DP_ISR_TxP | DP_ISR_TxE)); - DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START); - DP_OUT(base, DP_TBCL, len & 0xFF); - DP_OUT(base, DP_TBCH, len >> 8); - DP_OUT(base, DP_TPSR, start_page); - DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_TXPKT | DP_CR_START); - - dp->tx_started = true; -} - -/* - * This routine is called to send data to the hardware. It is known a-priori - * that there is free buffer space (dp->tx_next). - */ -static void -dp83902a_send(u8 *data, int total_len, u32 key) -{ - struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; - u8 *base = dp->base; - int len, start_page, pkt_len, i, isr; -#if DEBUG & 4 - int dx; -#endif - - DEBUG_FUNCTION(); - - len = pkt_len = total_len; - if (pkt_len < IEEE_8023_MIN_FRAME) - pkt_len = IEEE_8023_MIN_FRAME; - - start_page = dp->tx_next; - if (dp->tx_next == dp->tx_buf1) { - dp->tx1 = start_page; - dp->tx1_len = pkt_len; - dp->tx1_key = key; - dp->tx_next = dp->tx_buf2; - } else { - dp->tx2 = start_page; - dp->tx2_len = pkt_len; - dp->tx2_key = key; - dp->tx_next = dp->tx_buf1; - } - -#if DEBUG & 5 - printf("TX prep page %d len %d\n", start_page, pkt_len); -#endif - - DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */ - { - /* - * Dummy read. The manual sez something slightly different, - * but the code is extended a bit to do what Hitachi's monitor - * does (i.e., also read data). - */ - - u16 tmp; - int len = 1; - - DP_OUT(base, DP_RSAL, 0x100 - len); - DP_OUT(base, DP_RSAH, (start_page - 1) & 0xff); - DP_OUT(base, DP_RBCL, len); - DP_OUT(base, DP_RBCH, 0); - DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_RDMA | DP_CR_START); - DP_IN_DATA(dp->data, tmp); - } - -#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA - /* - * Stall for a bit before continuing to work around random data - * corruption problems on some platforms. - */ - CYGACC_CALL_IF_DELAY_US(1); -#endif - - /* Send data to device buffer(s) */ - DP_OUT(base, DP_RSAL, 0); - DP_OUT(base, DP_RSAH, start_page); - DP_OUT(base, DP_RBCL, pkt_len & 0xFF); - DP_OUT(base, DP_RBCH, pkt_len >> 8); - DP_OUT(base, DP_CR, DP_CR_WDMA | DP_CR_START); - - /* Put data into buffer */ -#if DEBUG & 4 - printf(" sg buf %08lx len %08x\n ", (u32)data, len); - dx = 0; -#endif - while (len > 0) { -#if DEBUG & 4 - printf(" %02x", *data); - if (0 == (++dx % 16)) printf("\n "); -#endif - - DP_OUT_DATA(dp->data, *data++); - len--; - } -#if DEBUG & 4 - printf("\n"); -#endif - if (total_len < pkt_len) { -#if DEBUG & 4 - printf(" + %d bytes of padding\n", pkt_len - total_len); -#endif - /* Padding to 802.3 length was required */ - for (i = total_len; i < pkt_len;) { - i++; - DP_OUT_DATA(dp->data, 0); - } - } - -#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA - /* - * After last data write, delay for a bit before accessing the - * device again, or we may get random data corruption in the last - * datum (on some platforms). - */ - CYGACC_CALL_IF_DELAY_US(1); -#endif - - /* Wait for DMA to complete */ - do { - DP_IN(base, DP_ISR, isr); - } while ((isr & DP_ISR_RDC) == 0); - - /* Then disable DMA */ - DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START); - - /* Start transmit if not already going */ - if (!dp->tx_started) { - if (start_page == dp->tx1) { - dp->tx_int = 1; /* Expecting interrupt from BUF1 */ - } else { - dp->tx_int = 2; /* Expecting interrupt from BUF2 */ - } - dp83902a_start_xmit(start_page, pkt_len); - } -} - -/* - * This function is called when a packet has been received. It's job is - * to prepare to unload the packet from the hardware. Once the length of - * the packet is known, the upper layer of the driver can be told. When - * the upper layer is ready to unload the packet, the internal function - * 'dp83902a_recv' will be called to actually fetch it from the hardware. - */ -static void -dp83902a_RxEvent(void) -{ - struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; - u8 *base = dp->base; - u8 rsr; - u8 rcv_hdr[4]; - int i, len, pkt, cur; - - DEBUG_FUNCTION(); - - DP_IN(base, DP_RSR, rsr); - while (true) { - /* Read incoming packet header */ - DP_OUT(base, DP_CR, DP_CR_PAGE1 | DP_CR_NODMA | DP_CR_START); - DP_IN(base, DP_P1_CURP, cur); - DP_OUT(base, DP_P1_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START); - DP_IN(base, DP_BNDRY, pkt); - - pkt += 1; - if (pkt == dp->rx_buf_end) - pkt = dp->rx_buf_start; - - if (pkt == cur) { - break; - } - DP_OUT(base, DP_RBCL, sizeof(rcv_hdr)); - DP_OUT(base, DP_RBCH, 0); - DP_OUT(base, DP_RSAL, 0); - DP_OUT(base, DP_RSAH, pkt); - if (dp->rx_next == pkt) { - if (cur == dp->rx_buf_start) - DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1); - else - DP_OUT(base, DP_BNDRY, cur - 1); /* Update pointer */ - return; - } - dp->rx_next = pkt; - DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */ - DP_OUT(base, DP_CR, DP_CR_RDMA | DP_CR_START); -#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_RX_DMA - CYGACC_CALL_IF_DELAY_US(10); -#endif - - /* read header (get data size)*/ - for (i = 0; i < sizeof(rcv_hdr);) { - DP_IN_DATA(dp->data, rcv_hdr[i++]); - } - -#if DEBUG & 5 - printf("rx hdr %02x %02x %02x %02x\n", - rcv_hdr[0], rcv_hdr[1], rcv_hdr[2], rcv_hdr[3]); -#endif - len = ((rcv_hdr[3] << 8) | rcv_hdr[2]) - sizeof(rcv_hdr); - - /* data read */ - uboot_push_packet_len(len); - - if (rcv_hdr[1] == dp->rx_buf_start) - DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1); - else - DP_OUT(base, DP_BNDRY, rcv_hdr[1] - 1); /* Update pointer */ - } -} - -/* - * This function is called as a result of the "eth_drv_recv()" call above. - * It's job is to actually fetch data for a packet from the hardware once - * memory buffers have been allocated for the packet. Note that the buffers - * may come in pieces, using a scatter-gather list. This allows for more - * efficient processing in the upper layers of the stack. - */ -static void -dp83902a_recv(u8 *data, int len) -{ - struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; - u8 *base = dp->base; - int i, mlen; - u8 saved_char = 0; - bool saved; -#if DEBUG & 4 - int dx; -#endif - - DEBUG_FUNCTION(); - -#if DEBUG & 5 - printf("Rx packet %d length %d\n", dp->rx_next, len); -#endif - - /* Read incoming packet data */ - DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START); - DP_OUT(base, DP_RBCL, len & 0xFF); - DP_OUT(base, DP_RBCH, len >> 8); - DP_OUT(base, DP_RSAL, 4); /* Past header */ - DP_OUT(base, DP_RSAH, dp->rx_next); - DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */ - DP_OUT(base, DP_CR, DP_CR_RDMA | DP_CR_START); -#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_RX_DMA - CYGACC_CALL_IF_DELAY_US(10); -#endif - - saved = false; - for (i = 0; i < 1; i++) { - if (data) { - mlen = len; -#if DEBUG & 4 - printf(" sg buf %08lx len %08x \n", (u32) data, mlen); - dx = 0; -#endif - while (0 < mlen) { - /* Saved byte from previous loop? */ - if (saved) { - *data++ = saved_char; - mlen--; - saved = false; - continue; - } - - { - u8 tmp; - DP_IN_DATA(dp->data, tmp); -#if DEBUG & 4 - printf(" %02x", tmp); - if (0 == (++dx % 16)) printf("\n "); -#endif - *data++ = tmp;; - mlen--; - } - } -#if DEBUG & 4 - printf("\n"); -#endif - } - } -} - -static void -dp83902a_TxEvent(void) -{ - struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; - u8 *base = dp->base; - u8 tsr; - u32 key; - - DEBUG_FUNCTION(); - - DP_IN(base, DP_TSR, tsr); - if (dp->tx_int == 1) { - key = dp->tx1_key; - dp->tx1 = 0; - } else { - key = dp->tx2_key; - dp->tx2 = 0; - } - /* Start next packet if one is ready */ - dp->tx_started = false; - if (dp->tx1) { - dp83902a_start_xmit(dp->tx1, dp->tx1_len); - dp->tx_int = 1; - } else if (dp->tx2) { - dp83902a_start_xmit(dp->tx2, dp->tx2_len); - dp->tx_int = 2; - } else { - dp->tx_int = 0; - } - /* Tell higher level we sent this packet */ - uboot_push_tx_done(key, 0); -} - -/* - * Read the tally counters to clear them. Called in response to a CNT - * interrupt. - */ -static void -dp83902a_ClearCounters(void) -{ - struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; - u8 *base = dp->base; - u8 cnt1, cnt2, cnt3; - - DP_IN(base, DP_FER, cnt1); - DP_IN(base, DP_CER, cnt2); - DP_IN(base, DP_MISSED, cnt3); - DP_OUT(base, DP_ISR, DP_ISR_CNT); -} - -/* - * Deal with an overflow condition. This code follows the procedure set - * out in section 7.0 of the datasheet. - */ -static void -dp83902a_Overflow(void) -{ - struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *)&nic; - u8 *base = dp->base; - u8 isr; - - /* Issue a stop command and wait 1.6ms for it to complete. */ - DP_OUT(base, DP_CR, DP_CR_STOP | DP_CR_NODMA); - CYGACC_CALL_IF_DELAY_US(1600); - - /* Clear the remote byte counter registers. */ - DP_OUT(base, DP_RBCL, 0); - DP_OUT(base, DP_RBCH, 0); - - /* Enter loopback mode while we clear the buffer. */ - DP_OUT(base, DP_TCR, DP_TCR_LOCAL); - DP_OUT(base, DP_CR, DP_CR_START | DP_CR_NODMA); - - /* - * Read in as many packets as we can and acknowledge any and receive - * interrupts. Since the buffer has overflowed, a receive event of - * some kind will have occured. - */ - dp83902a_RxEvent(); - DP_OUT(base, DP_ISR, DP_ISR_RxP|DP_ISR_RxE); - - /* Clear the overflow condition and leave loopback mode. */ - DP_OUT(base, DP_ISR, DP_ISR_OFLW); - DP_OUT(base, DP_TCR, DP_TCR_NORMAL); - - /* - * If a transmit command was issued, but no transmit event has occured, - * restart it here. - */ - DP_IN(base, DP_ISR, isr); - if (dp->tx_started && !(isr & (DP_ISR_TxP|DP_ISR_TxE))) { - DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_TXPKT | DP_CR_START); - } -} - -static void -dp83902a_poll(void) -{ - struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; - u8 *base = dp->base; - u8 isr; - - DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0 | DP_CR_START); - DP_IN(base, DP_ISR, isr); - while (0 != isr) { - /* - * The CNT interrupt triggers when the MSB of one of the error - * counters is set. We don't much care about these counters, but - * we should read their values to reset them. - */ - if (isr & DP_ISR_CNT) { - dp83902a_ClearCounters(); - } - /* - * Check for overflow. It's a special case, since there's a - * particular procedure that must be followed to get back into - * a running state.a - */ - if (isr & DP_ISR_OFLW) { - dp83902a_Overflow(); - } else { - /* - * Other kinds of interrupts can be acknowledged simply by - * clearing the relevant bits of the ISR. Do that now, then - * handle the interrupts we care about. - */ - DP_OUT(base, DP_ISR, isr); /* Clear set bits */ - if (!dp->running) break; /* Is this necessary? */ - /* - * Check for tx_started on TX event since these may happen - * spuriously it seems. - */ - if (isr & (DP_ISR_TxP|DP_ISR_TxE) && dp->tx_started) { - dp83902a_TxEvent(); - } - if (isr & (DP_ISR_RxP|DP_ISR_RxE)) { - dp83902a_RxEvent(); - } - } - DP_IN(base, DP_ISR, isr); - } -} - +#define mdelay(n) udelay((n)*1000) /* find prom (taken from pc_net_cs.c from Linux) */ #include "8390.h" @@ -763,18 +174,16 @@ static hw_info_t hw_info[] = { #define PCNET_RESET 0x1f /* Issue a read to reset, a write to clear. */ #define PCNET_MISC 0x18 /* For IBM CCAE and Socket EA cards */ -static void pcnet_reset_8390(void) +static void pcnet_reset_8390(u8* addr) { int i, r; - PRINTK("nic base is %lx\n", nic.base); - n2k_outb(E8390_NODMA + E8390_PAGE0+E8390_STOP, E8390_CMD); - PRINTK("cmd (at %lx) is %x\n", nic.base + E8390_CMD, n2k_inb(E8390_CMD)); + PRINTK("cmd (at %lx) is %x\n", addr + E8390_CMD, n2k_inb(E8390_CMD)); n2k_outb(E8390_NODMA+E8390_PAGE1+E8390_STOP, E8390_CMD); - PRINTK("cmd (at %lx) is %x\n", nic.base + E8390_CMD, n2k_inb(E8390_CMD)); + PRINTK("cmd (at %lx) is %x\n", addr + E8390_CMD, n2k_inb(E8390_CMD)); n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD); - PRINTK("cmd (at %lx) is %x\n", nic.base + E8390_CMD, n2k_inb(E8390_CMD)); + PRINTK("cmd (at %lx) is %x\n", addr + E8390_CMD, n2k_inb(E8390_CMD)); n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD); n2k_outb(n2k_inb(PCNET_RESET), PCNET_RESET); @@ -791,8 +200,7 @@ static void pcnet_reset_8390(void) printf("pcnet_reset_8390() did not complete.\n"); } /* pcnet_reset_8390 */ -int get_prom(u8* mac_addr) __attribute__ ((weak, alias ("__get_prom"))); -int __get_prom(u8* mac_addr) +int get_prom(u8* mac_addr, u8* base_addr) { u8 prom[32]; int i, j; @@ -816,7 +224,7 @@ int __get_prom(u8* mac_addr) PRINTK ("trying to get MAC via prom reading\n"); - pcnet_reset_8390 (); + pcnet_reset_8390 (base_addr); mdelay (10); @@ -849,116 +257,3 @@ int __get_prom(u8* mac_addr) } return 0; } - -/* U-boot specific routines */ -static u8 *pbuf = NULL; - -static int pkey = -1; -static int initialized = 0; - -void uboot_push_packet_len(int len) { - PRINTK("pushed len = %d\n", len); - if (len >= 2000) { - printf("NE2000: packet too big\n"); - return; - } - dp83902a_recv(&pbuf[0], len); - - /*Just pass it to the upper layer*/ - NetReceive(&pbuf[0], len); -} - -void uboot_push_tx_done(int key, int val) { - PRINTK("pushed key = %d\n", key); - pkey = key; -} - -int eth_init(bd_t *bd) { - int r; - u8 dev_addr[6]; - char ethaddr[20]; - - PRINTK("### eth_init\n"); - - if (!pbuf) { - pbuf = malloc(2000); - if (!pbuf) { - printf("Cannot allocate rx buffer\n"); - return -1; - } - } - -#ifdef CONFIG_DRIVER_NE2000_CCR - { - vu_char *p = (vu_char *) CONFIG_DRIVER_NE2000_CCR; - - PRINTK("CCR before is %x\n", *p); - *p = CONFIG_DRIVER_NE2000_VAL; - PRINTK("CCR after is %x\n", *p); - } -#endif - - nic.base = (u8 *) CONFIG_DRIVER_NE2000_BASE; - - r = get_prom(dev_addr); - if (!r) - return -1; - - sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X", - dev_addr[0], dev_addr[1], - dev_addr[2], dev_addr[3], - dev_addr[4], dev_addr[5]) ; - PRINTK("Set environment from HW MAC addr = \"%s\"\n", ethaddr); - setenv ("ethaddr", ethaddr); - - nic.data = nic.base + DP_DATA; - nic.tx_buf1 = START_PG; - nic.tx_buf2 = START_PG2; - nic.rx_buf_start = RX_START; - nic.rx_buf_end = RX_END; - - if (dp83902a_init() == false) - return -1; - - dp83902a_start(dev_addr); - initialized = 1; - - return 0; -} - -void eth_halt() { - - PRINTK("### eth_halt\n"); - if(initialized) - dp83902a_stop(); - initialized = 0; -} - -int eth_rx() { - dp83902a_poll(); - return 1; -} - -int eth_send(volatile void *packet, int length) { - int tmo; - - PRINTK("### eth_send\n"); - - pkey = -1; - - dp83902a_send((u8 *) packet, length, 666); - tmo = get_timer (0) + TOUT * CFG_HZ; - while(1) { - dp83902a_poll(); - if (pkey != -1) { - PRINTK("Packet sucesfully sent\n"); - return 0; - } - if (get_timer (0) >= tmo) { - printf("transmission error (timoeut)\n"); - return 0; - } - - } - return 0; -} diff --git a/drivers/net/ne2000_base.c b/drivers/net/ne2000_base.c new file mode 100644 index 0000000..4a07708 --- /dev/null +++ b/drivers/net/ne2000_base.c @@ -0,0 +1,757 @@ +/* +Ported to U-Boot by Christian Pellegrin + +Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and +eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world +are GPL, so this is, of course, GPL. + +========================================================================== + +dev/if_dp83902a.c + +Ethernet device driver for NS DP83902a ethernet controller + +========================================================================== +####ECOSGPLCOPYRIGHTBEGIN#### +------------------------------------------- +This file is part of eCos, the Embedded Configurable Operating System. +Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. + +eCos is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 2 or (at your option) any later version. + +eCos is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +You should have received a copy of the GNU General Public License along +with eCos; if not, write to the Free Software Foundation, Inc., +59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + +As a special exception, if other files instantiate templates or use macros +or inline functions from this file, or you compile this file and link it +with other works to produce a work based on this file, this file does not +by itself cause the resulting work to be covered by the GNU General Public +License. However the source code for this file must still be made available +in accordance with section (3) of the GNU General Public License. + +This exception does not invalidate any other reasons why a work based on +this file might be covered by the GNU General Public License. + +Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +at http://sources.redhat.com/ecos/ecos-license/ +------------------------------------------- +####ECOSGPLCOPYRIGHTEND#### +####BSDCOPYRIGHTBEGIN#### + +------------------------------------------- + +Portions of this software may have been derived from OpenBSD or other sources, +and are covered by the appropriate copyright disclaimers included herein. + +------------------------------------------- + +####BSDCOPYRIGHTEND#### +========================================================================== +#####DESCRIPTIONBEGIN#### + +Author(s): gthomas +Contributors: gthomas, jskov, rsandifo +Date: 2001-06-13 +Purpose: +Description: + +FIXME: Will fail if pinged with large packets (1520 bytes) +Add promisc config +Add SNMP + +####DESCRIPTIONEND#### + +========================================================================== +*/ + +#include +#include +#include +#include + +#define mdelay(n) udelay((n)*1000) +/* forward definition of function used for the uboot interface */ +void uboot_push_packet_len(int len); +void uboot_push_tx_done(int key, int val); + +/* NE2000 base header file */ +#include "ne2000_base.h" + +#if defined(CONFIG_DRIVER_AX88796L) +/* AX88796L support */ +#include "ax88796.h" +#else +/* Basic NE2000 chip support */ +#include "ne2000.h" +#endif + +static dp83902a_priv_data_t nic; /* just one instance of the card supported */ + +static bool +dp83902a_init(void) +{ + dp83902a_priv_data_t *dp = &nic; + u8* base; +#if defined(NE2000_BASIC_INIT) + int i; +#endif + + DEBUG_FUNCTION(); + + base = dp->base; + if (!base) + return false; /* No device found */ + + DEBUG_LINE(); + +#if defined(NE2000_BASIC_INIT) + /* AX88796L doesn't need */ + /* Prepare ESA */ + DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1); /* Select page 1 */ + /* Use the address from the serial EEPROM */ + for (i = 0; i < 6; i++) + DP_IN(base, DP_P1_PAR0+i, dp->esa[i]); + DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0); /* Select page 0 */ + + printf("NE2000 - %s ESA: %02x:%02x:%02x:%02x:%02x:%02x\n", + "eeprom", + dp->esa[0], + dp->esa[1], + dp->esa[2], + dp->esa[3], + dp->esa[4], + dp->esa[5] ); + +#endif /* NE2000_BASIC_INIT */ + return true; +} + +static void +dp83902a_stop(void) +{ + dp83902a_priv_data_t *dp = &nic; + u8 *base = dp->base; + + DEBUG_FUNCTION(); + + DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_STOP); /* Brutal */ + DP_OUT(base, DP_ISR, 0xFF); /* Clear any pending interrupts */ + DP_OUT(base, DP_IMR, 0x00); /* Disable all interrupts */ + + dp->running = false; +} + +/* + * This function is called to "start up" the interface. It may be called + * multiple times, even when the hardware is already running. It will be + * called whenever something "hardware oriented" changes and should leave + * the hardware ready to send/receive packets. + */ +static void +dp83902a_start(u8 * enaddr) +{ + dp83902a_priv_data_t *dp = &nic; + u8 *base = dp->base; + int i; + + DEBUG_FUNCTION(); + + DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_STOP); /* Brutal */ + DP_OUT(base, DP_DCR, DP_DCR_INIT); + DP_OUT(base, DP_RBCH, 0); /* Remote byte count */ + DP_OUT(base, DP_RBCL, 0); + DP_OUT(base, DP_RCR, DP_RCR_MON); /* Accept no packets */ + DP_OUT(base, DP_TCR, DP_TCR_LOCAL); /* Transmitter [virtually] off */ + DP_OUT(base, DP_TPSR, dp->tx_buf1); /* Transmitter start page */ + dp->tx1 = dp->tx2 = 0; + dp->tx_next = dp->tx_buf1; + dp->tx_started = false; + dp->running = true; + DP_OUT(base, DP_PSTART, dp->rx_buf_start); /* Receive ring start page */ + DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1); /* Receive ring boundary */ + DP_OUT(base, DP_PSTOP, dp->rx_buf_end); /* Receive ring end page */ + dp->rx_next = dp->rx_buf_start - 1; + dp->running = true; + DP_OUT(base, DP_ISR, 0xFF); /* Clear any pending interrupts */ + DP_OUT(base, DP_IMR, DP_IMR_All); /* Enable all interrupts */ + DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1 | DP_CR_STOP); /* Select page 1 */ + DP_OUT(base, DP_P1_CURP, dp->rx_buf_start); /* Current page - next free page for Rx */ + dp->running = true; + for (i = 0; i < ETHER_ADDR_LEN; i++) { + /* FIXME */ + /*((vu_short*)( base + ((DP_P1_PAR0 + i) * 2) + + * 0x1400)) = enaddr[i];*/ + DP_OUT(base, DP_P1_PAR0+i, enaddr[i]); + } + /* Enable and start device */ + DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START); + DP_OUT(base, DP_TCR, DP_TCR_NORMAL); /* Normal transmit operations */ + DP_OUT(base, DP_RCR, DP_RCR_AB); /* Accept broadcast, no errors, no multicast */ + dp->running = true; +} + +/* + * This routine is called to start the transmitter. It is split out from the + * data handling routine so it may be called either when data becomes first + * available or when an Tx interrupt occurs + */ + +static void +dp83902a_start_xmit(int start_page, int len) +{ + dp83902a_priv_data_t *dp = (dp83902a_priv_data_t *) &nic; + u8 *base = dp->base; + + DEBUG_FUNCTION(); + +#if DEBUG & 1 + printf("Tx pkt %d len %d\n", start_page, len); + if (dp->tx_started) + printf("TX already started?!?\n"); +#endif + + DP_OUT(base, DP_ISR, (DP_ISR_TxP | DP_ISR_TxE)); + DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START); + DP_OUT(base, DP_TBCL, len & 0xFF); + DP_OUT(base, DP_TBCH, len >> 8); + DP_OUT(base, DP_TPSR, start_page); + DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_TXPKT | DP_CR_START); + + dp->tx_started = true; +} + +/* + * This routine is called to send data to the hardware. It is known a-priori + * that there is free buffer space (dp->tx_next). + */ +static void +dp83902a_send(u8 *data, int total_len, u32 key) +{ + struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; + u8 *base = dp->base; + int len, start_page, pkt_len, i, isr; +#if DEBUG & 4 + int dx; +#endif + + DEBUG_FUNCTION(); + + len = pkt_len = total_len; + if (pkt_len < IEEE_8023_MIN_FRAME) + pkt_len = IEEE_8023_MIN_FRAME; + + start_page = dp->tx_next; + if (dp->tx_next == dp->tx_buf1) { + dp->tx1 = start_page; + dp->tx1_len = pkt_len; + dp->tx1_key = key; + dp->tx_next = dp->tx_buf2; + } else { + dp->tx2 = start_page; + dp->tx2_len = pkt_len; + dp->tx2_key = key; + dp->tx_next = dp->tx_buf1; + } + +#if DEBUG & 5 + printf("TX prep page %d len %d\n", start_page, pkt_len); +#endif + + DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */ + { + /* + * Dummy read. The manual sez something slightly different, + * but the code is extended a bit to do what Hitachi's monitor + * does (i.e., also read data). + */ + + u16 tmp; + int len = 1; + + DP_OUT(base, DP_RSAL, 0x100 - len); + DP_OUT(base, DP_RSAH, (start_page - 1) & 0xff); + DP_OUT(base, DP_RBCL, len); + DP_OUT(base, DP_RBCH, 0); + DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_RDMA | DP_CR_START); + DP_IN_DATA(dp->data, tmp); + } + +#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA + /* + * Stall for a bit before continuing to work around random data + * corruption problems on some platforms. + */ + CYGACC_CALL_IF_DELAY_US(1); +#endif + + /* Send data to device buffer(s) */ + DP_OUT(base, DP_RSAL, 0); + DP_OUT(base, DP_RSAH, start_page); + DP_OUT(base, DP_RBCL, pkt_len & 0xFF); + DP_OUT(base, DP_RBCH, pkt_len >> 8); + DP_OUT(base, DP_CR, DP_CR_WDMA | DP_CR_START); + + /* Put data into buffer */ +#if DEBUG & 4 + printf(" sg buf %08lx len %08x\n ", (u32)data, len); + dx = 0; +#endif + while (len > 0) { +#if DEBUG & 4 + printf(" %02x", *data); + if (0 == (++dx % 16)) printf("\n "); +#endif + + DP_OUT_DATA(dp->data, *data++); + len--; + } +#if DEBUG & 4 + printf("\n"); +#endif + if (total_len < pkt_len) { +#if DEBUG & 4 + printf(" + %d bytes of padding\n", pkt_len - total_len); +#endif + /* Padding to 802.3 length was required */ + for (i = total_len; i < pkt_len;) { + i++; + DP_OUT_DATA(dp->data, 0); + } + } + +#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA + /* + * After last data write, delay for a bit before accessing the + * device again, or we may get random data corruption in the last + * datum (on some platforms). + */ + CYGACC_CALL_IF_DELAY_US(1); +#endif + + /* Wait for DMA to complete */ + do { + DP_IN(base, DP_ISR, isr); + } while ((isr & DP_ISR_RDC) == 0); + + /* Then disable DMA */ + DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START); + + /* Start transmit if not already going */ + if (!dp->tx_started) { + if (start_page == dp->tx1) { + dp->tx_int = 1; /* Expecting interrupt from BUF1 */ + } else { + dp->tx_int = 2; /* Expecting interrupt from BUF2 */ + } + dp83902a_start_xmit(start_page, pkt_len); + } +} + +/* + * This function is called when a packet has been received. It's job is + * to prepare to unload the packet from the hardware. Once the length of + * the packet is known, the upper layer of the driver can be told. When + * the upper layer is ready to unload the packet, the internal function + * 'dp83902a_recv' will be called to actually fetch it from the hardware. + */ +static void +dp83902a_RxEvent(void) +{ + struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; + u8 *base = dp->base; + u8 rsr; + u8 rcv_hdr[4]; + int i, len, pkt, cur; + + DEBUG_FUNCTION(); + + DP_IN(base, DP_RSR, rsr); + while (true) { + /* Read incoming packet header */ + DP_OUT(base, DP_CR, DP_CR_PAGE1 | DP_CR_NODMA | DP_CR_START); + DP_IN(base, DP_P1_CURP, cur); + DP_OUT(base, DP_P1_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START); + DP_IN(base, DP_BNDRY, pkt); + + pkt += 1; + if (pkt == dp->rx_buf_end) + pkt = dp->rx_buf_start; + + if (pkt == cur) { + break; + } + DP_OUT(base, DP_RBCL, sizeof(rcv_hdr)); + DP_OUT(base, DP_RBCH, 0); + DP_OUT(base, DP_RSAL, 0); + DP_OUT(base, DP_RSAH, pkt); + if (dp->rx_next == pkt) { + if (cur == dp->rx_buf_start) + DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1); + else + DP_OUT(base, DP_BNDRY, cur - 1); /* Update pointer */ + return; + } + dp->rx_next = pkt; + DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */ + DP_OUT(base, DP_CR, DP_CR_RDMA | DP_CR_START); +#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_RX_DMA + CYGACC_CALL_IF_DELAY_US(10); +#endif + + /* read header (get data size)*/ + for (i = 0; i < sizeof(rcv_hdr);) { + DP_IN_DATA(dp->data, rcv_hdr[i++]); + } + +#if DEBUG & 5 + printf("rx hdr %02x %02x %02x %02x\n", + rcv_hdr[0], rcv_hdr[1], rcv_hdr[2], rcv_hdr[3]); +#endif + len = ((rcv_hdr[3] << 8) | rcv_hdr[2]) - sizeof(rcv_hdr); + + /* data read */ + uboot_push_packet_len(len); + + if (rcv_hdr[1] == dp->rx_buf_start) + DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1); + else + DP_OUT(base, DP_BNDRY, rcv_hdr[1] - 1); /* Update pointer */ + } +} + +/* + * This function is called as a result of the "eth_drv_recv()" call above. + * It's job is to actually fetch data for a packet from the hardware once + * memory buffers have been allocated for the packet. Note that the buffers + * may come in pieces, using a scatter-gather list. This allows for more + * efficient processing in the upper layers of the stack. + */ +static void +dp83902a_recv(u8 *data, int len) +{ + struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; + u8 *base = dp->base; + int i, mlen; + u8 saved_char = 0; + bool saved; +#if DEBUG & 4 + int dx; +#endif + + DEBUG_FUNCTION(); + +#if DEBUG & 5 + printf("Rx packet %d length %d\n", dp->rx_next, len); +#endif + + /* Read incoming packet data */ + DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START); + DP_OUT(base, DP_RBCL, len & 0xFF); + DP_OUT(base, DP_RBCH, len >> 8); + DP_OUT(base, DP_RSAL, 4); /* Past header */ + DP_OUT(base, DP_RSAH, dp->rx_next); + DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */ + DP_OUT(base, DP_CR, DP_CR_RDMA | DP_CR_START); +#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_RX_DMA + CYGACC_CALL_IF_DELAY_US(10); +#endif + + saved = false; + for (i = 0; i < 1; i++) { + if (data) { + mlen = len; +#if DEBUG & 4 + printf(" sg buf %08lx len %08x \n", (u32) data, mlen); + dx = 0; +#endif + while (0 < mlen) { + /* Saved byte from previous loop? */ + if (saved) { + *data++ = saved_char; + mlen--; + saved = false; + continue; + } + + { + u8 tmp; + DP_IN_DATA(dp->data, tmp); +#if DEBUG & 4 + printf(" %02x", tmp); + if (0 == (++dx % 16)) printf("\n "); +#endif + *data++ = tmp;; + mlen--; + } + } +#if DEBUG & 4 + printf("\n"); +#endif + } + } +} + +static void +dp83902a_TxEvent(void) +{ + struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; + u8 *base = dp->base; + u8 tsr; + u32 key; + + DEBUG_FUNCTION(); + + DP_IN(base, DP_TSR, tsr); + if (dp->tx_int == 1) { + key = dp->tx1_key; + dp->tx1 = 0; + } else { + key = dp->tx2_key; + dp->tx2 = 0; + } + /* Start next packet if one is ready */ + dp->tx_started = false; + if (dp->tx1) { + dp83902a_start_xmit(dp->tx1, dp->tx1_len); + dp->tx_int = 1; + } else if (dp->tx2) { + dp83902a_start_xmit(dp->tx2, dp->tx2_len); + dp->tx_int = 2; + } else { + dp->tx_int = 0; + } + /* Tell higher level we sent this packet */ + uboot_push_tx_done(key, 0); +} + +/* + * Read the tally counters to clear them. Called in response to a CNT + * interrupt. + */ +static void +dp83902a_ClearCounters(void) +{ + struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; + u8 *base = dp->base; + u8 cnt1, cnt2, cnt3; + + DP_IN(base, DP_FER, cnt1); + DP_IN(base, DP_CER, cnt2); + DP_IN(base, DP_MISSED, cnt3); + DP_OUT(base, DP_ISR, DP_ISR_CNT); +} + +/* + * Deal with an overflow condition. This code follows the procedure set + * out in section 7.0 of the datasheet. + */ +static void +dp83902a_Overflow(void) +{ + struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *)&nic; + u8 *base = dp->base; + u8 isr; + + /* Issue a stop command and wait 1.6ms for it to complete. */ + DP_OUT(base, DP_CR, DP_CR_STOP | DP_CR_NODMA); + CYGACC_CALL_IF_DELAY_US(1600); + + /* Clear the remote byte counter registers. */ + DP_OUT(base, DP_RBCL, 0); + DP_OUT(base, DP_RBCH, 0); + + /* Enter loopback mode while we clear the buffer. */ + DP_OUT(base, DP_TCR, DP_TCR_LOCAL); + DP_OUT(base, DP_CR, DP_CR_START | DP_CR_NODMA); + + /* + * Read in as many packets as we can and acknowledge any and receive + * interrupts. Since the buffer has overflowed, a receive event of + * some kind will have occured. + */ + dp83902a_RxEvent(); + DP_OUT(base, DP_ISR, DP_ISR_RxP|DP_ISR_RxE); + + /* Clear the overflow condition and leave loopback mode. */ + DP_OUT(base, DP_ISR, DP_ISR_OFLW); + DP_OUT(base, DP_TCR, DP_TCR_NORMAL); + + /* + * If a transmit command was issued, but no transmit event has occured, + * restart it here. + */ + DP_IN(base, DP_ISR, isr); + if (dp->tx_started && !(isr & (DP_ISR_TxP|DP_ISR_TxE))) { + DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_TXPKT | DP_CR_START); + } +} + +static void +dp83902a_poll(void) +{ + struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; + u8 *base = dp->base; + u8 isr; + + DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0 | DP_CR_START); + DP_IN(base, DP_ISR, isr); + while (0 != isr) { + /* + * The CNT interrupt triggers when the MSB of one of the error + * counters is set. We don't much care about these counters, but + * we should read their values to reset them. + */ + if (isr & DP_ISR_CNT) { + dp83902a_ClearCounters(); + } + /* + * Check for overflow. It's a special case, since there's a + * particular procedure that must be followed to get back into + * a running state.a + */ + if (isr & DP_ISR_OFLW) { + dp83902a_Overflow(); + } else { + /* + * Other kinds of interrupts can be acknowledged simply by + * clearing the relevant bits of the ISR. Do that now, then + * handle the interrupts we care about. + */ + DP_OUT(base, DP_ISR, isr); /* Clear set bits */ + if (!dp->running) break; /* Is this necessary? */ + /* + * Check for tx_started on TX event since these may happen + * spuriously it seems. + */ + if (isr & (DP_ISR_TxP|DP_ISR_TxE) && dp->tx_started) { + dp83902a_TxEvent(); + } + if (isr & (DP_ISR_RxP|DP_ISR_RxE)) { + dp83902a_RxEvent(); + } + } + DP_IN(base, DP_ISR, isr); + } +} + + +/* U-boot specific routines */ +static u8 *pbuf = NULL; + +static int pkey = -1; +static int initialized = 0; + +void uboot_push_packet_len(int len) { + PRINTK("pushed len = %d\n", len); + if (len >= 2000) { + printf("NE2000: packet too big\n"); + return; + } + dp83902a_recv(&pbuf[0], len); + + /*Just pass it to the upper layer*/ + NetReceive(&pbuf[0], len); +} + +void uboot_push_tx_done(int key, int val) { + PRINTK("pushed key = %d\n", key); + pkey = key; +} + +int eth_init(bd_t *bd) { + int r; + u8 dev_addr[6]; + char ethaddr[20]; + + PRINTK("### eth_init\n"); + + if (!pbuf) { + pbuf = malloc(2000); + if (!pbuf) { + printf("Cannot allocate rx buffer\n"); + return -1; + } + } + +#ifdef CONFIG_DRIVER_NE2000_CCR + { + vu_char *p = (vu_char *) CONFIG_DRIVER_NE2000_CCR; + + PRINTK("CCR before is %x\n", *p); + *p = CONFIG_DRIVER_NE2000_VAL; + PRINTK("CCR after is %x\n", *p); + } +#endif + + nic.base = (u8 *) CONFIG_DRIVER_NE2000_BASE; + + r = get_prom(dev_addr, nic.base); + if (!r) + return -1; + + sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X", + dev_addr[0], dev_addr[1], + dev_addr[2], dev_addr[3], + dev_addr[4], dev_addr[5]) ; + PRINTK("Set environment from HW MAC addr = \"%s\"\n", ethaddr); + setenv ("ethaddr", ethaddr); + + nic.data = nic.base + DP_DATA; + nic.tx_buf1 = START_PG; + nic.tx_buf2 = START_PG2; + nic.rx_buf_start = RX_START; + nic.rx_buf_end = RX_END; + + if (dp83902a_init() == false) + return -1; + + dp83902a_start(dev_addr); + initialized = 1; + + return 0; +} + +void eth_halt() { + + PRINTK("### eth_halt\n"); + if(initialized) + dp83902a_stop(); + initialized = 0; +} + +int eth_rx() { + dp83902a_poll(); + return 1; +} + +int eth_send(volatile void *packet, int length) { + int tmo; + + PRINTK("### eth_send\n"); + + pkey = -1; + + dp83902a_send((u8 *) packet, length, 666); + tmo = get_timer (0) + TOUT * CFG_HZ; + while(1) { + dp83902a_poll(); + if (pkey != -1) { + PRINTK("Packet sucesfully sent\n"); + return 0; + } + if (get_timer (0) >= tmo) { + printf("transmission error (timoeut)\n"); + return 0; + } + + } + return 0; +} diff --git a/drivers/net/ne2000_base.h b/drivers/net/ne2000_base.h index 948b290..5446de4 100644 --- a/drivers/net/ne2000_base.h +++ b/drivers/net/ne2000_base.h @@ -80,10 +80,35 @@ are GPL, so this is, of course, GPL. #define __NE2000_BASE_H__ #define bool int - #define false 0 #define true 1 +/* + * Debugging details + * + * Set to perms of: + * 0 disables all debug output + * 1 for process debug output + * 2 for added data IO output: get_reg, put_reg + * 4 for packet allocation/free output + * 8 for only startup status, so we can tell we're installed OK + */ +#if 0 +#define DEBUG 0xf +#else +#define DEBUG 0 +#endif + +#if DEBUG & 1 +#define DEBUG_FUNCTION() do { printf("%s\n", __FUNCTION__); } while (0) +#define DEBUG_LINE() do { printf("%d\n", __LINE__); } while (0) +#define PRINTK(args...) printf(args) +#else +#define DEBUG_FUNCTION() do {} while(0) +#define DEBUG_LINE() do {} while(0) +#define PRINTK(args...) +#endif + /* timeout for tx/rx in s */ #define TOUT 5 /* Ether MAC address size */ @@ -119,11 +144,6 @@ typedef struct dp83902a_priv_data { int rx_buf_start, rx_buf_end; } dp83902a_priv_data_t; -/* - * Some forward declarations - */ -static void dp83902a_poll(void); - /* ------------------------------------------------------------------------ */ /* Register offsets */ @@ -281,4 +301,8 @@ static void dp83902a_poll(void); #define IEEE_8023_MAX_FRAME 1518 /* Largest possible ethernet frame */ #define IEEE_8023_MIN_FRAME 64 /* Smallest possible ethernet frame */ + +/* Functions */ +int get_prom(u8* mac_addr, u8* base_addr); + #endif /* __NE2000_BASE_H__ */ -- cgit v1.1 From c9d6b6925344740ca1db2f8a6bab7921ff820de3 Mon Sep 17 00:00:00 2001 From: Andre Schwarz Date: Tue, 19 Aug 2008 16:07:03 +0200 Subject: enable 10/100M at VSC8601 at tsec driver Currently VSC8601 doesn't link with 10/100M partners if the EEPROM/Strapping is not set up. Setting the auto-neg register fixes this. Signed-off-by: Andre Schwarz Signed-off-by: Ben Warren --- drivers/net/tsec.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 8ab6d07..e34076f 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -1366,6 +1366,8 @@ struct phy_info phy_info_VSC8601 = { {MIIM_EXT_PAGE_ACCESS,0,NULL}, #endif #endif + {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_RESTART, &mii_cr_init}, {miim_end,} }, (struct phy_cmd[]){ /* startup */ -- cgit v1.1 From 30f574717277238b9014b8136c90eea77196490f Mon Sep 17 00:00:00 2001 From: Louis Su Date: Wed, 9 Jul 2008 11:01:37 +0800 Subject: AX88180: new gigabit network driver Signed-off-by: Louis Su Signed-off-by: Ben Warren --- drivers/net/Makefile | 1 + drivers/net/ax88180.c | 727 ++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/net/ax88180.h | 412 ++++++++++++++++++++++++++++ 3 files changed, 1140 insertions(+) create mode 100644 drivers/net/ax88180.c create mode 100644 drivers/net/ax88180.h (limited to 'drivers') diff --git a/drivers/net/Makefile b/drivers/net/Makefile index a4ea3a2..439c354 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libnet.a COBJS-$(CONFIG_DRIVER_3C589) += 3c589.o +COBJS-$(CONFIG_DRIVER_AX88180) += ax88180.o COBJS-$(CONFIG_BCM570x) += bcm570x.o bcm570x_autoneg.o 5701rls.o COBJS-$(CONFIG_BFIN_MAC) += bfin_mac.o COBJS-$(CONFIG_DRIVER_CS8900) += cs8900.o diff --git a/drivers/net/ax88180.c b/drivers/net/ax88180.c new file mode 100644 index 0000000..d843397 --- /dev/null +++ b/drivers/net/ax88180.c @@ -0,0 +1,727 @@ +/* + * ax88180: ASIX AX88180 Non-PCI Gigabit Ethernet u-boot driver + * + * This program is free software; you can distribute it and/or modify + * it under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * This program is distributed in the hope it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the GNU General Public License for more details. + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, + * USA. + */ + +/* + * ======================================================================== + * ASIX AX88180 Non-PCI 16/32-bit Gigabit Ethernet Linux Driver + * + * The AX88180 Ethernet controller is a high performance and highly + * integrated local CPU bus Ethernet controller with embedded 40K bytes + * SRAM and supports both 16-bit and 32-bit SRAM-Like interfaces for any + * embedded systems. + * The AX88180 is a single chip 10/100/1000Mbps Gigabit Ethernet + * controller that supports both MII and RGMII interfaces and is + * compliant to IEEE 802.3, IEEE 802.3u and IEEE 802.3z standards. + * + * Please visit ASIX's web site (http://www.asix.com.tw) for more + * details. + * + * Module Name : ax88180.c + * Date : 2008-07-07 + * History + * 09/06/2006 : New release for AX88180 US2 chip. + * 07/07/2008 : Fix up the coding style and using inline functions + * instead of macros + * ======================================================================== + */ +#include +#include +#include +#include +#include "ax88180.h" + +/* + * =========================================================================== + * Local SubProgram Declaration + * =========================================================================== + */ +static void ax88180_rx_handler (struct eth_device *dev); +static int ax88180_phy_initial (struct eth_device *dev); +static void ax88180_meidia_config (struct eth_device *dev); +static unsigned long get_CicadaPHY_meida_mode (struct eth_device *dev); +static unsigned long get_MarvellPHY_meida_mode (struct eth_device *dev); +static unsigned short ax88180_mdio_read (struct eth_device *dev, + unsigned long regaddr); +static void ax88180_mdio_write (struct eth_device *dev, + unsigned long regaddr, unsigned short regdata); + +/* + * =========================================================================== + * Local SubProgram Bodies + * =========================================================================== + */ +static int ax88180_mdio_check_complete (struct eth_device *dev) +{ + int us_cnt = 10000; + unsigned short tmpval; + + /* MDIO read/write should not take more than 10 ms */ + while (--us_cnt) { + tmpval = INW (dev, MDIOCTRL); + if (((tmpval & READ_PHY) == 0) && ((tmpval & WRITE_PHY) == 0)) + break; + } + + return us_cnt; +} + +static unsigned short +ax88180_mdio_read (struct eth_device *dev, unsigned long regaddr) +{ + struct ax88180_private *priv = (struct ax88180_private *)dev->priv; + unsigned long tmpval = 0; + + OUTW (dev, (READ_PHY | (regaddr << 8) | priv->PhyAddr), MDIOCTRL); + + if (ax88180_mdio_check_complete (dev)) + tmpval = INW (dev, MDIODP); + else + printf ("Failed to read PHY register!\n"); + + return (unsigned short)(tmpval & 0xFFFF); +} + +static void +ax88180_mdio_write (struct eth_device *dev, unsigned long regaddr, + unsigned short regdata) +{ + struct ax88180_private *priv = (struct ax88180_private *)dev->priv; + + OUTW (dev, regdata, MDIODP); + + OUTW (dev, (WRITE_PHY | (regaddr << 8) | priv->PhyAddr), MDIOCTRL); + + if (!ax88180_mdio_check_complete (dev)) + printf ("Failed to write PHY register!\n"); +} + +static int ax88180_phy_reset (struct eth_device *dev) +{ + unsigned short delay_cnt = 500; + + ax88180_mdio_write (dev, BMCR, (PHY_RESET | AUTONEG_EN)); + + /* Wait for the reset to complete, or time out (500 ms) */ + while (ax88180_mdio_read (dev, BMCR) & PHY_RESET) { + udelay (1000); + if (--delay_cnt == 0) { + printf ("Failed to reset PHY!\n"); + return -1; + } + } + + return 0; +} + +static void ax88180_mac_reset (struct eth_device *dev) +{ + unsigned long tmpval; + unsigned char i; + + struct { + unsigned short offset, value; + } program_seq[] = { + { + MISC, MISC_NORMAL}, { + RXINDICATOR, DEFAULT_RXINDICATOR}, { + TXCMD, DEFAULT_TXCMD}, { + TXBS, DEFAULT_TXBS}, { + TXDES0, DEFAULT_TXDES0}, { + TXDES1, DEFAULT_TXDES1}, { + TXDES2, DEFAULT_TXDES2}, { + TXDES3, DEFAULT_TXDES3}, { + TXCFG, DEFAULT_TXCFG}, { + MACCFG2, DEFAULT_MACCFG2}, { + MACCFG3, DEFAULT_MACCFG3}, { + TXLEN, DEFAULT_TXLEN}, { + RXBTHD0, DEFAULT_RXBTHD0}, { + RXBTHD1, DEFAULT_RXBTHD1}, { + RXFULTHD, DEFAULT_RXFULTHD}, { + DOGTHD0, DEFAULT_DOGTHD0}, { + DOGTHD1, DEFAULT_DOGTHD1},}; + + OUTW (dev, MISC_RESET_MAC, MISC); + tmpval = INW (dev, MISC); + + for (i = 0; i < (sizeof (program_seq) / sizeof (program_seq[0])); i++) + OUTW (dev, program_seq[i].value, program_seq[i].offset); +} + +static int ax88180_poll_tx_complete (struct eth_device *dev) +{ + struct ax88180_private *priv = (struct ax88180_private *)dev->priv; + unsigned long tmpval, txbs_txdp; + int TimeOutCnt = 10000; + + txbs_txdp = 1 << priv->NextTxDesc; + + while (TimeOutCnt--) { + + tmpval = INW (dev, TXBS); + + if ((tmpval & txbs_txdp) == 0) + break; + + udelay (100); + } + + if (TimeOutCnt) + return 0; + else + return -TimeOutCnt; +} + +static void ax88180_rx_handler (struct eth_device *dev) +{ + struct ax88180_private *priv = (struct ax88180_private *)dev->priv; + unsigned long data_size; + unsigned short rxcurt_ptr, rxbound_ptr, next_ptr; + int i; +#if defined (CONFIG_DRIVER_AX88180_16BIT) + unsigned short *rxdata = (unsigned short *)NetRxPackets[0]; +#else + unsigned long *rxdata = (unsigned long *)NetRxPackets[0]; +#endif + unsigned short count; + + rxcurt_ptr = INW (dev, RXCURT); + rxbound_ptr = INW (dev, RXBOUND); + next_ptr = (rxbound_ptr + 1) & RX_PAGE_NUM_MASK; + + debug ("ax88180: RX original RXBOUND=0x%04x," + " RXCURT=0x%04x\n", rxbound_ptr, rxcurt_ptr); + + while (next_ptr != rxcurt_ptr) { + + OUTW (dev, RX_START_READ, RXINDICATOR); + + data_size = READ_RXBUF (dev) & 0xFFFF; + + if ((data_size == 0) || (data_size > MAX_RX_SIZE)) { + + OUTW (dev, RX_STOP_READ, RXINDICATOR); + + ax88180_mac_reset (dev); + printf ("ax88180: Invalid Rx packet length!" + " (len=0x%04lx)\n", data_size); + + debug ("ax88180: RX RXBOUND=0x%04x," + "RXCURT=0x%04x\n", rxbound_ptr, rxcurt_ptr); + return; + } + + rxbound_ptr += (((data_size + 0xF) & 0xFFF0) >> 4) + 1; + rxbound_ptr &= RX_PAGE_NUM_MASK; + + /* Comput access times */ + count = (data_size + priv->PadSize) >> priv->BusWidth; + + for (i = 0; i < count; i++) { + *(rxdata + i) = READ_RXBUF (dev); + } + + OUTW (dev, RX_STOP_READ, RXINDICATOR); + + /* Pass the packet up to the protocol layers. */ + NetReceive (NetRxPackets[0], data_size); + + OUTW (dev, rxbound_ptr, RXBOUND); + + rxcurt_ptr = INW (dev, RXCURT); + rxbound_ptr = INW (dev, RXBOUND); + next_ptr = (rxbound_ptr + 1) & RX_PAGE_NUM_MASK; + + debug ("ax88180: RX updated RXBOUND=0x%04x," + "RXCURT=0x%04x\n", rxbound_ptr, rxcurt_ptr); + } + + return; +} + +static int ax88180_phy_initial (struct eth_device *dev) +{ + struct ax88180_private *priv = (struct ax88180_private *)dev->priv; + unsigned long tmp_regval; + + /* Check avaliable PHY chipset */ + priv->PhyAddr = MARVELL_88E1111_PHYADDR; + priv->PhyID0 = ax88180_mdio_read (dev, PHYIDR0); + + if (priv->PhyID0 == MARVELL_88E1111_PHYIDR0) { + + debug ("ax88180: Found Marvell 88E1111 PHY." + " (PHY Addr=0x%x)\n", priv->PhyAddr); + + tmp_regval = ax88180_mdio_read (dev, M88_EXT_SSR); + if ((tmp_regval & HWCFG_MODE_MASK) == RGMII_COPPER_MODE) { + + ax88180_mdio_write (dev, M88_EXT_SCR, DEFAULT_EXT_SCR); + if (ax88180_phy_reset (dev) < 0) + return 0; + ax88180_mdio_write (dev, M88_IER, LINK_CHANGE_INT); + } + } else { + + priv->PhyAddr = CICADA_CIS8201_PHYADDR; + priv->PhyID0 = ax88180_mdio_read (dev, PHYIDR0); + + if (priv->PhyID0 == CICADA_CIS8201_PHYIDR0) { + + debug ("ax88180: Found CICADA CIS8201 PHY" + " chipset. (PHY Addr=0x%x)\n", priv->PhyAddr); + ax88180_mdio_write (dev, CIS_IMR, + (CIS_INT_ENABLE | LINK_CHANGE_INT)); + + /* Set CIS_SMI_PRIORITY bit before force the media mode */ + tmp_regval = + ax88180_mdio_read (dev, CIS_AUX_CTRL_STATUS); + tmp_regval &= ~CIS_SMI_PRIORITY; + ax88180_mdio_write (dev, CIS_AUX_CTRL_STATUS, + tmp_regval); + } else { + printf ("ax88180: Unknown PHY chipset!!\n"); + return 0; + } + } + + return 1; +} + +static void ax88180_meidia_config (struct eth_device *dev) +{ + struct ax88180_private *priv = (struct ax88180_private *)dev->priv; + unsigned long bmcr_val, bmsr_val; + unsigned long rxcfg_val, maccfg0_val, maccfg1_val; + unsigned long RealMediaMode; + int i; + + /* Waiting 2 seconds for PHY link stable */ + for (i = 0; i < 20000; i++) { + bmsr_val = ax88180_mdio_read (dev, BMSR); + if (bmsr_val & LINKOK) { + break; + } + udelay (100); + } + + bmsr_val = ax88180_mdio_read (dev, BMSR); + debug ("ax88180: BMSR=0x%04x\n", (unsigned int)bmsr_val); + + if (bmsr_val & LINKOK) { + bmcr_val = ax88180_mdio_read (dev, BMCR); + + if (bmcr_val & AUTONEG_EN) { + + /* + * Waiting for Auto-negotiation completion, this may + * take up to 5 seconds. + */ + debug ("ax88180: Auto-negotiation is " + "enabled. Waiting for NWay completion..\n"); + for (i = 0; i < 50000; i++) { + bmsr_val = ax88180_mdio_read (dev, BMSR); + if (bmsr_val & AUTONEG_COMPLETE) { + break; + } + udelay (100); + } + } else + debug ("ax88180: Auto-negotiation is disabled.\n"); + + debug ("ax88180: BMCR=0x%04x, BMSR=0x%04x\n", + (unsigned int)bmcr_val, (unsigned int)bmsr_val); + + /* Get real media mode here */ + if (priv->PhyID0 == MARVELL_88E1111_PHYIDR0) { + RealMediaMode = get_MarvellPHY_meida_mode (dev); + } else if (priv->PhyID0 == CICADA_CIS8201_PHYIDR0) { + RealMediaMode = get_CicadaPHY_meida_mode (dev); + } else { + RealMediaMode = MEDIA_1000FULL; + } + + priv->LinkState = INS_LINK_UP; + + switch (RealMediaMode) { + case MEDIA_1000FULL: + debug ("ax88180: 1000Mbps Full-duplex mode.\n"); + rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG; + maccfg0_val = TXFLOW_ENABLE | DEFAULT_MACCFG0; + maccfg1_val = GIGA_MODE_EN | RXFLOW_EN | + FULLDUPLEX | DEFAULT_MACCFG1; + break; + + case MEDIA_1000HALF: + debug ("ax88180: 1000Mbps Half-duplex mode.\n"); + rxcfg_val = DEFAULT_RXCFG; + maccfg0_val = DEFAULT_MACCFG0; + maccfg1_val = GIGA_MODE_EN | DEFAULT_MACCFG1; + break; + + case MEDIA_100FULL: + debug ("ax88180: 100Mbps Full-duplex mode.\n"); + rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG; + maccfg0_val = SPEED100 | TXFLOW_ENABLE + | DEFAULT_MACCFG0; + maccfg1_val = RXFLOW_EN | FULLDUPLEX | DEFAULT_MACCFG1; + break; + + case MEDIA_100HALF: + debug ("ax88180: 100Mbps Half-duplex mode.\n"); + rxcfg_val = DEFAULT_RXCFG; + maccfg0_val = SPEED100 | DEFAULT_MACCFG0; + maccfg1_val = DEFAULT_MACCFG1; + break; + + case MEDIA_10FULL: + debug ("ax88180: 10Mbps Full-duplex mode.\n"); + rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG; + maccfg0_val = TXFLOW_ENABLE | DEFAULT_MACCFG0; + maccfg1_val = RXFLOW_EN | FULLDUPLEX | DEFAULT_MACCFG1; + break; + + case MEDIA_10HALF: + debug ("ax88180: 10Mbps Half-duplex mode.\n"); + rxcfg_val = DEFAULT_RXCFG; + maccfg0_val = DEFAULT_MACCFG0; + maccfg1_val = DEFAULT_MACCFG1; + break; + default: + debug ("ax88180: Unknow media mode.\n"); + rxcfg_val = DEFAULT_RXCFG; + maccfg0_val = DEFAULT_MACCFG0; + maccfg1_val = DEFAULT_MACCFG1; + + priv->LinkState = INS_LINK_DOWN; + break; + } + + } else { + rxcfg_val = DEFAULT_RXCFG; + maccfg0_val = DEFAULT_MACCFG0; + maccfg1_val = DEFAULT_MACCFG1; + + priv->LinkState = INS_LINK_DOWN; + } + + OUTW (dev, rxcfg_val, RXCFG); + OUTW (dev, maccfg0_val, MACCFG0); + OUTW (dev, maccfg1_val, MACCFG1); + + return; +} + +static unsigned long get_MarvellPHY_meida_mode (struct eth_device *dev) +{ + unsigned long m88_ssr; + unsigned long MediaMode; + + m88_ssr = ax88180_mdio_read (dev, M88_SSR); + switch (m88_ssr & SSR_MEDIA_MASK) { + case SSR_1000FULL: + MediaMode = MEDIA_1000FULL; + break; + case SSR_1000HALF: + MediaMode = MEDIA_1000HALF; + break; + case SSR_100FULL: + MediaMode = MEDIA_100FULL; + break; + case SSR_100HALF: + MediaMode = MEDIA_100HALF; + break; + case SSR_10FULL: + MediaMode = MEDIA_10FULL; + break; + case SSR_10HALF: + MediaMode = MEDIA_10HALF; + break; + default: + MediaMode = MEDIA_UNKNOWN; + break; + } + + return MediaMode; +} + +static unsigned long get_CicadaPHY_meida_mode (struct eth_device *dev) +{ + unsigned long tmp_regval; + unsigned long MediaMode; + + tmp_regval = ax88180_mdio_read (dev, CIS_AUX_CTRL_STATUS); + switch (tmp_regval & CIS_MEDIA_MASK) { + case CIS_1000FULL: + MediaMode = MEDIA_1000FULL; + break; + case CIS_1000HALF: + MediaMode = MEDIA_1000HALF; + break; + case CIS_100FULL: + MediaMode = MEDIA_100FULL; + break; + case CIS_100HALF: + MediaMode = MEDIA_100HALF; + break; + case CIS_10FULL: + MediaMode = MEDIA_10FULL; + break; + case CIS_10HALF: + MediaMode = MEDIA_10HALF; + break; + default: + MediaMode = MEDIA_UNKNOWN; + break; + } + + return MediaMode; +} + +static void ax88180_halt (struct eth_device *dev) +{ + /* Disable AX88180 TX/RX functions */ + OUTW (dev, WAKEMOD, CMD); +} + +static int ax88180_init (struct eth_device *dev, bd_t * bd) +{ + struct ax88180_private *priv = (struct ax88180_private *)dev->priv; + unsigned short tmp_regval; + + ax88180_mac_reset (dev); + + /* Disable interrupt */ + OUTW (dev, CLEAR_IMR, IMR); + + /* Disable AX88180 TX/RX functions */ + OUTW (dev, WAKEMOD, CMD); + + /* Fill the MAC address */ + tmp_regval = + dev->enetaddr[0] | (((unsigned short)dev->enetaddr[1]) << 8); + OUTW (dev, tmp_regval, MACID0); + + tmp_regval = + dev->enetaddr[2] | (((unsigned short)dev->enetaddr[3]) << 8); + OUTW (dev, tmp_regval, MACID1); + + tmp_regval = + dev->enetaddr[4] | (((unsigned short)dev->enetaddr[5]) << 8); + OUTW (dev, tmp_regval, MACID2); + + ax88180_meidia_config (dev); + + OUTW (dev, DEFAULT_RXFILTER, RXFILTER); + + /* Initial variables here */ + priv->FirstTxDesc = TXDP0; + priv->NextTxDesc = TXDP0; + + /* Check if there is any invalid interrupt status and clear it. */ + OUTW (dev, INW (dev, ISR), ISR); + + /* Start AX88180 TX/RX functions */ + OUTW (dev, (RXEN | TXEN | WAKEMOD), CMD); + + return 0; +} + +/* Get a data block via Ethernet */ +static int ax88180_recv (struct eth_device *dev) +{ + unsigned short ISR_Status; + unsigned short tmp_regval; + + /* Read and check interrupt status here. */ + ISR_Status = INW (dev, ISR); + + while (ISR_Status) { + /* Clear the interrupt status */ + OUTW (dev, ISR_Status, ISR); + + debug ("\nax88180: The interrupt status = 0x%04x\n", + ISR_Status); + + if (ISR_Status & ISR_PHY) { + /* Read ISR register once to clear PHY interrupt bit */ + tmp_regval = ax88180_mdio_read (dev, M88_ISR); + ax88180_meidia_config (dev); + } + + if ((ISR_Status & ISR_RX) || (ISR_Status & ISR_RXBUFFOVR)) { + ax88180_rx_handler (dev); + } + + /* Read and check interrupt status again */ + ISR_Status = INW (dev, ISR); + } + + return 0; +} + +/* Send a data block via Ethernet. */ +static int +ax88180_send (struct eth_device *dev, volatile void *packet, int length) +{ + struct ax88180_private *priv = (struct ax88180_private *)dev->priv; + unsigned short TXDES_addr; + unsigned short txcmd_txdp, txbs_txdp; + unsigned short tmp_data; + int i; +#if defined (CONFIG_DRIVER_AX88180_16BIT) + volatile unsigned short *txdata = (volatile unsigned short *)packet; +#else + volatile unsigned long *txdata = (volatile unsigned long *)packet; +#endif + unsigned short count; + + if (priv->LinkState != INS_LINK_UP) { + return 0; + } + + priv->FirstTxDesc = priv->NextTxDesc; + txbs_txdp = 1 << priv->FirstTxDesc; + + debug ("ax88180: TXDP%d is available\n", priv->FirstTxDesc); + + txcmd_txdp = priv->FirstTxDesc << 13; + TXDES_addr = TXDES0 + (priv->FirstTxDesc << 2); + + OUTW (dev, (txcmd_txdp | length | TX_START_WRITE), TXCMD); + + /* Comput access times */ + count = (length + priv->PadSize) >> priv->BusWidth; + + for (i = 0; i < count; i++) { + WRITE_TXBUF (dev, *(txdata + i)); + } + + OUTW (dev, txcmd_txdp | length, TXCMD); + OUTW (dev, txbs_txdp, TXBS); + OUTW (dev, (TXDPx_ENABLE | length), TXDES_addr); + + priv->NextTxDesc = (priv->NextTxDesc + 1) & TXDP_MASK; + + /* + * Check the available transmit descriptor, if we had exhausted all + * transmit descriptor ,then we have to wait for at least one free + * descriptor + */ + txbs_txdp = 1 << priv->NextTxDesc; + tmp_data = INW (dev, TXBS); + + if (tmp_data & txbs_txdp) { + if (ax88180_poll_tx_complete (dev) < 0) { + ax88180_mac_reset (dev); + priv->FirstTxDesc = TXDP0; + priv->NextTxDesc = TXDP0; + printf ("ax88180: Transmit time out occurred!\n"); + } + } + + return 0; +} + +static void ax88180_read_mac_addr (struct eth_device *dev) +{ + unsigned short macid0_val, macid1_val, macid2_val; + unsigned short tmp_regval; + unsigned short i; + + /* Reload MAC address from EEPROM */ + OUTW (dev, RELOAD_EEPROM, PROMCTRL); + + /* Waiting for reload eeprom completion */ + for (i = 0; i < 500; i++) { + tmp_regval = INW (dev, PROMCTRL); + if ((tmp_regval & RELOAD_EEPROM) == 0) + break; + udelay (1000); + } + + /* Get MAC addresses */ + macid0_val = INW (dev, MACID0); + macid1_val = INW (dev, MACID1); + macid2_val = INW (dev, MACID2); + + if (((macid0_val | macid1_val | macid2_val) != 0) && + ((macid0_val & 0x01) == 0)) { + dev->enetaddr[0] = (unsigned char)macid0_val; + dev->enetaddr[1] = (unsigned char)(macid0_val >> 8); + dev->enetaddr[2] = (unsigned char)macid1_val; + dev->enetaddr[3] = (unsigned char)(macid1_val >> 8); + dev->enetaddr[4] = (unsigned char)macid2_val; + dev->enetaddr[5] = (unsigned char)(macid2_val >> 8); + } +} + +/* +=========================================================================== +<<<<<< Exported SubProgram Bodies >>>>>> +=========================================================================== +*/ +int ax88180_initialize (bd_t * bis) +{ + struct eth_device *dev; + struct ax88180_private *priv; + + dev = (struct eth_device *)malloc (sizeof *dev); + + if (NULL == dev) + return 0; + + memset (dev, 0, sizeof *dev); + + priv = (struct ax88180_private *)malloc (sizeof (*priv)); + + if (NULL == priv) + return 0; + + memset (priv, 0, sizeof *priv); + + sprintf (dev->name, "ax88180"); + dev->iobase = AX88180_BASE; + dev->priv = priv; + dev->init = ax88180_init; + dev->halt = ax88180_halt; + dev->send = ax88180_send; + dev->recv = ax88180_recv; + + priv->BusWidth = BUS_WIDTH_32; + priv->PadSize = 3; +#if defined (CONFIG_DRIVER_AX88180_16BIT) + OUTW (dev, (START_BASE >> 8), BASE); + OUTW (dev, DECODE_EN, DECODE); + + priv->BusWidth = BUS_WIDTH_16; + priv->PadSize = 1; +#endif + + ax88180_mac_reset (dev); + + /* Disable interrupt */ + OUTW (dev, CLEAR_IMR, IMR); + + /* Disable AX88180 TX/RX functions */ + OUTW (dev, WAKEMOD, CMD); + + ax88180_read_mac_addr (dev); + + eth_register (dev); + + return ax88180_phy_initial (dev); + +} diff --git a/drivers/net/ax88180.h b/drivers/net/ax88180.h new file mode 100644 index 0000000..5254e7d --- /dev/null +++ b/drivers/net/ax88180.h @@ -0,0 +1,412 @@ +/* ax88180.h: ASIX AX88180 Non-PCI Gigabit Ethernet u-boot driver */ +/* + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ + +#ifndef _AX88180_H_ +#define _AX88180_H_ + +#include +#include + +typedef enum _ax88180_link_state { + INS_LINK_DOWN, + INS_LINK_UP, + INS_LINK_UNKNOWN +} ax88180_link_state; + +struct ax88180_private { + unsigned char BusWidth; + unsigned char PadSize; + unsigned short PhyAddr; + unsigned short PhyID0; + unsigned short FirstTxDesc; + unsigned short NextTxDesc; + ax88180_link_state LinkState; +}; + +#define BUS_WIDTH_16 1 +#define BUS_WIDTH_32 2 + +#define ENABLE_JUMBO 1 +#define DISABLE_JUMBO 0 + +#define ENABLE_BURST 1 +#define DISABLE_BURST 0 + +#define NORMAL_RX_MODE 0 +#define RX_LOOPBACK_MODE 1 +#define RX_INIFINIT_LOOP_MODE 2 +#define TX_INIFINIT_LOOP_MODE 3 + +#define DEFAULT_ETH_MTU 1500 + +/* Jumbo packet size 4086 bytes included 4 bytes CRC*/ +#define MAX_JUMBO_MTU 4072 + +/* Max Tx Jumbo size 4086 bytes included 4 bytes CRC */ +#define MAX_TX_JUMBO_SIZE 4086 + +/* Max Rx Jumbo size is 15K Bytes */ +#define MAX_RX_SIZE 0x3C00 + +#define MARVELL_88E1111_PHYADDR 0x18 +#define MARVELL_88E1111_PHYIDR0 0x0141 + +#define CICADA_CIS8201_PHYADDR 0x01 +#define CICADA_CIS8201_PHYIDR0 0x000F + +#define MEDIA_AUTO 0 +#define MEDIA_1000FULL 1 +#define MEDIA_1000HALF 2 +#define MEDIA_100FULL 3 +#define MEDIA_100HALF 4 +#define MEDIA_10FULL 5 +#define MEDIA_10HALF 6 +#define MEDIA_UNKNOWN 7 + +#define AUTO_MEDIA 0 +#define FORCE_MEDIA 1 + +#define TXDP_MASK 3 +#define TXDP0 0 +#define TXDP1 1 +#define TXDP2 2 +#define TXDP3 3 + +#define CMD_MAP_SIZE 0x100 + +#if defined (CONFIG_DRIVER_AX88180_16BIT) + #define AX88180_MEMORY_SIZE 0x00004000 + #define START_BASE 0x1000 + + #define RX_BUF_SIZE 0x1000 + #define TX_BUF_SIZE 0x0F00 + + #define TX_BASE START_BASE + #define CMD_BASE (TX_BASE + TX_BUF_SIZE) + #define RX_BASE (CMD_BASE + CMD_MAP_SIZE) +#else + #define AX88180_MEMORY_SIZE 0x00010000 + + #define RX_BUF_SIZE 0x8000 + #define TX_BUF_SIZE 0x7C00 + + #define RX_BASE 0x0000 + #define TX_BASE (RX_BASE + RX_BUF_SIZE) + #define CMD_BASE (TX_BASE + TX_BUF_SIZE) +#endif + +/* AX88180 Memory Mapping Definition */ +#define RXBUFFER_START RX_BASE + #define RX_PACKET_LEN_OFFSET 0 + #define RX_PAGE_NUM_MASK 0x7FF /* RX pages 0~7FFh */ +#define TXBUFFER_START TX_BASE + +/* AX88180 MAC Register Definition */ +#define DECODE (0) + #define DECODE_EN 0x00000001 +#define BASE (6) +#define CMD (CMD_BASE + 0x0000) + #define WAKEMOD 0x00000001 + #define TXEN 0x00000100 + #define RXEN 0x00000200 + #define DEFAULT_CMD WAKEMOD +#define IMR (CMD_BASE + 0x0004) + #define IMR_RXBUFFOVR 0x00000001 + #define IMR_WATCHDOG 0x00000002 + #define IMR_TX 0x00000008 + #define IMR_RX 0x00000010 + #define IMR_PHY 0x00000020 + #define CLEAR_IMR 0x00000000 + #define DEFAULT_IMR (IMR_PHY | IMR_RX | IMR_TX |\ + IMR_RXBUFFOVR | IMR_WATCHDOG) +#define ISR (CMD_BASE + 0x0008) + #define ISR_RXBUFFOVR 0x00000001 + #define ISR_WATCHDOG 0x00000002 + #define ISR_TX 0x00000008 + #define ISR_RX 0x00000010 + #define ISR_PHY 0x00000020 +#define TXCFG (CMD_BASE + 0x0010) + #define AUTOPAD_CRC 0x00000050 + #define DEFAULT_TXCFG AUTOPAD_CRC +#define TXCMD (CMD_BASE + 0x0014) + #define TXCMD_TXDP_MASK 0x00006000 + #define TXCMD_TXDP0 0x00000000 + #define TXCMD_TXDP1 0x00002000 + #define TXCMD_TXDP2 0x00004000 + #define TXCMD_TXDP3 0x00006000 + #define TX_START_WRITE 0x00008000 + #define TX_STOP_WRITE 0x00000000 + #define DEFAULT_TXCMD 0x00000000 +#define TXBS (CMD_BASE + 0x0018) + #define TXDP0_USED 0x00000001 + #define TXDP1_USED 0x00000002 + #define TXDP2_USED 0x00000004 + #define TXDP3_USED 0x00000008 + #define DEFAULT_TXBS 0x00000000 +#define TXDES0 (CMD_BASE + 0x0020) + #define TXDPx_ENABLE 0x00008000 + #define TXDPx_LEN_MASK 0x00001FFF + #define DEFAULT_TXDES0 0x00000000 +#define TXDES1 (CMD_BASE + 0x0024) + #define TXDPx_ENABLE 0x00008000 + #define TXDPx_LEN_MASK 0x00001FFF + #define DEFAULT_TXDES1 0x00000000 +#define TXDES2 (CMD_BASE + 0x0028) + #define TXDPx_ENABLE 0x00008000 + #define TXDPx_LEN_MASK 0x00001FFF + #define DEFAULT_TXDES2 0x00000000 +#define TXDES3 (CMD_BASE + 0x002C) + #define TXDPx_ENABLE 0x00008000 + #define TXDPx_LEN_MASK 0x00001FFF + #define DEFAULT_TXDES3 0x00000000 +#define RXCFG (CMD_BASE + 0x0030) + #define RXBUFF_PROTECT 0x00000001 + #define RXTCPCRC_CHECK 0x00000010 + #define RXFLOW_ENABLE 0x00000100 + #define DEFAULT_RXCFG RXBUFF_PROTECT +#define RXCURT (CMD_BASE + 0x0034) + #define DEFAULT_RXCURT 0x00000000 +#define RXBOUND (CMD_BASE + 0x0038) + #define DEFAULT_RXBOUND 0x7FF //RX pages 0~7FFh +#define MACCFG0 (CMD_BASE + 0x0040) + #define MACCFG0_BIT3_0 0x00000007 + #define IPGT_VAL 0x00000150 + #define TXFLOW_ENABLE 0x00001000 + #define SPEED100 0x00008000 + #define DEFAULT_MACCFG0 (IPGT_VAL | MACCFG0_BIT3_0) +#define MACCFG1 (CMD_BASE + 0x0044) + #define RGMII_EN 0x00000002 + #define RXFLOW_EN 0x00000020 + #define FULLDUPLEX 0x00000040 + #define MAX_JUMBO_LEN 0x00000780 + #define RXJUMBO_EN 0x00000800 + #define GIGA_MODE_EN 0x00001000 + #define RXCRC_CHECK 0x00002000 + #define RXPAUSE_DA_CHECK 0x00004000 + + #define JUMBO_LEN_4K 0x00000200 + #define JUMBO_LEN_15K 0x00000780 + #define DEFAULT_MACCFG1 (RXCRC_CHECK | RXPAUSE_DA_CHECK | \ + RGMII_EN) + #define CICADA_DEFAULT_MACCFG1 (RXCRC_CHECK | RXPAUSE_DA_CHECK) +#define MACCFG2 (CMD_BASE + 0x0048) + #define MACCFG2_BIT15_8 0x00000100 + #define JAM_LIMIT_MASK 0x000000FC + #define DEFAULT_JAM_LIMIT 0x00000064 + #define DEFAULT_MACCFG2 MACCFG2_BIT15_8 +#define MACCFG3 (CMD_BASE + 0x004C) + #define IPGR2_VAL 0x0000000E + #define IPGR1_VAL 0x00000600 + #define NOABORT 0x00008000 + #define DEFAULT_MACCFG3 (IPGR1_VAL | IPGR2_VAL) +#define TXPAUT (CMD_BASE + 0x0054) + #define DEFAULT_TXPAUT 0x001FE000 +#define RXBTHD0 (CMD_BASE + 0x0058) + #define DEFAULT_RXBTHD0 0x00000300 +#define RXBTHD1 (CMD_BASE + 0x005C) + #define DEFAULT_RXBTHD1 0x00000600 +#define RXFULTHD (CMD_BASE + 0x0060) + #define DEFAULT_RXFULTHD 0x00000100 +#define MISC (CMD_BASE + 0x0068) + /* Normal operation mode */ + #define MISC_NORMAL 0x00000003 + /* Clear bit 0 to reset MAC */ + #define MISC_RESET_MAC 0x00000002 + /* Clear bit 1 to reset PHY */ + #define MISC_RESET_PHY 0x00000001 + /* Clear bit 0 and 1 to reset MAC and PHY */ + #define MISC_RESET_MAC_PHY 0x00000000 + #define DEFAULT_MISC MISC_NORMAL +#define MACID0 (CMD_BASE + 0x0070) +#define MACID1 (CMD_BASE + 0x0074) +#define MACID2 (CMD_BASE + 0x0078) +#define TXLEN (CMD_BASE + 0x007C) + #define DEFAULT_TXLEN 0x000005FC +#define RXFILTER (CMD_BASE + 0x0080) + #define RX_RXANY 0x00000001 + #define RX_MULTICAST 0x00000002 + #define RX_UNICAST 0x00000004 + #define RX_BROADCAST 0x00000008 + #define RX_MULTI_HASH 0x00000010 + #define DISABLE_RXFILTER 0x00000000 + #define DEFAULT_RXFILTER (RX_BROADCAST + RX_UNICAST) +#define MDIOCTRL (CMD_BASE + 0x0084) + #define PHY_ADDR_MASK 0x0000001F + #define REG_ADDR_MASK 0x00001F00 + #define READ_PHY 0x00004000 + #define WRITE_PHY 0x00008000 +#define MDIODP (CMD_BASE + 0x0088) +#define GPIOCTRL (CMD_BASE + 0x008C) +#define RXINDICATOR (CMD_BASE + 0x0090) + #define RX_START_READ 0x00000001 + #define RX_STOP_READ 0x00000000 + #define DEFAULT_RXINDICATOR RX_STOP_READ +#define TXST (CMD_BASE + 0x0094) +#define MDCCLKPAT (CMD_BASE + 0x00A0) +#define RXIPCRCCNT (CMD_BASE + 0x00A4) +#define RXCRCCNT (CMD_BASE + 0x00A8) +#define TXFAILCNT (CMD_BASE + 0x00AC) +#define PROMDP (CMD_BASE + 0x00B0) +#define PROMCTRL (CMD_BASE + 0x00B4) + #define RELOAD_EEPROM 0x00000200 +#define MAXRXLEN (CMD_BASE + 0x00B8) +#define HASHTAB0 (CMD_BASE + 0x00C0) +#define HASHTAB1 (CMD_BASE + 0x00C4) +#define HASHTAB2 (CMD_BASE + 0x00C8) +#define HASHTAB3 (CMD_BASE + 0x00CC) +#define DOGTHD0 (CMD_BASE + 0x00E0) + #define DEFAULT_DOGTHD0 0x0000FFFF +#define DOGTHD1 (CMD_BASE + 0x00E4) + #define START_WATCHDOG_TIMER 0x00008000 + #define DEFAULT_DOGTHD1 0x00000FFF +#define SOFTRST (CMD_BASE + 0x00EC) + #define SOFTRST_NORMAL 0x00000003 + #define SOFTRST_RESET_MAC 0x00000002 + +/* External PHY Register Definition */ +#define BMCR 0x0000 + #define LINE_SPEED_MSB 0x0040 + #define DUPLEX_MODE 0x0100 + #define RESTART_AUTONEG 0x0200 + #define POWER_DOWN 0x0800 + #define AUTONEG_EN 0x1000 + #define LINE_SPEED_LSB 0x2000 + #define PHY_RESET 0x8000 + + #define MEDIAMODE_MASK (LINE_SPEED_MSB | LINE_SPEED_LSB |\ + DUPLEX_MODE) + #define BMCR_SPEED_1000 LINE_SPEED_MSB + #define BMCR_SPEED_100 LINE_SPEED_LSB + #define BMCR_SPEED_10 0x0000 + + #define BMCR_1000FULL (BMCR_SPEED_1000 | DUPLEX_MODE) + #define BMCR_100FULL (BMCR_SPEED_100 | DUPLEX_MODE) + #define BMCR_100HALF BMCR_SPEED_100 + #define BMCR_10FULL DUPLEX_MODE + #define BMCR_10HALF 0x0000 +#define BMSR 0x0001 + #define LINKOK 0x0004 + #define AUTONEG_ENABLE_STS 0x0008 + #define AUTONEG_COMPLETE 0x0020 +#define PHYIDR0 0x0002 +#define PHYIDR1 0x0003 +#define ANAR 0x0004 + #define ANAR_PAUSE 0x0400 + #define ANAR_100FULL 0x0100 + #define ANAR_100HALF 0x0080 + #define ANAR_10FULL 0x0040 + #define ANAR_10HALF 0x0020 + #define ANAR_8023BIT 0x0001 +#define ANLPAR 0x0005 +#define ANER 0x0006 +#define AUX_1000_CTRL 0x0009 + #define ENABLE_1000HALF 0x0100 + #define ENABLE_1000FULL 0x0200 + #define DEFAULT_AUX_1000_CTRL (ENABLE_1000HALF | ENABLE_1000FULL) +#define AUX_1000_STATUS 0x000A + #define LP_1000HALF 0x0400 + #define LP_1000FULL 0x0800 + +/* Marvell 88E1111 Gigabit PHY Register Definition */ +#define M88_SSR 0x0011 + #define SSR_SPEED_MASK 0xC000 + #define SSR_SPEED_1000 0x8000 + #define SSR_SPEED_100 0x4000 + #define SSR_SPEED_10 0x0000 + #define SSR_DUPLEX 0x2000 + #define SSR_MEDIA_RESOLVED_OK 0x0800 + + #define SSR_MEDIA_MASK (SSR_SPEED_MASK | SSR_DUPLEX) + #define SSR_1000FULL (SSR_SPEED_1000 | SSR_DUPLEX) + #define SSR_1000HALF SSR_SPEED_1000 + #define SSR_100FULL (SSR_SPEED_100 | SSR_DUPLEX) + #define SSR_100HALF SSR_SPEED_100 + #define SSR_10FULL (SSR_SPEED_10 | SSR_DUPLEX) + #define SSR_10HALF SSR_SPEED_10 +#define M88_IER 0x0012 + #define LINK_CHANGE_INT 0x0400 +#define M88_ISR 0x0013 + #define LINK_CHANGE_STATUS 0x0400 +#define M88_EXT_SCR 0x0014 + #define RGMII_RXCLK_DELAY 0x0080 + #define RGMII_TXCLK_DELAY 0x0002 + #define DEFAULT_EXT_SCR (RGMII_TXCLK_DELAY | RGMII_RXCLK_DELAY) +#define M88_EXT_SSR 0x001B + #define HWCFG_MODE_MASK 0x000F + #define RGMII_COPPER_MODE 0x000B + +/* CICADA CIS8201 Gigabit PHY Register Definition */ +#define CIS_IMR 0x0019 + #define CIS_INT_ENABLE 0x8000 + #define CIS_LINK_CHANGE_INT 0x2000 +#define CIS_ISR 0x001A + #define CIS_INT_PENDING 0x8000 + #define CIS_LINK_CHANGE_STATUS 0x2000 +#define CIS_AUX_CTRL_STATUS 0x001C + #define CIS_AUTONEG_COMPLETE 0x8000 + #define CIS_SPEED_MASK 0x0018 + #define CIS_SPEED_1000 0x0010 + #define CIS_SPEED_100 0x0008 + #define CIS_SPEED_10 0x0000 + #define CIS_DUPLEX 0x0020 + + #define CIS_MEDIA_MASK (CIS_SPEED_MASK | CIS_DUPLEX) + #define CIS_1000FULL (CIS_SPEED_1000 | CIS_DUPLEX) + #define CIS_1000HALF CIS_SPEED_1000 + #define CIS_100FULL (CIS_SPEED_100 | CIS_DUPLEX) + #define CIS_100HALF CIS_SPEED_100 + #define CIS_10FULL (CIS_SPEED_10 | CIS_DUPLEX) + #define CIS_10HALF CIS_SPEED_10 + #define CIS_SMI_PRIORITY 0x0004 + +static inline unsigned short INW (struct eth_device *dev, unsigned long addr) +{ + return le16_to_cpu (*(volatile unsigned short *) (addr + dev->iobase)); +} + +static inline void OUTW (struct eth_device *dev, unsigned short command, unsigned long addr) +{ + *(volatile unsigned short *) ((addr + dev->iobase)) = cpu_to_le16 (command); +} + +/* + Access RXBUFFER_START/TXBUFFER_START to read RX buffer/write TX buffer +*/ +#if defined (CONFIG_DRIVER_AX88180_16BIT) +static inline unsigned short READ_RXBUF (struct eth_device *dev) +{ + return le16_to_cpu (*(volatile unsigned short *) (RXBUFFER_START + dev->iobase)); +} + +static inline void WRITE_TXBUF (struct eth_device *dev, unsigned short data) +{ + *(volatile unsigned short *) ((TXBUFFER_START + dev->iobase)) = cpu_to_le16 (data); +} +#else +static inline unsigned long READ_RXBUF (struct eth_device *dev) +{ + return le32_to_cpu (*(volatile unsigned long *) (RXBUFFER_START + dev->iobase)); +} + +static inline void WRITE_TXBUF (struct eth_device *dev, unsigned long data) +{ + *(volatile unsigned long *) ((TXBUFFER_START + dev->iobase)) = cpu_to_le32 (data); +} +#endif + +#endif /* _AX88180_H_ */ -- cgit v1.1 From fecb5ade3b37f62981f2b05b621005850173aaa9 Mon Sep 17 00:00:00 2001 From: Jason Jin Date: Fri, 19 Sep 2008 17:32:49 +0800 Subject: Fix the NAND size overflow issue. When the total size of all NAND devices exceeds 4 GiB, the size will overflow. This patch tries to fix this. Note that we still have a problem when a single NAND device is bigger than 4 GiB: then the overflow would actually happen earlier, i. e. when storing the size in nand_info[].size, as nand_info[].size is an "u_int32_t". Signed-off-by: Jason Jin Signed-off-by: Wolfgang Denk --- drivers/mtd/nand/nand.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c index ebd2acd..71a0e4b 100644 --- a/drivers/mtd/nand/nand.c +++ b/drivers/mtd/nand/nand.c @@ -63,11 +63,11 @@ void nand_init(void) unsigned int size = 0; for (i = 0; i < CFG_MAX_NAND_DEVICE; i++) { nand_init_chip(&nand_info[i], &nand_chip[i], base_address[i]); - size += nand_info[i].size; + size += nand_info[i].size / 1024; if (nand_curr_device == -1) nand_curr_device = i; } - printf("%u MiB\n", size / (1024 * 1024)); + printf("%u MiB\n", size / 1024); #ifdef CFG_NAND_SELECT_DEVICE /* -- cgit v1.1 From 81e612014c40c922ec35488d17c504d4e9286f06 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Tue, 23 Sep 2008 12:38:42 -0500 Subject: Remove CFG_EEPROM_PAGE* dependencies for temperature sensors The checks for CFG_EEPROM_PAGE_WRITE_ENABLE and CFG_EEPROM_PAGE_WRITE_BITS in various temperature sensor drivers are not necessary Signed-off-by: Peter Tyser --- drivers/hwmon/ds1621.c | 5 ----- drivers/hwmon/lm75.c | 6 ------ drivers/hwmon/lm81.c | 6 ------ 3 files changed, 17 deletions(-) (limited to 'drivers') diff --git a/drivers/hwmon/ds1621.c b/drivers/hwmon/ds1621.c index 749aa26..523f8be 100644 --- a/drivers/hwmon/ds1621.c +++ b/drivers/hwmon/ds1621.c @@ -26,11 +26,6 @@ */ #include - -#if !defined(CFG_EEPROM_PAGE_WRITE_ENABLE) || \ - (CFG_EEPROM_PAGE_WRITE_BITS < 1) -# error "CFG_EEPROM_PAGE_WRITE_ENABLE must be defined and CFG_EEPROM_PAGE_WRITE_BITS must be greater than 1 to use CONFIG_DTT_DS1621" -#endif #include #include diff --git a/drivers/hwmon/lm75.c b/drivers/hwmon/lm75.c index 67a18f6..6770cdd 100644 --- a/drivers/hwmon/lm75.c +++ b/drivers/hwmon/lm75.c @@ -26,12 +26,6 @@ */ #include - -#if !defined(CFG_EEPROM_PAGE_WRITE_ENABLE) || \ - (CFG_EEPROM_PAGE_WRITE_BITS < 1) -# error "CFG_EEPROM_PAGE_WRITE_ENABLE must be defined and CFG_EEPROM_PAGE_WRITE_BITS must be greater than 1 to use CONFIG_DTT_LM75" -#endif - #include #include diff --git a/drivers/hwmon/lm81.c b/drivers/hwmon/lm81.c index 9349eb6..668ee9f 100644 --- a/drivers/hwmon/lm81.c +++ b/drivers/hwmon/lm81.c @@ -31,12 +31,6 @@ */ #include - -#if !defined(CFG_EEPROM_PAGE_WRITE_ENABLE) || \ - (CFG_EEPROM_PAGE_WRITE_BITS < 1) -# error "CFG_EEPROM_PAGE_WRITE_ENABLE must be defined and CFG_EEPROM_PAGE_WRITE_BITS must be greater than 1 to use CONFIG_DTT_LM81" -#endif - #include #include -- cgit v1.1 From b4dbacf69a669a17487054552fc2761149dd6767 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 15 Oct 2008 15:50:45 +0200 Subject: Coding Style cleanup, update CHANGELOG, prepare 2008.10-rc3 Signed-off-by: Wolfgang Denk --- drivers/net/ax88180.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/ax88180.h b/drivers/net/ax88180.h index 5254e7d..d2113df 100644 --- a/drivers/net/ax88180.h +++ b/drivers/net/ax88180.h @@ -182,7 +182,7 @@ struct ax88180_private { #define RXCURT (CMD_BASE + 0x0034) #define DEFAULT_RXCURT 0x00000000 #define RXBOUND (CMD_BASE + 0x0038) - #define DEFAULT_RXBOUND 0x7FF //RX pages 0~7FFh + #define DEFAULT_RXBOUND 0x7FF /* RX pages 0~7FFh */ #define MACCFG0 (CMD_BASE + 0x0040) #define MACCFG0_BIT3_0 0x00000007 #define IPGT_VAL 0x00000150 -- cgit v1.1 From 9029b68f3f81b3013044f167ea025e836e6c8c0e Mon Sep 17 00:00:00 2001 From: Jason Jin Date: Wed, 15 Oct 2008 10:40:24 +0800 Subject: Fix the function conflict in x86emu when DEBUG is on The function parse_line() in common/main.c was exposed globally by commit 6636b62a6efc7f14e6e788788631ae7a7fca4537, Result in conflict with the same name funciton in drivers/bios_emulator/x86emu/debug.c when define the DEBUG. This patch fix this by renaming the function in the debug.c file. Signed-off-by: Jason Jin --- drivers/bios_emulator/x86emu/debug.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/bios_emulator/x86emu/debug.c b/drivers/bios_emulator/x86emu/debug.c index 5cbcc95..29fe3f1 100644 --- a/drivers/bios_emulator/x86emu/debug.c +++ b/drivers/bios_emulator/x86emu/debug.c @@ -50,7 +50,7 @@ static void print_encoded_bytes(u16 s, u16 o); static void print_decoded_instruction(void); -static int parse_line(char *s, int *ps, int *n); +static int x86emu_parse_line(char *s, int *ps, int *n); /* should look something like debug's output. */ void X86EMU_trace_regs(void) @@ -257,7 +257,7 @@ void x86emu_single_step(void) offset = M.x86.saved_ip; while (!done) { printk("-"); - cmd = parse_line(s, ps, &ntok); + cmd = x86emu_parse_line(s, ps, &ntok); switch (cmd) { case 'u': disassemble_forward(M.x86.saved_cs, (u16) offset, 10); @@ -331,7 +331,7 @@ int X86EMU_trace_off(void) return M.x86.debug &= ~(DEBUG_STEP_F | DEBUG_DECODE_F | DEBUG_TRACE_F); } -static int parse_line(char *s, int *ps, int *n) +static int x86emu_parse_line(char *s, int *ps, int *n) { int cmd; -- cgit v1.1 From 41410eee472b0f42e03a77f961bbc55ef58f3c01 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Wed, 24 Sep 2008 11:42:12 -0500 Subject: Change UEC PHY interface to RGMII on MPC8568MDS Change UEC phy interface from GMII to RGMII on MPC8568MDS board Because on MPC8568MDS, GMII interface is only recommended for 1000Mbps speed, but RGMII interface can work at 10/100/1000Mbps, and RGMII interface works more stable. Now both UEC1 and UEC2 can work properly under u-boot. It is also in consistent with the kernel setting for 8568 UEC phy interface. Signed-off-by: Haiying Wang Signed-off-by: Ben Warren --- drivers/qe/uec.c | 1 + drivers/qe/uec.h | 1 + drivers/qe/uec_phy.c | 24 ++++++++++++++++++++++++ drivers/qe/uec_phy.h | 8 ++++++++ 4 files changed, 34 insertions(+) (limited to 'drivers') diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index 344c649..85e2ad3 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -424,6 +424,7 @@ static int uec_set_mac_if_mode(uec_private_t *uec, enet_interface_e if_mode) upsmr |= (UPSMR_RPM | UPSMR_TBIM); break; case ENET_1000_RGMII_RXID: + case ENET_1000_RGMII_ID: case ENET_1000_RGMII: maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE; upsmr |= UPSMR_RPM; diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h index e357a92..0b64499 100644 --- a/drivers/qe/uec.h +++ b/drivers/qe/uec.h @@ -642,6 +642,7 @@ typedef enum enet_interface { ENET_100_RGMII, ENET_1000_GMII, ENET_1000_RGMII, + ENET_1000_RGMII_ID, ENET_1000_RGMII_RXID, ENET_1000_TBI, ENET_1000_RTBI diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c index 186922e..2243d3b 100644 --- a/drivers/qe/uec_phy.c +++ b/drivers/qe/uec_phy.c @@ -376,6 +376,29 @@ static int bcm_init(struct uec_mii_info *mii_info) return 0; } +static int marvell_init(struct uec_mii_info *mii_info) +{ + struct eth_device *edev = mii_info->dev; + uec_private_t *uec = edev->priv; + + if (uec->uec_info->enet_interface == ENET_1000_RGMII_ID) { + int temp; + + temp = phy_read(mii_info, MII_M1111_PHY_EXT_CR); + temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY); + phy_write(mii_info, MII_M1111_PHY_EXT_CR, temp); + + temp = phy_read(mii_info, MII_M1111_PHY_EXT_SR); + temp &= ~MII_M1111_HWCFG_MODE_MASK; + temp |= MII_M1111_HWCFG_MODE_RGMII; + phy_write(mii_info, MII_M1111_PHY_EXT_SR, temp); + + phy_write(mii_info, PHY_BMCR, PHY_BMCR_RESET); + } + + return 0; +} + static int marvell_read_status (struct uec_mii_info *mii_info) { u16 status; @@ -538,6 +561,7 @@ static struct phy_info phy_info_marvell = { .phy_id_mask = 0xffffff00, .name = "Marvell 88E11x1", .features = MII_GBIT_FEATURES, + .init = &marvell_init, .config_aneg = &marvell_config_aneg, .read_status = &marvell_read_status, .ack_interrupt = &marvell_ack_interrupt, diff --git a/drivers/qe/uec_phy.h b/drivers/qe/uec_phy.h index 6f769fb..7ac1ff9 100644 --- a/drivers/qe/uec_phy.h +++ b/drivers/qe/uec_phy.h @@ -77,6 +77,14 @@ #define MII_M1011_IMASK_INIT 0x6400 #define MII_M1011_IMASK_CLEAR 0x0000 +/* 88E1111 PHY Register */ +#define MII_M1111_PHY_EXT_CR 0x14 +#define MII_M1111_RX_DELAY 0x80 +#define MII_M1111_TX_DELAY 0x2 +#define MII_M1111_PHY_EXT_SR 0x1b +#define MII_M1111_HWCFG_MODE_MASK 0xf +#define MII_M1111_HWCFG_MODE_RGMII 0xb + #define MII_DM9161_SCR 0x10 #define MII_DM9161_SCR_INIT 0x0610 #define MII_DM9161_SCR_RMII_INIT 0x0710 -- cgit v1.1 From c68a05feeb88de9fcf158e67ff6423c4cc988f88 Mon Sep 17 00:00:00 2001 From: richardretanubun Date: Mon, 29 Sep 2008 18:28:23 -0400 Subject: Adds two more ethernet interface to 83xx Added as a convenience for other platforms that uses MPC8360 (has 8 UCC). Six eth interface is chosen because the platform I am using combines UCC1&2 and UCC3&4 as 1000 Eth and the other four UCCs as 10/100 Eth. Signed-off-by: Richard Retanubun Signed-off-by: Ben Warren --- drivers/qe/uec.c | 48 +++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 47 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index 85e2ad3..0d48360 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -123,8 +123,54 @@ static uec_info_t eth4_uec_info = { .enet_interface = CFG_UEC4_INTERFACE_MODE, }; #endif +#ifdef CONFIG_UEC_ETH5 +static uec_info_t eth5_uec_info = { + .uf_info = { + .ucc_num = CFG_UEC5_UCC_NUM, + .rx_clock = CFG_UEC5_RX_CLK, + .tx_clock = CFG_UEC5_TX_CLK, + .eth_type = CFG_UEC5_ETH_TYPE, + }, +#if (CFG_UEC5_ETH_TYPE == FAST_ETH) + .num_threads_tx = UEC_NUM_OF_THREADS_1, + .num_threads_rx = UEC_NUM_OF_THREADS_1, +#else + .num_threads_tx = UEC_NUM_OF_THREADS_4, + .num_threads_rx = UEC_NUM_OF_THREADS_4, +#endif + .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, + .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, + .tx_bd_ring_len = 16, + .rx_bd_ring_len = 16, + .phy_address = CFG_UEC5_PHY_ADDR, + .enet_interface = CFG_UEC5_INTERFACE_MODE, +}; +#endif +#ifdef CONFIG_UEC_ETH6 +static uec_info_t eth6_uec_info = { + .uf_info = { + .ucc_num = CFG_UEC6_UCC_NUM, + .rx_clock = CFG_UEC6_RX_CLK, + .tx_clock = CFG_UEC6_TX_CLK, + .eth_type = CFG_UEC6_ETH_TYPE, + }, +#if (CFG_UEC6_ETH_TYPE == FAST_ETH) + .num_threads_tx = UEC_NUM_OF_THREADS_1, + .num_threads_rx = UEC_NUM_OF_THREADS_1, +#else + .num_threads_tx = UEC_NUM_OF_THREADS_4, + .num_threads_rx = UEC_NUM_OF_THREADS_4, +#endif + .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, + .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, + .tx_bd_ring_len = 16, + .rx_bd_ring_len = 16, + .phy_address = CFG_UEC6_PHY_ADDR, + .enet_interface = CFG_UEC6_INTERFACE_MODE, +}; +#endif -#define MAXCONTROLLERS (4) +#define MAXCONTROLLERS (6) static struct eth_device *devlist[MAXCONTROLLERS]; -- cgit v1.1 From 1c6fe6eac75d695fde677af8330c0dbe75fb6a2b Mon Sep 17 00:00:00 2001 From: Dirk Eibach Date: Wed, 8 Oct 2008 13:44:27 +0200 Subject: hwmon: Add LM63 support This patch adds support for the National LM63 temperature sensor with integrated fan control. It's used on the GDSys Neo board (405EP) which will be submitted later. Signed-off-by: Dirk Eibach Acked-by: Stefan Roese --- drivers/hwmon/Makefile | 1 + drivers/hwmon/lm63.c | 174 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 175 insertions(+) create mode 100644 drivers/hwmon/lm63.c (limited to 'drivers') diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index 7f7d3db..59302fa 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -35,6 +35,7 @@ COBJS-$(CONFIG_DTT_ADT7460) += adt7460.o COBJS-$(CONFIG_DTT_DS1621) += ds1621.o COBJS-$(CONFIG_DTT_DS1722) += ds1722.o COBJS-$(CONFIG_DTT_DS1775) += ds1775.o +COBJS-$(CONFIG_DTT_LM63) += lm63.o COBJS-$(CONFIG_DTT_LM73) += lm73.o COBJS-$(CONFIG_DTT_LM75) += lm75.o COBJS-$(CONFIG_DTT_LM81) += lm81.o diff --git a/drivers/hwmon/lm63.c b/drivers/hwmon/lm63.c new file mode 100644 index 0000000..03616e1 --- /dev/null +++ b/drivers/hwmon/lm63.c @@ -0,0 +1,174 @@ +/* + * (C) Copyright 2007-2008 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * based on lm75.c by Bill Hunter + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * National LM63 Temperature Sensor + */ + +#include +#include +#include + +#define DTT_I2C_DEV_CODE 0x4C /* National LM63 device */ + +#define DTT_READ_TEMP_RMT_MSB 0x01 +#define DTT_CONFIG 0x03 +#define DTT_READ_TEMP_RMT_LSB 0x10 +#define DTT_TACHLIM_LSB 0x48 +#define DTT_TACHLIM_MSB 0x49 +#define DTT_FAN_CONFIG 0x4A +#define DTT_PWM_FREQ 0x4D +#define DTT_PWM_LOOKUP_BASE 0x50 + +struct pwm_lookup_entry { + u8 temp; + u8 pwm; +}; + +/* + * Device code + */ + +int dtt_read(int sensor, int reg) +{ + int dlen; + uchar data[2]; + + /* + * Calculate sensor address and register. + */ + sensor = DTT_I2C_DEV_CODE; /* address of lm63 is not adjustable */ + + dlen = 1; + + /* + * Now try to read the register. + */ + if (i2c_read(sensor, reg, 1, data, dlen) != 0) + return -1; + + return (int)data[0]; +} /* dtt_read() */ + +int dtt_write(int sensor, int reg, int val) +{ + int dlen; + uchar data[2]; + + /* + * Calculate sensor address and register. + */ + sensor = DTT_I2C_DEV_CODE; /* address of lm63 is not adjustable */ + + dlen = 1; + data[0] = (char)(val & 0xff); + + /* + * Write value to register. + */ + if (i2c_write(sensor, reg, 1, data, dlen) != 0) + return 1; + + return 0; +} /* dtt_write() */ + +static int _dtt_init(int sensor) +{ + int i; + int val; + + struct pwm_lookup_entry pwm_lookup[] = CONFIG_DTT_PWM_LOOKUPTABLE; + + /* + * Set PWM Frequency to 2.5% resolution + */ + val = 20; + if (dtt_write(sensor, DTT_PWM_FREQ, val) != 0) + return 1; + + /* + * Set Tachometer Limit + */ + val = CONFIG_DTT_TACH_LIMIT; + if (dtt_write(sensor, DTT_TACHLIM_LSB, val & 0xff) != 0) + return 1; + if (dtt_write(sensor, DTT_TACHLIM_MSB, (val >> 8) & 0xff) != 0) + return 1; + + /* + * Setup PWM Lookup-Table + */ + for (i = 0; i < sizeof(pwm_lookup) / sizeof(struct pwm_lookup_entry); + i++) { + int address = DTT_PWM_LOOKUP_BASE + 2 * i; + val = pwm_lookup[i].temp; + if (dtt_write(sensor, address, val) != 0) + return 1; + val = pwm_lookup[i].pwm; + if (dtt_write(sensor, address + 1, val) != 0) + return 1; + } + + /* + * Enable PWM Lookup-Table, PWM Clock 360 kHz, Tachometer Mode 2 + */ + val = 0x02; + if (dtt_write(sensor, DTT_FAN_CONFIG, val) != 0) + return 1; + + /* + * Enable Tach input + */ + val = dtt_read(sensor, DTT_CONFIG) | 0x04; + if (dtt_write(sensor, DTT_CONFIG, val) != 0) + return 1; + + return 0; +} + +int dtt_get_temp(int sensor) +{ + s16 temp = (dtt_read(sensor, DTT_READ_TEMP_RMT_MSB) << 8) + | (dtt_read(sensor, DTT_READ_TEMP_RMT_LSB)); + + /* Ignore LSB for now, U-Boot only prints natural numbers */ + return temp >> 8; +} + +int dtt_init(void) +{ + int i; + unsigned char sensors[] = CONFIG_DTT_SENSORS; + const char *const header = "DTT: "; + + for (i = 0; i < sizeof(sensors); i++) { + if (_dtt_init(sensors[i]) != 0) + printf("%s%d FAILED INIT\n", header, i + 1); + else + printf("%s%d is %i C\n", header, i + 1, + dtt_get_temp(sensors[i])); + } + + return 0; +} -- cgit v1.1 From 799b784aa00cb03a352847ab9f9acdde79b72d21 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Wed, 15 Oct 2008 09:34:45 +0200 Subject: i2c: add CONFIG_I2C_MULTI_BUS for soft_i2c and mpc8260 i2c driver. Signed-off-by: Heiko Schocher --- drivers/i2c/soft_i2c.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'drivers') diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index 23db2ee..57736da 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -68,6 +68,10 @@ DECLARE_GLOBAL_DATA_PTR; #define PRINTD(fmt,args...) #endif +#if defined(CONFIG_I2C_MULTI_BUS) +static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0; +#endif /* CONFIG_I2C_MULTI_BUS */ + /*----------------------------------------------------------------------- * Local functions */ @@ -230,6 +234,38 @@ static int write_byte(uchar data) return(nack); /* not a nack is an ack */ } +#if defined(CONFIG_I2C_MULTI_BUS) +/* + * Functions for multiple I2C bus handling + */ +unsigned int i2c_get_bus_num(void) +{ + return i2c_bus_num; +} + +int i2c_set_bus_num(unsigned int bus) +{ + if (bus >= CFG_MAX_I2C_BUS) + return -1; + i2c_bus_num = bus; + + return 0; +} + +/* TODO: add 100/400k switching */ +unsigned int i2c_get_bus_speed(void) +{ + return CFG_I2C_SPEED; +} + +int i2c_set_bus_speed(unsigned int speed) +{ + if (speed != CFG_I2C_SPEED) + return -1; + + return 0; +} +#endif /*----------------------------------------------------------------------- * if ack == I2C_ACK, ACK the byte so can continue reading, else -- cgit v1.1 From 98aed379586a155292efbf3209356836584b601c Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Wed, 15 Oct 2008 09:35:26 +0200 Subject: soft_i2c: prevent compiler warnings if driver does not use CPU Pins. This patch fixes the following warnings, when using the soft_i2c driver using no CPU pins on MPC82xx or MPC8xx systems: soft_i2c.c: In function 'send_reset': soft_i2c.c:93: warning: unused variable 'immr' soft_i2c.c: In function 'send_start': soft_i2c.c:124: warning: unused variable 'immr' soft_i2c.c: In function 'send_stop': soft_i2c.c:146: warning: unused variable 'immr' soft_i2c.c: In function 'send_ack': soft_i2c.c:171: warning: unused variable 'immr' soft_i2c.c: In function 'write_byte': soft_i2c.c:196: warning: unused variable 'immr' soft_i2c.c: In function 'read_byte': soft_i2c.c:244: warning: unused variable 'immr' Signed-off-by: Heiko Schocher --- drivers/i2c/soft_i2c.c | 43 ++++++------------------------------------- 1 file changed, 6 insertions(+), 37 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index 57736da..19c364b 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -82,7 +82,6 @@ static void send_ack (int); static int write_byte (uchar byte); static uchar read_byte (int); - /*----------------------------------------------------------------------- * Send a reset sequence consisting of 9 clocks with the data signal high * to clock any confused device back into an idle state. Also send a @@ -90,12 +89,7 @@ static uchar read_byte (int); */ static void send_reset(void) { -#ifdef CONFIG_MPC8260 - volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT); -#endif -#ifdef CONFIG_8xx - volatile immap_t *immr = (immap_t *)CFG_IMMR; -#endif + I2C_SOFT_DECLARATIONS /* intentional without ';' */ int j; I2C_SCL(1); @@ -121,12 +115,7 @@ static void send_reset(void) */ static void send_start(void) { -#ifdef CONFIG_MPC8260 - volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT); -#endif -#ifdef CONFIG_8xx - volatile immap_t *immr = (immap_t *)CFG_IMMR; -#endif + I2C_SOFT_DECLARATIONS /* intentional without ';' */ I2C_DELAY; I2C_SDA(1); @@ -143,12 +132,7 @@ static void send_start(void) */ static void send_stop(void) { -#ifdef CONFIG_MPC8260 - volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT); -#endif -#ifdef CONFIG_8xx - volatile immap_t *immr = (immap_t *)CFG_IMMR; -#endif + I2C_SOFT_DECLARATIONS /* intentional without ';' */ I2C_SCL(0); I2C_DELAY; @@ -168,12 +152,7 @@ static void send_stop(void) */ static void send_ack(int ack) { -#ifdef CONFIG_MPC8260 - volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT); -#endif -#ifdef CONFIG_8xx - volatile immap_t *immr = (immap_t *)CFG_IMMR; -#endif + I2C_SOFT_DECLARATIONS /* intentional without ';' */ I2C_SCL(0); I2C_DELAY; @@ -193,12 +172,7 @@ static void send_ack(int ack) */ static int write_byte(uchar data) { -#ifdef CONFIG_MPC8260 - volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT); -#endif -#ifdef CONFIG_8xx - volatile immap_t *immr = (immap_t *)CFG_IMMR; -#endif + I2C_SOFT_DECLARATIONS /* intentional without ';' */ int j; int nack; @@ -273,12 +247,7 @@ int i2c_set_bus_speed(unsigned int speed) */ static uchar read_byte(int ack) { -#ifdef CONFIG_MPC8260 - volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT); -#endif -#ifdef CONFIG_8xx - volatile immap_t *immr = (immap_t *)CFG_IMMR; -#endif + I2C_SOFT_DECLARATIONS /* intentional without ';' */ int data; int j; -- cgit v1.1 From 12f1678127c1df2b2878ba93c88948bedc060775 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Wed, 15 Oct 2008 09:37:04 +0200 Subject: lm75: fix Codingstyle issues. Signed-off-by: Heiko Schocher --- drivers/hwmon/lm75.c | 222 +++++++++++++++++++++++---------------------------- 1 file changed, 99 insertions(+), 123 deletions(-) (limited to 'drivers') diff --git a/drivers/hwmon/lm75.c b/drivers/hwmon/lm75.c index 6770cdd..f544ebb 100644 --- a/drivers/hwmon/lm75.c +++ b/drivers/hwmon/lm75.c @@ -44,159 +44,135 @@ int dtt_read(int sensor, int reg) { - int dlen; - uchar data[2]; + int dlen; + uchar data[2]; #ifdef CONFIG_DTT_AD7414 - /* - * On AD7414 the first value upon bootup is not read correctly. - * This is most likely because of the 800ms update time of the - * temp register in normal update mode. To get current values - * each time we issue the "dtt" command including upon powerup - * we switch into one-short mode. - * - * Issue one-shot mode command - */ - dtt_write(sensor, DTT_CONFIG, 0x64); + /* + * On AD7414 the first value upon bootup is not read correctly. + * This is most likely because of the 800ms update time of the + * temp register in normal update mode. To get current values + * each time we issue the "dtt" command including upon powerup + * we switch into one-short mode. + * + * Issue one-shot mode command + */ + dtt_write(sensor, DTT_CONFIG, 0x64); #endif - /* - * Validate 'reg' param - */ - if((reg < 0) || (reg > 3)) - return -1; - - /* - * Calculate sensor address and register. - */ - sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); /* calculate address of lm75 */ - - /* - * Prepare to handle 2 byte result. - */ - if ((reg == DTT_READ_TEMP) || - (reg == DTT_TEMP_HYST) || - (reg == DTT_TEMP_SET)) - dlen = 2; - else - dlen = 1; - - /* - * Now try to read the register. - */ - if (i2c_read(sensor, reg, 1, data, dlen) != 0) - return -1; - - /* - * Handle 2 byte result. - */ - if (dlen == 2) - return ((int)((short)data[1] + (((short)data[0]) << 8))); - - - return (int)data[0]; + /* Validate 'reg' param */ + if((reg < 0) || (reg > 3)) + return -1; + + /* Calculate sensor address and register. */ + sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); + + /* Prepare to handle 2 byte result. */ + if ((reg == DTT_READ_TEMP) || + (reg == DTT_TEMP_HYST) || + (reg == DTT_TEMP_SET)) + dlen = 2; + else + dlen = 1; + + /* Now try to read the register. */ + if (i2c_read(sensor, reg, 1, data, dlen) != 0) + return -1; + + /* Handle 2 byte result. */ + if (dlen == 2) + return ((int)((short)data[1] + (((short)data[0]) << 8))); + + return (int)data[0]; } /* dtt_read() */ int dtt_write(int sensor, int reg, int val) { - int dlen; - uchar data[2]; - - /* - * Validate 'reg' param - */ - if ((reg < 0) || (reg > 3)) - return 1; - - /* - * Calculate sensor address and register. - */ - sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); /* calculate address of lm75 */ - - /* - * Handle 2 byte values. - */ - if ((reg == DTT_READ_TEMP) || - (reg == DTT_TEMP_HYST) || - (reg == DTT_TEMP_SET)) { - dlen = 2; - data[0] = (char)((val >> 8) & 0xff); /* MSB first */ - data[1] = (char)(val & 0xff); - } else { - dlen = 1; - data[0] = (char)(val & 0xff); - } - - /* - * Write value to register. - */ - if (i2c_write(sensor, reg, 1, data, dlen) != 0) - return 1; - - return 0; + int dlen; + uchar data[2]; + + /* Validate 'reg' param */ + if ((reg < 0) || (reg > 3)) + return 1; + + /* Calculate sensor address and register. */ + sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); + + /* Handle 2 byte values. */ + if ((reg == DTT_READ_TEMP) || + (reg == DTT_TEMP_HYST) || + (reg == DTT_TEMP_SET)) { + dlen = 2; + data[0] = (char)((val >> 8) & 0xff); /* MSB first */ + data[1] = (char)(val & 0xff); + } else { + dlen = 1; + data[0] = (char)(val & 0xff); + } + + /* Write value to register. */ + if (i2c_write(sensor, reg, 1, data, dlen) != 0) + return 1; + + return 0; } /* dtt_write() */ static int _dtt_init(int sensor) { - int val; - - /* - * Setup TSET ( trip point ) register - */ - val = ((CFG_DTT_MAX_TEMP * 2) << 7) & 0xff80; /* trip */ - if (dtt_write(sensor, DTT_TEMP_SET, val) != 0) - return 1; - - /* - * Setup THYST ( untrip point ) register - Hysteresis - */ - val = (((CFG_DTT_MAX_TEMP - CFG_DTT_HYSTERESIS) * 2) << 7) & 0xff80; - if (dtt_write(sensor, DTT_TEMP_HYST, val) != 0) - return 1; - - /* - * Setup configuraton register - */ + int val; + + /* Setup TSET ( trip point ) register */ + val = ((CFG_DTT_MAX_TEMP * 2) << 7) & 0xff80; /* trip */ + if (dtt_write(sensor, DTT_TEMP_SET, val) != 0) + return 1; + + /* Setup THYST ( untrip point ) register - Hysteresis */ + val = (((CFG_DTT_MAX_TEMP - CFG_DTT_HYSTERESIS) * 2) << 7) & 0xff80; + if (dtt_write(sensor, DTT_TEMP_HYST, val) != 0) + return 1; + + /* Setup configuraton register */ #ifdef CONFIG_DTT_AD7414 - /* config = alert active low and disabled */ - val = 0x60; + /* config = alert active low and disabled */ + val = 0x60; #else - /* config = 6 sample integration, int mode, active low, and enable */ - val = 0x18; + /* config = 6 sample integration, int mode, active low, and enable */ + val = 0x18; #endif - if (dtt_write(sensor, DTT_CONFIG, val) != 0) - return 1; + if (dtt_write(sensor, DTT_CONFIG, val) != 0) + return 1; - return 0; + return 0; } /* _dtt_init() */ int dtt_init (void) { - int i; - unsigned char sensors[] = CONFIG_DTT_SENSORS; - const char *const header = "DTT: "; + int i; + unsigned char sensors[] = CONFIG_DTT_SENSORS; + const char *const header = "DTT: "; + int old_bus; - for (i = 0; i < sizeof(sensors); i++) { + for (i = 0; i < sizeof(sensors); i++) { if (_dtt_init(sensors[i]) != 0) - printf("%s%d FAILED INIT\n", header, i+1); + printf("%s%d FAILED INIT\n", header, i+1); else - printf("%s%d is %i C\n", header, i+1, - dtt_get_temp(sensors[i])); - } + printf("%s%d is %i C\n", header, i+1, + dtt_get_temp(sensors[i])); + } - return (0); + return (0); } /* dtt_init() */ int dtt_get_temp(int sensor) { - int const ret = dtt_read(sensor, DTT_READ_TEMP); + int const ret = dtt_read(sensor, DTT_READ_TEMP); - if (ret < 0) { - printf("DTT temperature read failed.\n"); - return 0; - } - return (int)((int16_t) ret / 256); + if (ret < 0) { + printf("DTT temperature read failed.\n"); + return 0; + } + return (int)((int16_t) ret / 256); } /* dtt_get_temp() */ -- cgit v1.1 From 8e442df438ab677057571e3ac01846bff7719bce Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Wed, 15 Oct 2008 09:37:34 +0200 Subject: lm75: Make the LM75 MULTI_BUS compatible. Signed-off-by: Heiko Schocher --- drivers/hwmon/lm75.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers') diff --git a/drivers/hwmon/lm75.c b/drivers/hwmon/lm75.c index f544ebb..17379e5 100644 --- a/drivers/hwmon/lm75.c +++ b/drivers/hwmon/lm75.c @@ -155,6 +155,10 @@ int dtt_init (void) const char *const header = "DTT: "; int old_bus; + /* switch to correct I2C bus */ + old_bus = I2C_GET_BUS(); + I2C_SET_BUS(CFG_DTT_BUS_NUM); + for (i = 0; i < sizeof(sensors); i++) { if (_dtt_init(sensors[i]) != 0) printf("%s%d FAILED INIT\n", header, i+1); @@ -162,6 +166,8 @@ int dtt_init (void) printf("%s%d is %i C\n", header, i+1, dtt_get_temp(sensors[i])); } + /* switch back to original I2C bus */ + I2C_SET_BUS(old_bus); return (0); } /* dtt_init() */ -- cgit v1.1 From 4ca107effebfbabac1057c39632105dacef95957 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Wed, 15 Oct 2008 09:38:38 +0200 Subject: soft_i2c: Add CFG_I2C_INIT_BOARD option This patch adds the option for a boardspecific I2C deblocking mechanism for the soft i2c driver. Signed-off-by: Heiko Schocher --- drivers/i2c/soft_i2c.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'drivers') diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index 19c364b..63e6a7b 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -75,13 +75,16 @@ static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0; /*----------------------------------------------------------------------- * Local functions */ +#if !defined(CFG_I2C_INIT_BOARD) static void send_reset (void); +#endif static void send_start (void); static void send_stop (void); static void send_ack (int); static int write_byte (uchar byte); static uchar read_byte (int); +#if !defined(CFG_I2C_INIT_BOARD) /*----------------------------------------------------------------------- * Send a reset sequence consisting of 9 clocks with the data signal high * to clock any confused device back into an idle state. Also send a @@ -109,6 +112,7 @@ static void send_reset(void) send_stop(); I2C_TRISTATE; } +#endif /*----------------------------------------------------------------------- * START: High -> Low on SDA while SCL is High @@ -280,6 +284,12 @@ static uchar read_byte(int ack) */ void i2c_init (int speed, int slaveaddr) { +#if defined(CFG_I2C_INIT_BOARD) + /* call board specific i2c bus reset routine before accessing the */ + /* environment, which might be in a chip on that bus. For details */ + /* about this problem see doc/I2C_Edge_Conditions. */ + i2c_init_board(); +#else /* * WARNING: Do NOT save speed in a static variable: if the * I2C routines are called before RAM is initialized (to read @@ -287,6 +297,7 @@ void i2c_init (int speed, int slaveaddr) * system will crash. */ send_reset (); +#endif } /*----------------------------------------------------------------------- -- cgit v1.1 From 67b23a322848d828a5e45c0567b72762bfde7abf Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Wed, 15 Oct 2008 09:39:47 +0200 Subject: I2C: adding new "i2c bus" Command to the I2C Subsystem. With this Command it is possible to add new I2C Busses, which are behind 1 .. n I2C Muxes. Details see README. Signed-off-by: Heiko Schocher --- drivers/i2c/soft_i2c.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index 63e6a7b..0a9feb6 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -223,10 +223,23 @@ unsigned int i2c_get_bus_num(void) int i2c_set_bus_num(unsigned int bus) { +#if defined(CONFIG_I2C_MUX) + if (bus < CFG_MAX_I2C_BUS) { + i2c_bus_num = bus; + } else { + int ret; + + ret = i2x_mux_select_mux(bus); + if (ret == 0) + i2c_bus_num = bus; + else + return ret; + } +#else if (bus >= CFG_MAX_I2C_BUS) return -1; i2c_bus_num = bus; - +#endif return 0; } -- cgit v1.1 From 6d0f6bcf337c5261c08fabe12982178c2c489d76 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Thu, 16 Oct 2008 15:01:15 +0200 Subject: rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- drivers/block/ahci.c | 2 +- drivers/block/ata_piix.c | 30 +++++----- drivers/block/ata_piix.h | 2 +- drivers/block/fsl_sata.c | 16 +++--- drivers/block/sata_sil3114.c | 4 +- drivers/block/sil680.c | 28 +++++----- drivers/block/sym53c8xx.c | 6 +- drivers/block/systemace.c | 28 +++++----- drivers/hwmon/adm1021.c | 4 +- drivers/hwmon/ds1621.c | 4 +- drivers/hwmon/ds1775.c | 6 +- drivers/hwmon/lm73.c | 4 +- drivers/hwmon/lm75.c | 10 ++-- drivers/i2c/fsl_i2c.c | 22 ++++---- drivers/i2c/mxc_i2c.c | 8 +-- drivers/i2c/omap1510_i2c.c | 4 +- drivers/i2c/omap24xx_i2c.c | 4 +- drivers/i2c/soft_i2c.c | 18 +++--- drivers/i2c/tsi108_i2c.c | 20 +++---- drivers/input/i8042.c | 6 +- drivers/input/keyboard.c | 4 +- drivers/input/ps2ser.c | 12 ++-- drivers/misc/fsl_law.c | 6 +- drivers/misc/ns87308.c | 72 ++++++++++++------------ drivers/mmc/atmel_mci.c | 22 ++++---- drivers/mtd/cfi_flash.c | 102 +++++++++++++++++----------------- drivers/mtd/dataflash.c | 14 ++--- drivers/mtd/jedec_flash.c | 8 +-- drivers/mtd/nand/fsl_elbc_nand.c | 2 +- drivers/mtd/nand/nand.c | 14 ++--- drivers/mtd/nand/nand_base.c | 6 +- drivers/mtd/nand/s3c64xx.c | 12 ++-- drivers/mtd/nand_legacy/nand_legacy.c | 12 ++-- drivers/mtd/onenand/onenand_uboot.c | 2 +- drivers/mtd/spi/spi_flash_internal.h | 6 +- drivers/mtd/spi/stmicro.c | 2 +- drivers/net/bcm570x.c | 14 ++--- drivers/net/bfin_mac.c | 2 +- drivers/net/cs8900.c | 6 +- drivers/net/dm9000x.c | 2 +- drivers/net/eepro100.c | 32 +++++------ drivers/net/fsl_mcdmafec.c | 60 ++++++++++---------- drivers/net/lan91c96.c | 2 +- drivers/net/macb.c | 44 +++++++-------- drivers/net/mcffec.c | 64 ++++++++++----------- drivers/net/ne2000_base.c | 2 +- drivers/net/netarm_eth.c | 4 +- drivers/net/ns7520_eth.c | 4 +- drivers/net/ns9750_eth.c | 4 +- drivers/net/phy/miiphybb.c | 6 +- drivers/net/sk98lin/h/skdrv1st.h | 2 +- drivers/net/sk98lin/h/skgehw.h | 6 +- drivers/net/sk98lin/skgeinit.c | 4 +- drivers/net/sk98lin/u-boot_compat.h | 2 +- drivers/net/smc91111.c | 2 +- drivers/net/tsec.c | 10 ++-- drivers/net/tsi108_eth.c | 2 +- drivers/net/vsc7385.c | 12 ++-- drivers/pci/pci.c | 2 +- drivers/pci/pci_auto.c | 8 +-- drivers/pci/tsi108_pci.c | 38 ++++++------- drivers/pci/w83c553f.c | 4 +- drivers/pcmcia/i82365.c | 12 ++-- drivers/pcmcia/marubun_pcmcia.c | 32 +++++------ drivers/pcmcia/mpc8xx_pcmcia.c | 32 +++++------ drivers/pcmcia/pxa_pcmcia.c | 12 ++-- drivers/pcmcia/ti_pci1410a.c | 14 ++--- drivers/pcmcia/tqm8xx_pcmcia.c | 26 ++++----- drivers/qe/uec.c | 84 ++++++++++++++-------------- drivers/rtc/ds1306.c | 16 +++--- drivers/rtc/ds1307.c | 10 ++-- drivers/rtc/ds1337.c | 8 +-- drivers/rtc/ds1374.c | 18 +++--- drivers/rtc/ds1556.c | 2 +- drivers/rtc/ds164x.c | 2 +- drivers/rtc/ds174x.c | 2 +- drivers/rtc/ds3231.c | 4 +- drivers/rtc/isl1208.c | 4 +- drivers/rtc/m41t11.c | 48 ++++++++-------- drivers/rtc/m41t60.c | 16 +++--- drivers/rtc/m41t62.c | 6 +- drivers/rtc/m48t35ax.c | 4 +- drivers/rtc/max6900.c | 8 +-- drivers/rtc/mc146818.c | 8 +-- drivers/rtc/mcfrtc.c | 8 +-- drivers/rtc/mpc5xxx.c | 4 +- drivers/rtc/mpc8xx.c | 4 +- drivers/rtc/pcf8563.c | 4 +- drivers/rtc/pl031.c | 8 +-- drivers/rtc/rs5c372.c | 12 ++-- drivers/rtc/rx8025.c | 10 ++-- drivers/rtc/x1205.c | 4 +- drivers/serial/mcfuart.c | 10 ++-- drivers/serial/ns16550.c | 4 +- drivers/serial/serial.c | 42 +++++++------- drivers/spi/mpc8xxx_spi.c | 4 +- drivers/spi/soft_spi.c | 10 ++-- drivers/usb/sl811_usb.c | 4 +- drivers/usb/usb_ohci.c | 30 +++++----- drivers/usb/usb_ohci.h | 6 +- drivers/usb/usbdcore_mpc8xx.c | 20 +++---- drivers/video/ati_radeon_fb.c | 6 +- drivers/video/cfb_console.c | 12 ++-- drivers/video/ct69000.c | 2 +- drivers/video/mb862xx.c | 2 +- drivers/video/smiLynxEM.c | 6 +- drivers/video/videomodes.c | 2 +- drivers/video/videomodes.h | 4 +- 108 files changed, 723 insertions(+), 723 deletions(-) (limited to 'drivers') diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index 52fd108..2445e8c 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -676,7 +676,7 @@ void scsi_low_level_init(int busdevfunc) linkmap = probe_ent->link_port_map; - for (i = 0; i < CFG_SCSI_MAX_SCSI_ID; i++) { + for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) { if (((linkmap >> i) & 0x01)) { if (ahci_port_start((u8) i)) { printf("Can not start port %d\n", i); diff --git a/drivers/block/ata_piix.c b/drivers/block/ata_piix.c index 4c26b36..ec37687 100644 --- a/drivers/block/ata_piix.c +++ b/drivers/block/ata_piix.c @@ -35,7 +35,7 @@ #include #include -extern block_dev_desc_t sata_dev_desc[CFG_SATA_MAX_DEVICE]; +extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE]; extern int curr_device; #define DEBUG_SATA 0 /*For debug prints set DEBUG_SATA to 1 */ @@ -173,10 +173,10 @@ init_sata (int dev) iobase4 | ATA_PCI_CTL_OFS; port[1].ioaddr.bmdma_addr = iobase5 + 0x8; - for (i = 0; i < CFG_SATA_MAXBUS; i++) + for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++) sata_port (&port[i].ioaddr); - for (i = 0; i < CFG_SATA_MAXBUS; i++) { + for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++) { if (!(sata_bus_probe (i))) { port[i].port_state = 0; printf ("SATA#%d port is not present \n", i); @@ -190,15 +190,15 @@ init_sata (int dev) } } - for (i = 0; i < CFG_SATA_MAXBUS; i++) { + for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++) { u8 j, devno; if (port[i].port_state == 0) continue; - for (j = 0; j < CFG_SATA_DEVS_PER_BUS; j++) { + for (j = 0; j < CONFIG_SYS_SATA_DEVS_PER_BUS; j++) { sata_identify (i, j); set_Feature_cmd (i, j); - devno = i * CFG_SATA_DEVS_PER_BUS + j; + devno = i * CONFIG_SYS_SATA_DEVS_PER_BUS + j; if ((sata_dev_desc[devno].lba > 0) && (sata_dev_desc[devno].blksz > 0)) { dev_print (&sata_dev_desc[devno]); @@ -206,7 +206,7 @@ init_sata (int dev) init_part (&sata_dev_desc[devno]); if (curr_device < 0) curr_device = - i * CFG_SATA_DEVS_PER_BUS + j; + i * CONFIG_SYS_SATA_DEVS_PER_BUS + j; } } } @@ -271,7 +271,7 @@ sata_bus_softreset (int num) port[num].dev_mask = 0; - for (i = 0; i < CFG_SATA_DEVS_PER_BUS; i++) { + for (i = 0; i < CONFIG_SYS_SATA_DEVS_PER_BUS; i++) { if (!(sata_devchk (&port[num].ioaddr, i))) { PRINTF ("dev_chk failed for dev#%d\n", i); } else { @@ -328,7 +328,7 @@ sata_bus_softreset (int num) void sata_identify (int num, int dev) { - u8 cmd = 0, status = 0, devno = num * CFG_SATA_DEVS_PER_BUS + dev; + u8 cmd = 0, status = 0, devno = num * CONFIG_SYS_SATA_DEVS_PER_BUS + dev; u16 iobuf[ATA_SECT_SIZE]; u64 n_sectors = 0; u8 mask = 0; @@ -564,10 +564,10 @@ sata_read (int device, ulong blknr,lbaint_t blkcnt, void * buff) } #endif /*Port Number */ - num = device / CFG_SATA_DEVS_PER_BUS; + num = device / CONFIG_SYS_SATA_DEVS_PER_BUS; /*dev on the port */ - if (device >= CFG_SATA_DEVS_PER_BUS) - dev = device - CFG_SATA_DEVS_PER_BUS; + if (device >= CONFIG_SYS_SATA_DEVS_PER_BUS) + dev = device - CONFIG_SYS_SATA_DEVS_PER_BUS; else dev = device; @@ -671,10 +671,10 @@ sata_write (int device, ulong blknr,lbaint_t blkcnt, void * buff) } #endif /*Port Number */ - num = device / CFG_SATA_DEVS_PER_BUS; + num = device / CONFIG_SYS_SATA_DEVS_PER_BUS; /*dev on the Port */ - if (device >= CFG_SATA_DEVS_PER_BUS) - dev = device - CFG_SATA_DEVS_PER_BUS; + if (device >= CONFIG_SYS_SATA_DEVS_PER_BUS) + dev = device - CONFIG_SYS_SATA_DEVS_PER_BUS; else dev = device; diff --git a/drivers/block/ata_piix.h b/drivers/block/ata_piix.h index f9f0194..11885af 100644 --- a/drivers/block/ata_piix.h +++ b/drivers/block/ata_piix.h @@ -88,7 +88,7 @@ int init_sata (int dev); #endif #ifdef DRV_DECL /*Defines Driver Specific variables */ -struct sata_port port[CFG_SATA_MAXBUS]; +struct sata_port port[CONFIG_SYS_SATA_MAXBUS]; #endif #endif /* __ATA_PIIX_H__ */ diff --git a/drivers/block/fsl_sata.c b/drivers/block/fsl_sata.c index 55f593a..2009d1e 100644 --- a/drivers/block/fsl_sata.c +++ b/drivers/block/fsl_sata.c @@ -26,23 +26,23 @@ #include #include "fsl_sata.h" -extern block_dev_desc_t sata_dev_desc[CFG_SATA_MAX_DEVICE]; +extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE]; -#ifndef CFG_SATA1_FLAGS - #define CFG_SATA1_FLAGS FLAGS_DMA +#ifndef CONFIG_SYS_SATA1_FLAGS + #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA #endif -#ifndef CFG_SATA2_FLAGS - #define CFG_SATA2_FLAGS FLAGS_DMA +#ifndef CONFIG_SYS_SATA2_FLAGS + #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA #endif static struct fsl_sata_info fsl_sata_info[] = { #ifdef CONFIG_SATA1 - {CFG_SATA1, CFG_SATA1_FLAGS}, + {CONFIG_SYS_SATA1, CONFIG_SYS_SATA1_FLAGS}, #else {0, 0}, #endif #ifdef CONFIG_SATA2 - {CFG_SATA2, CFG_SATA2_FLAGS}, + {CONFIG_SYS_SATA2, CONFIG_SYS_SATA2_FLAGS}, #else {0, 0}, #endif @@ -123,7 +123,7 @@ int init_sata(int dev) int i; fsl_sata_t *sata; - if (dev < 0 || dev > (CFG_SATA_MAX_DEVICE - 1)) { + if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) { printf("the sata index %d is out of ranges\n\r", dev); return -1; } diff --git a/drivers/block/sata_sil3114.c b/drivers/block/sata_sil3114.c index 8399737..351cf99 100644 --- a/drivers/block/sata_sil3114.c +++ b/drivers/block/sata_sil3114.c @@ -48,9 +48,9 @@ static u8 sata_chk_status (struct sata_ioports *ioaddr, u8 usealtstatus); static void msleep (int count); static u32 iobase[6] = { 0, 0, 0, 0, 0, 0}; /* PCI BAR registers for device */ -extern block_dev_desc_t sata_dev_desc[CFG_SATA_MAX_DEVICE]; +extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE]; -static struct sata_port port[CFG_SATA_MAX_DEVICE]; +static struct sata_port port[CONFIG_SYS_SATA_MAX_DEVICE]; static void output_data (struct sata_ioports *ioaddr, u16 * sect_buf, int words) { diff --git a/drivers/block/sil680.c b/drivers/block/sil680.c index 052c3d3..e21fb9b 100644 --- a/drivers/block/sil680.c +++ b/drivers/block/sil680.c @@ -32,25 +32,25 @@ * #define CONFIG_PCI_PNP * NOTE it may also be necessary to define this if the default of 8 is * incorrect for the target board (e.g. the sequoia board requires 0). - * #define CFG_PCI_CACHE_LINE_SIZE 0 + * #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 * * #define CONFIG_CMD_IDE * #undef CONFIG_IDE_8xx_DIRECT * #undef CONFIG_IDE_LED * #undef CONFIG_IDE_RESET * #define CONFIG_IDE_PREINIT - * #define CFG_IDE_MAXBUS 2 - modify to suit - * #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) - modify to suit - * #define CFG_ATA_BASE_ADDR 0 - * #define CFG_ATA_IDE0_OFFSET 0 - * #define CFG_ATA_IDE1_OFFSET 0 - * #define CFG_ATA_DATA_OFFSET 0 - * #define CFG_ATA_REG_OFFSET 0 - * #define CFG_ATA_ALT_OFFSET 0x0004 + * #define CONFIG_SYS_IDE_MAXBUS 2 - modify to suit + * #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) - modify to suit + * #define CONFIG_SYS_ATA_BASE_ADDR 0 + * #define CONFIG_SYS_ATA_IDE0_OFFSET 0 + * #define CONFIG_SYS_ATA_IDE1_OFFSET 0 + * #define CONFIG_SYS_ATA_DATA_OFFSET 0 + * #define CONFIG_SYS_ATA_REG_OFFSET 0 + * #define CONFIG_SYS_ATA_ALT_OFFSET 0x0004 * * The mapping for PCI IO-space. * NOTE this is the value for the sequoia board. Modify to suit. - * #define CFG_PCI0_IO_SPACE 0xE8000000 + * #define CONFIG_SYS_PCI0_IO_SPACE 0xE8000000 */ #include @@ -58,7 +58,7 @@ #include #include -extern ulong ide_bus_offset[CFG_IDE_MAXBUS]; +extern ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS]; int ide_preinit (void) { @@ -67,7 +67,7 @@ int ide_preinit (void) int l; status = 1; - for (l = 0; l < CFG_IDE_MAXBUS; l++) { + for (l = 0; l < CONFIG_SYS_IDE_MAXBUS; l++) { ide_bus_offset[l] = -ATA_STATUS; } devbusfn = pci_find_device (0x1095, 0x0680, 0); @@ -77,11 +77,11 @@ int ide_preinit (void) pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, (u32 *) &ide_bus_offset[0]); ide_bus_offset[0] &= 0xfffffff8; - ide_bus_offset[0] += CFG_PCI0_IO_SPACE; + ide_bus_offset[0] += CONFIG_SYS_PCI0_IO_SPACE; pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2, (u32 *) &ide_bus_offset[1]); ide_bus_offset[1] &= 0xfffffff8; - ide_bus_offset[1] += CFG_PCI0_IO_SPACE; + ide_bus_offset[1] += CONFIG_SYS_PCI0_IO_SPACE; /* init various things - taken from the Linux driver */ /* set PIO mode */ pci_write_config_byte(devbusfn, 0x80, 0x00); diff --git a/drivers/block/sym53c8xx.c b/drivers/block/sym53c8xx.c index 44e998b..0c60bf8 100644 --- a/drivers/block/sym53c8xx.c +++ b/drivers/block/sym53c8xx.c @@ -426,7 +426,7 @@ void scsi_bus_reset(void) { unsigned char t; int i; - int end = CFG_SCSI_SPIN_UP_TIME*1000; + int end = CONFIG_SYS_SCSI_SPIN_UP_TIME*1000; t=scsi_read_byte(SCNTL1); scsi_write_byte(SCNTL1,(t | CRST)); @@ -836,10 +836,10 @@ void scsi_chip_init(void) scsi_write_byte(SCNTL0,0xC0); /* full arbitration no start, no message, parity disabled, master */ scsi_write_byte(SCNTL1,0x00); scsi_write_byte(SCNTL2,0x00); -#ifndef CFG_SCSI_SYM53C8XX_CCF /* config value for none 40 mhz clocks */ +#ifndef CONFIG_SYS_SCSI_SYM53C8XX_CCF /* config value for none 40 mhz clocks */ scsi_write_byte(SCNTL3,0x13); /* synchronous clock 40/4=10MHz, asynchronous 40MHz */ #else - scsi_write_byte(SCNTL3,CFG_SCSI_SYM53C8XX_CCF); /* config value for none 40 mhz clocks */ + scsi_write_byte(SCNTL3,CONFIG_SYS_SCSI_SYM53C8XX_CCF); /* config value for none 40 mhz clocks */ #endif scsi_write_byte(SCID,0x47); /* ID=7, enable reselection */ scsi_write_byte(SXFER,0x00); /* synchronous transfer period 10MHz, asynchronous */ diff --git a/drivers/block/systemace.c b/drivers/block/systemace.c index dfaab52..e8dff0a 100644 --- a/drivers/block/systemace.c +++ b/drivers/block/systemace.c @@ -20,7 +20,7 @@ /* * The Xilinx SystemACE chip support is activated by defining - * CONFIG_SYSTEMACE to turn on support, and CFG_SYSTEMACE_BASE + * CONFIG_SYSTEMACE to turn on support, and CONFIG_SYS_SYSTEMACE_BASE * to set the base address of the device. This code currently * assumes that the chip is connected via a byte-wide bus. * @@ -47,25 +47,25 @@ /* * The ace_readw and writew functions read/write 16bit words, but the * offset value is the BYTE offset as most used in the Xilinx - * datasheet for the SystemACE chip. The CFG_SYSTEMACE_BASE is defined + * datasheet for the SystemACE chip. The CONFIG_SYS_SYSTEMACE_BASE is defined * to be the base address for the chip, usually in the local * peripheral bus. */ -#if (CFG_SYSTEMACE_WIDTH == 8) +#if (CONFIG_SYS_SYSTEMACE_WIDTH == 8) #if !defined(__BIG_ENDIAN) -#define ace_readw(off) ((readb(CFG_SYSTEMACE_BASE+off)<<8) | \ - (readb(CFG_SYSTEMACE_BASE+off+1))) -#define ace_writew(val, off) {writeb(val>>8, CFG_SYSTEMACE_BASE+off); \ - writeb(val, CFG_SYSTEMACE_BASE+off+1);} +#define ace_readw(off) ((readb(CONFIG_SYS_SYSTEMACE_BASE+off)<<8) | \ + (readb(CONFIG_SYS_SYSTEMACE_BASE+off+1))) +#define ace_writew(val, off) {writeb(val>>8, CONFIG_SYS_SYSTEMACE_BASE+off); \ + writeb(val, CONFIG_SYS_SYSTEMACE_BASE+off+1);} #else -#define ace_readw(off) ((readb(CFG_SYSTEMACE_BASE+off)) | \ - (readb(CFG_SYSTEMACE_BASE+off+1)<<8)) -#define ace_writew(val, off) {writeb(val, CFG_SYSTEMACE_BASE+off); \ - writeb(val>>8, CFG_SYSTEMACE_BASE+off+1);} +#define ace_readw(off) ((readb(CONFIG_SYS_SYSTEMACE_BASE+off)) | \ + (readb(CONFIG_SYS_SYSTEMACE_BASE+off+1)<<8)) +#define ace_writew(val, off) {writeb(val, CONFIG_SYS_SYSTEMACE_BASE+off); \ + writeb(val>>8, CONFIG_SYS_SYSTEMACE_BASE+off+1);} #endif #else -#define ace_readw(off) (in16(CFG_SYSTEMACE_BASE+off)) -#define ace_writew(val, off) (out16(CFG_SYSTEMACE_BASE+off,val)) +#define ace_readw(off) (in16(CONFIG_SYS_SYSTEMACE_BASE+off)) +#define ace_writew(val, off) (out16(CONFIG_SYS_SYSTEMACE_BASE+off,val)) #endif /* */ @@ -120,7 +120,7 @@ block_dev_desc_t *systemace_get_dev(int dev) /* * Ensure the correct bus mode (8/16 bits) gets enabled */ - ace_writew(CFG_SYSTEMACE_WIDTH == 8 ? 0 : 0x0001, 0); + ace_writew(CONFIG_SYS_SYSTEMACE_WIDTH == 8 ? 0 : 0x0001, 0); init_part(&systemace_dev); diff --git a/drivers/hwmon/adm1021.c b/drivers/hwmon/adm1021.c index b791ec0..d753e9a 100644 --- a/drivers/hwmon/adm1021.c +++ b/drivers/hwmon/adm1021.c @@ -81,7 +81,7 @@ typedef } dtt_cfg_t; -dtt_cfg_t dttcfg[] = CFG_DTT_ADM1021; +dtt_cfg_t dttcfg[] = CONFIG_SYS_DTT_ADM1021; int dtt_read (int sensor, int reg) @@ -174,7 +174,7 @@ dtt_init (void) const char *const header = "DTT: "; /* switch to correct I2C bus */ - I2C_SET_BUS(CFG_DTT_BUS_NUM); + I2C_SET_BUS(CONFIG_SYS_DTT_BUS_NUM); for (i = 0; i < sizeof(sensors); i++) { if (_dtt_init(sensors[i]) != 0) diff --git a/drivers/hwmon/ds1621.c b/drivers/hwmon/ds1621.c index 523f8be..d15a082 100644 --- a/drivers/hwmon/ds1621.c +++ b/drivers/hwmon/ds1621.c @@ -125,7 +125,7 @@ static int _dtt_init(int sensor) /* * Setup High Temp. */ - val = ((CFG_DTT_MAX_TEMP * 2) << 7) & 0xff80; + val = ((CONFIG_SYS_DTT_MAX_TEMP * 2) << 7) & 0xff80; if (dtt_write(sensor, DTT_TEMP_HIGH, val) != 0) return 1; udelay(50000); /* Max 50ms */ @@ -133,7 +133,7 @@ static int _dtt_init(int sensor) /* * Setup Low Temp - hysteresis. */ - val = (((CFG_DTT_MAX_TEMP - CFG_DTT_HYSTERESIS) * 2) << 7) & 0xff80; + val = (((CONFIG_SYS_DTT_MAX_TEMP - CONFIG_SYS_DTT_HYSTERESIS) * 2) << 7) & 0xff80; if (dtt_write(sensor, DTT_TEMP_LOW, val) != 0) return 1; udelay(50000); /* Max 50ms */ diff --git a/drivers/hwmon/ds1775.c b/drivers/hwmon/ds1775.c index 6a4d8e5..80fb26f 100644 --- a/drivers/hwmon/ds1775.c +++ b/drivers/hwmon/ds1775.c @@ -24,7 +24,7 @@ #include #include -#define DTT_I2C_DEV_CODE CFG_I2C_DTT_ADDR /* Dallas Semi's DS1775 device code */ +#define DTT_I2C_DEV_CODE CONFIG_SYS_I2C_DTT_ADDR /* Dallas Semi's DS1775 device code */ #define DTT_READ_TEMP 0x0 #define DTT_CONFIG 0x1 #define DTT_TEMP_HYST 0x2 @@ -105,7 +105,7 @@ static int _dtt_init(int sensor) /* * Setup High Temp */ - val = ((CFG_DTT_MAX_TEMP * 2) << 7) & 0xff80; + val = ((CONFIG_SYS_DTT_MAX_TEMP * 2) << 7) & 0xff80; if (dtt_write(sensor, DTT_TEMP_OS, val) != 0) return 1; udelay(50000); /* Max 50ms */ @@ -113,7 +113,7 @@ static int _dtt_init(int sensor) /* * Setup Low Temp - hysteresis */ - val = (((CFG_DTT_MAX_TEMP - CFG_DTT_HYSTERESIS) * 2) << 7) & 0xff80; + val = (((CONFIG_SYS_DTT_MAX_TEMP - CONFIG_SYS_DTT_HYSTERESIS) * 2) << 7) & 0xff80; if (dtt_write(sensor, DTT_TEMP_HYST, val) != 0) return 1; udelay(50000); /* Max 50ms */ diff --git a/drivers/hwmon/lm73.c b/drivers/hwmon/lm73.c index dd24683..7b5d893 100644 --- a/drivers/hwmon/lm73.c +++ b/drivers/hwmon/lm73.c @@ -124,11 +124,11 @@ static int _dtt_init(int const sensor) /* * Setup THIGH (upper-limit) and TLOW (lower-limit) registers */ - val = CFG_DTT_MAX_TEMP << 7; + val = CONFIG_SYS_DTT_MAX_TEMP << 7; if (dtt_write(sensor, DTT_TEMP_HIGH, val)) return -1; - val = CFG_DTT_MIN_TEMP << 7; + val = CONFIG_SYS_DTT_MIN_TEMP << 7; if (dtt_write(sensor, DTT_TEMP_LOW, val)) return -1; /* diff --git a/drivers/hwmon/lm75.c b/drivers/hwmon/lm75.c index 17379e5..8119821 100644 --- a/drivers/hwmon/lm75.c +++ b/drivers/hwmon/lm75.c @@ -32,8 +32,8 @@ /* * Device code */ -#if defined(CFG_I2C_DTT_ADDR) -#define DTT_I2C_DEV_CODE CFG_I2C_DTT_ADDR +#if defined(CONFIG_SYS_I2C_DTT_ADDR) +#define DTT_I2C_DEV_CODE CONFIG_SYS_I2C_DTT_ADDR #else #define DTT_I2C_DEV_CODE 0x48 /* ON Semi's LM75 device */ #endif @@ -124,12 +124,12 @@ static int _dtt_init(int sensor) int val; /* Setup TSET ( trip point ) register */ - val = ((CFG_DTT_MAX_TEMP * 2) << 7) & 0xff80; /* trip */ + val = ((CONFIG_SYS_DTT_MAX_TEMP * 2) << 7) & 0xff80; /* trip */ if (dtt_write(sensor, DTT_TEMP_SET, val) != 0) return 1; /* Setup THYST ( untrip point ) register - Hysteresis */ - val = (((CFG_DTT_MAX_TEMP - CFG_DTT_HYSTERESIS) * 2) << 7) & 0xff80; + val = (((CONFIG_SYS_DTT_MAX_TEMP - CONFIG_SYS_DTT_HYSTERESIS) * 2) << 7) & 0xff80; if (dtt_write(sensor, DTT_TEMP_HYST, val) != 0) return 1; @@ -157,7 +157,7 @@ int dtt_init (void) /* switch to correct I2C bus */ old_bus = I2C_GET_BUS(); - I2C_SET_BUS(CFG_DTT_BUS_NUM); + I2C_SET_BUS(CONFIG_SYS_DTT_BUS_NUM); for (i = 0; i < sizeof(sensors); i++) { if (_dtt_init(sensors[i]) != 0) diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index 264553d..281a88b 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -26,7 +26,7 @@ #include #include /* HW definitions */ -#define I2C_TIMEOUT (CFG_HZ / 4) +#define I2C_TIMEOUT (CONFIG_SYS_HZ / 4) #define I2C_READ_BIT 1 #define I2C_WRITE_BIT 0 @@ -38,18 +38,18 @@ DECLARE_GLOBAL_DATA_PTR; * runs from ROM, and we can't switch buses because we can't modify * the global variables. */ -#ifdef CFG_SPD_BUS_NUM -static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = CFG_SPD_BUS_NUM; +#ifdef CONFIG_SYS_SPD_BUS_NUM +static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = CONFIG_SYS_SPD_BUS_NUM; #else static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0; #endif -static unsigned int i2c_bus_speed[2] = {CFG_I2C_SPEED, CFG_I2C_SPEED}; +static unsigned int i2c_bus_speed[2] = {CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SPEED}; static const struct fsl_i2c *i2c_dev[2] = { - (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET), -#ifdef CFG_I2C2_OFFSET - (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET) + (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET), +#ifdef CONFIG_SYS_I2C2_OFFSET + (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C2_OFFSET) #endif }; @@ -176,7 +176,7 @@ i2c_init(int speed, int slaveadd) struct fsl_i2c *dev; unsigned int temp; - dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET); + dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET); writeb(0, &dev->cr); /* stop I2C controller */ udelay(5); /* let it shutdown in peace */ @@ -187,8 +187,8 @@ i2c_init(int speed, int slaveadd) writeb(0x0, &dev->sr); /* clear status register */ writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ -#ifdef CFG_I2C2_OFFSET - dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET); +#ifdef CONFIG_SYS_I2C2_OFFSET + dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C2_OFFSET); writeb(0, &dev->cr); /* stop I2C controller */ udelay(5); /* let it shutdown in peace */ @@ -386,7 +386,7 @@ i2c_reg_write(uchar i2c_addr, uchar reg, uchar val) int i2c_set_bus_num(unsigned int bus) { -#ifdef CFG_I2C2_OFFSET +#ifdef CONFIG_SYS_I2C2_OFFSET if (bus > 1) { #else if (bus > 0) { diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index 1f6ba1f..eedad06 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -47,14 +47,14 @@ #define I2SR_IIF (1 << 1) #define I2SR_RX_NO_AK (1 << 0) -#ifdef CFG_I2C_MX31_PORT1 +#ifdef CONFIG_SYS_I2C_MX31_PORT1 #define I2C_BASE 0x43f80000 -#elif defined (CFG_I2C_MX31_PORT2) +#elif defined (CONFIG_SYS_I2C_MX31_PORT2) #define I2C_BASE 0x43f98000 -#elif defined (CFG_I2C_MX31_PORT3) +#elif defined (CONFIG_SYS_I2C_MX31_PORT3) #define I2C_BASE 0x43f84000 #else -#error "define CFG_I2C_MX31_PORTx to use the mx31 I2C driver" +#error "define CONFIG_SYS_I2C_MX31_PORTx to use the mx31 I2C driver" #endif #ifdef DEBUG diff --git a/drivers/i2c/omap1510_i2c.c b/drivers/i2c/omap1510_i2c.c index 388951d..a4e6227 100644 --- a/drivers/i2c/omap1510_i2c.c +++ b/drivers/i2c/omap1510_i2c.c @@ -205,7 +205,7 @@ int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len) for (i = 0; i < len; i++) { if (i2c_read_byte (chip, addr + i, &buffer[i])) { printf ("I2C read: I/O error\n"); - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); return 1; } } @@ -230,7 +230,7 @@ int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len) for (i = 0; i < len; i++) { if (i2c_write_byte (chip, addr + i, buffer[i])) { printf ("I2C read: I/O error\n"); - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); return 1; } } diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index d16cfb1..134dccb 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -252,7 +252,7 @@ int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len) for (i = 0; i < len; i++) { if (i2c_read_byte (chip, addr + i, &buffer[i])) { printf ("I2C read: I/O error\n"); - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); return 1; } } @@ -277,7 +277,7 @@ int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len) for (i = 0; i < len; i++) { if (i2c_write_byte (chip, addr + i, buffer[i])) { printf ("I2C read: I/O error\n"); - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); return 1; } } diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index 0a9feb6..508d3d7 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -75,7 +75,7 @@ static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0; /*----------------------------------------------------------------------- * Local functions */ -#if !defined(CFG_I2C_INIT_BOARD) +#if !defined(CONFIG_SYS_I2C_INIT_BOARD) static void send_reset (void); #endif static void send_start (void); @@ -84,7 +84,7 @@ static void send_ack (int); static int write_byte (uchar byte); static uchar read_byte (int); -#if !defined(CFG_I2C_INIT_BOARD) +#if !defined(CONFIG_SYS_I2C_INIT_BOARD) /*----------------------------------------------------------------------- * Send a reset sequence consisting of 9 clocks with the data signal high * to clock any confused device back into an idle state. Also send a @@ -224,7 +224,7 @@ unsigned int i2c_get_bus_num(void) int i2c_set_bus_num(unsigned int bus) { #if defined(CONFIG_I2C_MUX) - if (bus < CFG_MAX_I2C_BUS) { + if (bus < CONFIG_SYS_MAX_I2C_BUS) { i2c_bus_num = bus; } else { int ret; @@ -236,7 +236,7 @@ int i2c_set_bus_num(unsigned int bus) return ret; } #else - if (bus >= CFG_MAX_I2C_BUS) + if (bus >= CONFIG_SYS_MAX_I2C_BUS) return -1; i2c_bus_num = bus; #endif @@ -246,12 +246,12 @@ int i2c_set_bus_num(unsigned int bus) /* TODO: add 100/400k switching */ unsigned int i2c_get_bus_speed(void) { - return CFG_I2C_SPEED; + return CONFIG_SYS_I2C_SPEED; } int i2c_set_bus_speed(unsigned int speed) { - if (speed != CFG_I2C_SPEED) + if (speed != CONFIG_SYS_I2C_SPEED) return -1; return 0; @@ -297,7 +297,7 @@ static uchar read_byte(int ack) */ void i2c_init (int speed, int slaveaddr) { -#if defined(CFG_I2C_INIT_BOARD) +#if defined(CONFIG_SYS_I2C_INIT_BOARD) /* call board specific i2c bus reset routine before accessing the */ /* environment, which might be in a chip on that bus. For details */ /* about this problem see doc/I2C_Edge_Conditions. */ @@ -342,7 +342,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) PRINTD("i2c_read: chip %02X addr %02X alen %d buffer %p len %d\n", chip, addr, alen, buffer, len); -#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW /* * EEPROM chips that implement "address overflow" are ones * like Catalyst 24WC04/08/16 which has 9/10/11 bits of @@ -354,7 +354,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) * still be one byte because the extra address bits are * hidden in the chip address. */ - chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); + chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); PRINTD("i2c_read: fix addr_overflow: chip %02X addr %02X\n", chip, addr); diff --git a/drivers/i2c/tsi108_i2c.c b/drivers/i2c/tsi108_i2c.c index 695e393..fda822c 100644 --- a/drivers/i2c/tsi108_i2c.c +++ b/drivers/i2c/tsi108_i2c.c @@ -60,14 +60,14 @@ static int i2c_read_byte ( chan_offset = TSI108_I2C_SDRAM_OFFSET; /* Check if I2C operation is in progress */ - temp = *(u32 *) (CFG_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2); + temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2); if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START))) { /* Set device address and operation (read = 0) */ temp = (byte_addr << 16) | ((chip_addr & 0x07) << 8) | ((chip_addr >> 3) & 0x0F); - *(u32 *) (CFG_TSI108_CSR_BASE + chan_offset + I2C_CNTRL1) = + *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL1) = temp; /* Issue the read command @@ -75,13 +75,13 @@ static int i2c_read_byte ( * (size = 1 byte, lane = 0) */ - *(u32 *) (CFG_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2) = + *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2) = (I2C_CNTRL2_START); /* Wait until operation completed */ do { /* Read I2C operation status */ - temp = *(u32 *) (CFG_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2); + temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2); if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_START))) { if (0 == (temp & @@ -90,7 +90,7 @@ static int i2c_read_byte ( ) { op_status = TSI108_I2C_SUCCESS; - temp = *(u32 *) (CFG_TSI108_CSR_BASE + + temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_RD_DATA); @@ -172,25 +172,25 @@ static int i2c_write_byte (uchar chip_addr,/* I2C device address on the bus */ u32 op_status = TSI108_I2C_TIMEOUT_ERR; /* Check if I2C operation is in progress */ - temp = *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2); + temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2); if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START))) { /* Place data into the I2C Tx Register */ - *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET + + *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_TX_DATA) = (u32) * buffer; /* Set device address and operation */ temp = I2C_CNTRL1_I2CWRITE | (byte_addr << 16) | ((chip_addr & 0x07) << 8) | ((chip_addr >> 3) & 0x0F); - *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET + + *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL1) = temp; /* Issue the write command (at this moment all other parameters * are 0 (size = 1 byte, lane = 0) */ - *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET + + *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2) = (I2C_CNTRL2_START); op_status = TSI108_I2C_TIMEOUT_ERR; @@ -198,7 +198,7 @@ static int i2c_write_byte (uchar chip_addr,/* I2C device address on the bus */ /* Wait until operation completed */ do { /* Read I2C operation status */ - temp = *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2); + temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2); if (0 == (temp & (I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START))) { if (0 == (temp & diff --git a/drivers/input/i8042.c b/drivers/input/i8042.c index d152768..58094c9 100644 --- a/drivers/input/i8042.c +++ b/drivers/input/i8042.c @@ -41,7 +41,7 @@ extern void gt_cpcidvi_out8(u32 offset, u8 data); #ifdef CONFIG_CONSOLE_CURSOR extern void console_cursor (int state); -static int blinkCount = CFG_CONSOLE_BLINK_COUNT; +static int blinkCount = CONFIG_SYS_CONSOLE_BLINK_COUNT; static int cursor_state = 0; #endif @@ -368,7 +368,7 @@ int i8042_tstc (void) { cursor_state ^= 1; console_cursor (cursor_state); - blinkCount = CFG_CONSOLE_BLINK_COUNT; + blinkCount = CONFIG_SYS_CONSOLE_BLINK_COUNT; udelay (10); } #endif @@ -409,7 +409,7 @@ int i8042_getc (void) { cursor_state ^= 1; console_cursor (cursor_state); - blinkCount = CFG_CONSOLE_BLINK_COUNT; + blinkCount = CONFIG_SYS_CONSOLE_BLINK_COUNT; } udelay (10); #endif diff --git a/drivers/input/keyboard.c b/drivers/input/keyboard.c index a634d76..512b9f2 100644 --- a/drivers/input/keyboard.c +++ b/drivers/input/keyboard.c @@ -258,12 +258,12 @@ void handle_scancode(unsigned char scancode) * Init ******************************************************************/ -#ifdef CFG_CONSOLE_OVERWRITE_ROUTINE +#ifdef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE extern int overwrite_console (void); #define OVERWRITE_CONSOLE overwrite_console () #else #define OVERWRITE_CONSOLE 0 -#endif /* CFG_CONSOLE_OVERWRITE_ROUTINE */ +#endif /* CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE */ int kbd_init (void) { diff --git a/drivers/input/ps2ser.c b/drivers/input/ps2ser.c index 480ffa2..1af3fde 100644 --- a/drivers/input/ps2ser.c +++ b/drivers/input/ps2ser.c @@ -18,7 +18,7 @@ #include #include #include -#if defined(CFG_NS16550) || defined(CONFIG_MPC85xx) +#if defined(CONFIG_SYS_NS16550) || defined(CONFIG_MPC85xx) #include #endif @@ -51,9 +51,9 @@ DECLARE_GLOBAL_DATA_PTR; defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555) #if CONFIG_PS2SERIAL == 1 -#define COM_BASE (CFG_CCSRBAR+0x4500) +#define COM_BASE (CONFIG_SYS_CCSRBAR+0x4500) #elif CONFIG_PS2SERIAL == 2 -#define COM_BASE (CFG_CCSRBAR+0x4600) +#define COM_BASE (CONFIG_SYS_CCSRBAR+0x4600) #else #error CONFIG_PS2SERIAL must be in 1 ... 2 #endif @@ -88,7 +88,7 @@ int ps2ser_init(void) /* select clock sources */ #if defined(CONFIG_MGT5100) psc->psc_clock_select = 0xdd00; - baseclk = (CFG_MPC5XXX_CLKIN + 16) / 32; + baseclk = (CONFIG_SYS_MPC5XXX_CLKIN + 16) / 32; #elif defined(CONFIG_MPC5200) psc->psc_clock_select = 0; baseclk = (gd->ipb_clk + 16) / 32; @@ -129,8 +129,8 @@ int ps2ser_init(void) com_port->ier = 0x00; com_port->lcr = LCR_BKSE | LCR_8N1; - com_port->dll = (CFG_NS16550_CLK / 16 / PS2SER_BAUD) & 0xff; - com_port->dlm = ((CFG_NS16550_CLK / 16 / PS2SER_BAUD) >> 8) & 0xff; + com_port->dll = (CONFIG_SYS_NS16550_CLK / 16 / PS2SER_BAUD) & 0xff; + com_port->dlm = ((CONFIG_SYS_NS16550_CLK / 16 / PS2SER_BAUD) >> 8) & 0xff; com_port->lcr = LCR_8N1; com_port->mcr = (MCR_DTR | MCR_RTS); com_port->fcr = (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR); diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c index 2e94614..64df1c9 100644 --- a/drivers/misc/fsl_law.c +++ b/drivers/misc/fsl_law.c @@ -46,7 +46,7 @@ DECLARE_GLOBAL_DATA_PTR; void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id) { - volatile u32 *base = (volatile u32 *)(CFG_IMMR + 0xc08); + volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08); volatile u32 *lawbar = base + 8 * idx; volatile u32 *lawar = base + 8 * idx + 2; @@ -91,7 +91,7 @@ int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id) void disable_law(u8 idx) { - volatile u32 *base = (volatile u32 *)(CFG_IMMR + 0xc08); + volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08); volatile u32 *lawbar = base + 8 * idx; volatile u32 *lawar = base + 8 * idx + 2; @@ -105,7 +105,7 @@ void disable_law(u8 idx) void print_laws(void) { - volatile u32 *base = (volatile u32 *)(CFG_IMMR + 0xc08); + volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08); volatile u32 *lawbar = base; volatile u32 *lawar = base + 2; int i; diff --git a/drivers/misc/ns87308.c b/drivers/misc/ns87308.c index 6642c2e..9130a1f 100644 --- a/drivers/misc/ns87308.c +++ b/drivers/misc/ns87308.c @@ -27,7 +27,7 @@ void initialise_ns87308 (void) { -#ifdef CFG_NS87308_PS2MOD +#ifdef CONFIG_SYS_NS87308_PS2MOD unsigned char data; /* @@ -38,80 +38,80 @@ void initialise_ns87308 (void) write_pnp_config(SUPOERIO_CONF1, data); #endif -#if (CFG_NS87308_DEVS & CFG_NS87308_KBC1) - PNP_SET_DEVICE_BASE(LDEV_KBC1, CFG_NS87308_KBC1_BASE); +#if (CONFIG_SYS_NS87308_DEVS & CONFIG_SYS_NS87308_KBC1) + PNP_SET_DEVICE_BASE(LDEV_KBC1, CONFIG_SYS_NS87308_KBC1_BASE); write_pnp_config(LUN_CONFIG_REG, 0); write_pnp_config(CBASE_HIGH, 0x00); write_pnp_config(CBASE_LOW, 0x64); #endif -#if (CFG_NS87308_DEVS & CFG_NS87308_MOUSE) +#if (CONFIG_SYS_NS87308_DEVS & CONFIG_SYS_NS87308_MOUSE) PNP_ACTIVATE_DEVICE(LDEV_MOUSE); #endif -#if (CFG_NS87308_DEVS & CFG_NS87308_RTC_APC) - PNP_SET_DEVICE_BASE(LDEV_RTC_APC, CFG_NS87308_RTC_BASE); +#if (CONFIG_SYS_NS87308_DEVS & CONFIG_SYS_NS87308_RTC_APC) + PNP_SET_DEVICE_BASE(LDEV_RTC_APC, CONFIG_SYS_NS87308_RTC_BASE); #endif -#if (CFG_NS87308_DEVS & CFG_NS87308_FDC) - PNP_SET_DEVICE_BASE(LDEV_FDC, CFG_NS87308_FDC_BASE); +#if (CONFIG_SYS_NS87308_DEVS & CONFIG_SYS_NS87308_FDC) + PNP_SET_DEVICE_BASE(LDEV_FDC, CONFIG_SYS_NS87308_FDC_BASE); write_pnp_config(LUN_CONFIG_REG, 0x40); #endif -#if (CFG_NS87308_DEVS & CFG_NS87308_RARP) - PNP_SET_DEVICE_BASE(LDEV_PARP, CFG_NS87308_LPT_BASE); +#if (CONFIG_SYS_NS87308_DEVS & CONFIG_SYS_NS87308_RARP) + PNP_SET_DEVICE_BASE(LDEV_PARP, CONFIG_SYS_NS87308_LPT_BASE); #endif -#if (CFG_NS87308_DEVS & CFG_NS87308_UART1) - PNP_SET_DEVICE_BASE(LDEV_UART1, CFG_NS87308_UART1_BASE); +#if (CONFIG_SYS_NS87308_DEVS & CONFIG_SYS_NS87308_UART1) + PNP_SET_DEVICE_BASE(LDEV_UART1, CONFIG_SYS_NS87308_UART1_BASE); #endif -#if (CFG_NS87308_DEVS & CFG_NS87308_UART2) - PNP_SET_DEVICE_BASE(LDEV_UART2, CFG_NS87308_UART2_BASE); +#if (CONFIG_SYS_NS87308_DEVS & CONFIG_SYS_NS87308_UART2) + PNP_SET_DEVICE_BASE(LDEV_UART2, CONFIG_SYS_NS87308_UART2_BASE); #endif -#if (CFG_NS87308_DEVS & CFG_NS87308_GPIO) - PNP_SET_DEVICE_BASE(LDEV_GPIO, CFG_NS87308_GPIO_BASE); +#if (CONFIG_SYS_NS87308_DEVS & CONFIG_SYS_NS87308_GPIO) + PNP_SET_DEVICE_BASE(LDEV_GPIO, CONFIG_SYS_NS87308_GPIO_BASE); #endif -#if (CFG_NS87308_DEVS & CFG_NS87308_POWRMAN) -#ifndef CFG_NS87308_PWMAN_BASE +#if (CONFIG_SYS_NS87308_DEVS & CONFIG_SYS_NS87308_POWRMAN) +#ifndef CONFIG_SYS_NS87308_PWMAN_BASE PNP_ACTIVATE_DEVICE(LDEV_POWRMAN); #else - PNP_SET_DEVICE_BASE(LDEV_POWRMAN, CFG_NS87308_PWMAN_BASE); + PNP_SET_DEVICE_BASE(LDEV_POWRMAN, CONFIG_SYS_NS87308_PWMAN_BASE); /* * Enable all units */ - write_pm_reg(CFG_NS87308_PWMAN_BASE, PWM_FER1, 0x7d); - write_pm_reg(CFG_NS87308_PWMAN_BASE, PWM_FER2, 0x87); + write_pm_reg(CONFIG_SYS_NS87308_PWMAN_BASE, PWM_FER1, 0x7d); + write_pm_reg(CONFIG_SYS_NS87308_PWMAN_BASE, PWM_FER2, 0x87); -#ifdef CFG_NS87308_PMC1 - write_pm_reg(CFG_NS87308_PWMAN_BASE, PWM_PMC1, CFG_NS87308_PMC1); +#ifdef CONFIG_SYS_NS87308_PMC1 + write_pm_reg(CONFIG_SYS_NS87308_PWMAN_BASE, PWM_PMC1, CONFIG_SYS_NS87308_PMC1); #endif -#ifdef CFG_NS87308_PMC2 - write_pm_reg(CFG_NS87308_PWMAN_BASE, PWM_PMC2, CFG_NS87308_PMC2); +#ifdef CONFIG_SYS_NS87308_PMC2 + write_pm_reg(CONFIG_SYS_NS87308_PWMAN_BASE, PWM_PMC2, CONFIG_SYS_NS87308_PMC2); #endif -#ifdef CFG_NS87308_PMC3 - write_pm_reg(CFG_NS87308_PWMAN_BASE, PWM_PMC3, CFG_NS87308_PMC3); +#ifdef CONFIG_SYS_NS87308_PMC3 + write_pm_reg(CONFIG_SYS_NS87308_PWMAN_BASE, PWM_PMC3, CONFIG_SYS_NS87308_PMC3); #endif #endif #endif -#ifdef CFG_NS87308_CS0_BASE - PNP_PGCS_CSLINE_BASE(0, CFG_NS87308_CS0_BASE); - PNP_PGCS_CSLINE_CONF(0, CFG_NS87308_CS0_CONF); +#ifdef CONFIG_SYS_NS87308_CS0_BASE + PNP_PGCS_CSLINE_BASE(0, CONFIG_SYS_NS87308_CS0_BASE); + PNP_PGCS_CSLINE_CONF(0, CONFIG_SYS_NS87308_CS0_CONF); #endif -#ifdef CFG_NS87308_CS1_BASE - PNP_PGCS_CSLINE_BASE(1, CFG_NS87308_CS1_BASE); - PNP_PGCS_CSLINE_CONF(1, CFG_NS87308_CS1_CONF); +#ifdef CONFIG_SYS_NS87308_CS1_BASE + PNP_PGCS_CSLINE_BASE(1, CONFIG_SYS_NS87308_CS1_BASE); + PNP_PGCS_CSLINE_CONF(1, CONFIG_SYS_NS87308_CS1_CONF); #endif -#ifdef CFG_NS87308_CS2_BASE - PNP_PGCS_CSLINE_BASE(2, CFG_NS87308_CS2_BASE); - PNP_PGCS_CSLINE_CONF(2, CFG_NS87308_CS2_CONF); +#ifdef CONFIG_SYS_NS87308_CS2_BASE + PNP_PGCS_CSLINE_BASE(2, CONFIG_SYS_NS87308_CS2_BASE); + PNP_PGCS_CSLINE_CONF(2, CONFIG_SYS_NS87308_CS2_CONF); #endif } diff --git a/drivers/mmc/atmel_mci.c b/drivers/mmc/atmel_mci.c index a151488..3aa92f2 100644 --- a/drivers/mmc/atmel_mci.c +++ b/drivers/mmc/atmel_mci.c @@ -38,16 +38,16 @@ #define pr_debug(...) do { } while(0) #endif -#ifndef CFG_MMC_CLK_OD -#define CFG_MMC_CLK_OD 150000 +#ifndef CONFIG_SYS_MMC_CLK_OD +#define CONFIG_SYS_MMC_CLK_OD 150000 #endif -#ifndef CFG_MMC_CLK_PP -#define CFG_MMC_CLK_PP 5000000 +#ifndef CONFIG_SYS_MMC_CLK_PP +#define CONFIG_SYS_MMC_CLK_PP 5000000 #endif -#ifndef CFG_MMC_OP_COND -#define CFG_MMC_OP_COND 0x00100000 +#ifndef CONFIG_SYS_MMC_OP_COND +#define CONFIG_SYS_MMC_OP_COND 0x00100000 #endif #define MMC_DEFAULT_BLKLEN 512 @@ -349,7 +349,7 @@ static int sd_init_card(struct mmc_cid *cid, int verbose) mmc_idle_cards(); for (i = 0; i < 1000; i++) { - ret = mmc_acmd(SD_CMD_APP_SEND_OP_COND, CFG_MMC_OP_COND, + ret = mmc_acmd(SD_CMD_APP_SEND_OP_COND, CONFIG_SYS_MMC_OP_COND, resp, R3 | NID); if (ret || (resp[0] & 0x80000000)) break; @@ -385,7 +385,7 @@ static int mmc_init_card(struct mmc_cid *cid, int verbose) mmc_idle_cards(); for (i = 0; i < 1000; i++) { - ret = mmc_cmd(MMC_CMD_SEND_OP_COND, CFG_MMC_OP_COND, resp, + ret = mmc_cmd(MMC_CMD_SEND_OP_COND, CONFIG_SYS_MMC_OP_COND, resp, R3 | NID | OPEN_DRAIN); if (ret || (resp[0] & 0x80000000)) break; @@ -434,7 +434,7 @@ static void mci_set_data_timeout(struct mmc_csd *csd) timeout_clks = csd->nsac * 100; timeout_clks += (((timeout_ns + 9) / 10) - * ((CFG_MMC_CLK_PP + 99999) / 100000) + 9999) / 10000; + * ((CONFIG_SYS_MMC_CLK_PP + 99999) / 100000) + 9999) / 10000; if (!mmc_card_is_sd) timeout_clks *= 10; else @@ -475,7 +475,7 @@ int mmc_init(int verbose) mmci_writel(CR, MMCI_BIT(MCIEN)); mmci_writel(DTOR, 0x5f); mmci_writel(IDR, ~0UL); - mci_set_mode(CFG_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); + mci_set_mode(CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); mmc_card_is_sd = 0; @@ -520,7 +520,7 @@ int mmc_init(int verbose) mmc_blkdev.blksz = 512; mmc_blkdev.lba = (csd.c_size + 1) * (1 << (csd.c_size_mult + 2)); - mci_set_mode(CFG_MMC_CLK_PP, mmc_blkdev.blksz); + mci_set_mode(CONFIG_SYS_MMC_CLK_PP, mmc_blkdev.blksz); #if 0 if (fat_register_device(&mmc_blkdev, 1)) diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 7bfdc43..c40bf66 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -57,12 +57,12 @@ * AMD/Spansion Application Note: Migration from Single-byte to Three-byte * Device IDs, Publication Number 25538 Revision A, November 8, 2001 * - * Define CFG_WRITE_SWAPPED_DATA, if you have to swap the Bytes between + * Define CONFIG_SYS_WRITE_SWAPPED_DATA, if you have to swap the Bytes between * reading and writing ... (yes there is such a Hardware). */ -#ifndef CFG_FLASH_BANKS_LIST -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#ifndef CONFIG_SYS_FLASH_BANKS_LIST +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } #endif #define FLASH_CMD_CFI 0x98 @@ -143,7 +143,7 @@ #define CFI_CMDSET_SST 258 #define CFI_CMDSET_INTEL_PROG_REGIONS 512 -#ifdef CFG_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */ +#ifdef CONFIG_SYS_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */ # undef FLASH_CMD_RESET # define FLASH_CMD_RESET AMD_CMD_RESET /* use AMD-Reset instead */ #endif @@ -159,11 +159,11 @@ typedef union { static uint flash_offset_cfi[2] = { FLASH_OFFSET_CFI, FLASH_OFFSET_CFI_ALT }; -/* use CFG_MAX_FLASH_BANKS_DETECT if defined */ -#ifdef CFG_MAX_FLASH_BANKS_DETECT -# define CFI_MAX_FLASH_BANKS CFG_MAX_FLASH_BANKS_DETECT +/* use CONFIG_SYS_MAX_FLASH_BANKS_DETECT if defined */ +#ifdef CONFIG_SYS_MAX_FLASH_BANKS_DETECT +# define CFI_MAX_FLASH_BANKS CONFIG_SYS_MAX_FLASH_BANKS_DETECT #else -# define CFI_MAX_FLASH_BANKS CFG_MAX_FLASH_BANKS +# define CFI_MAX_FLASH_BANKS CONFIG_SYS_MAX_FLASH_BANKS #endif flash_info_t flash_info[CFI_MAX_FLASH_BANKS]; /* FLASH chips info */ @@ -171,8 +171,8 @@ flash_info_t flash_info[CFI_MAX_FLASH_BANKS]; /* FLASH chips info */ /* * Check if chip width is defined. If not, start detecting with 8bit. */ -#ifndef CFG_FLASH_CFI_WIDTH -#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT +#ifndef CONFIG_SYS_FLASH_CFI_WIDTH +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT #endif typedef unsigned long flash_sect_t; @@ -255,20 +255,20 @@ u64 flash_read64(void *addr)__attribute__((weak, alias("__flash_read64"))); /*----------------------------------------------------------------------- */ -#if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE) +#if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) static flash_info_t *flash_get_info(ulong base) { int i; flash_info_t * info = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { info = & flash_info[i]; if (info->size && info->start[0] <= base && base <= info->start[0] + info->size - 1) break; } - return i == CFG_MAX_FLASH_BANKS ? 0 : info; + return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info; } #endif @@ -309,7 +309,7 @@ static void flash_make_cmd(flash_info_t *info, u32 cmd, void *cmdbuf) int i; int cword_offset; int cp_offset; -#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA) +#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) u32 cmd_le = cpu_to_le32(cmd); #endif uchar val; @@ -317,7 +317,7 @@ static void flash_make_cmd(flash_info_t *info, u32 cmd, void *cmdbuf) for (i = info->portwidth; i > 0; i--){ cword_offset = (info->portwidth-i)%info->chipwidth; -#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA) +#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) cp_offset = info->portwidth - i; val = *((uchar*)&cmd_le + cword_offset); #else @@ -374,7 +374,7 @@ static inline uchar flash_read_uchar (flash_info_t * info, uint offset) uchar retval; cp = flash_map (info, 0, offset); -#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA) +#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) retval = flash_read8(cp); #else retval = flash_read8(cp + info->portwidth - 1); @@ -419,7 +419,7 @@ static ulong flash_read_long (flash_info_t * info, flash_sect_t sect, debug ("addr[%x] = 0x%x\n", x, flash_read8(addr + x)); } #endif -#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA) +#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) retval = ((flash_read8(addr) << 16) | (flash_read8(addr + info->portwidth) << 24) | (flash_read8(addr + 2 * info->portwidth)) | @@ -646,8 +646,8 @@ static int flash_status_check (flash_info_t * info, flash_sect_t sector, { ulong start; -#if CFG_HZ != 1000 - tout *= CFG_HZ/1000; +#if CONFIG_SYS_HZ != 1000 + tout *= CONFIG_SYS_HZ/1000; #endif /* Wait for command completion */ @@ -716,7 +716,7 @@ static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, */ static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c) { -#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA) +#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) unsigned short w; unsigned int l; unsigned long long ll; @@ -727,7 +727,7 @@ static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c) cword->c = c; break; case FLASH_CFI_16BIT: -#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA) +#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) w = c; w <<= 8; cword->w = (cword->w >> 8) | w; @@ -736,7 +736,7 @@ static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c) #endif break; case FLASH_CFI_32BIT: -#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA) +#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) l = c; l <<= 24; cword->l = (cword->l >> 8) | l; @@ -745,7 +745,7 @@ static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c) #endif break; case FLASH_CFI_64BIT: -#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA) +#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) ll = c; ll <<= 56; cword->ll = (cword->ll >> 8) | ll; @@ -850,7 +850,7 @@ static int flash_write_cfiword (flash_info_t * info, ulong dest, info->write_tout, "write"); } -#ifdef CFG_FLASH_USE_BUFFER_WRITE +#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, int len) @@ -1024,7 +1024,7 @@ out_unmap: unmap_physmem(dst, len); return retcode; } -#endif /* CFG_FLASH_USE_BUFFER_WRITE */ +#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ /*----------------------------------------------------------------------- @@ -1173,7 +1173,7 @@ void flash_print_info (flash_info_t * info) for (i = 0; i < info->sector_count; ++i) { if ((i % 5) == 0) printf ("\n"); -#ifdef CFG_FLASH_EMPTY_INFO +#ifdef CONFIG_SYS_FLASH_EMPTY_INFO int k; int size; int erased; @@ -1198,7 +1198,7 @@ void flash_print_info (flash_info_t * info) info->start[i], erased ? 'E' : ' ', info->protect[i] ? "RO" : " "); -#else /* ! CFG_FLASH_EMPTY_INFO */ +#else /* ! CONFIG_SYS_FLASH_EMPTY_INFO */ printf (" %08lX %s ", info->start[i], info->protect[i] ? "RO" : " "); @@ -1242,7 +1242,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) int aln; cfiword_t cword; int i, rc; -#ifdef CFG_FLASH_USE_BUFFER_WRITE +#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE int buffered_size; #endif #ifdef CONFIG_FLASH_SHOW_PROGRESS @@ -1286,7 +1286,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) } /* handle the aligned part */ -#ifdef CFG_FLASH_USE_BUFFER_WRITE +#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE buffered_size = (info->portwidth / info->chipwidth); buffered_size *= info->buffer_size; while (cnt >= info->portwidth) { @@ -1326,7 +1326,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) cnt -= info->portwidth; FLASH_SHOW_PROGRESS(scale, dots, digit, info->portwidth); } -#endif /* CFG_FLASH_USE_BUFFER_WRITE */ +#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ if (cnt == 0) { return (0); @@ -1350,7 +1350,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) /*----------------------------------------------------------------------- */ -#ifdef CFG_FLASH_PROTECTION +#ifdef CONFIG_SYS_FLASH_PROTECTION int flash_real_protect (flash_info_t * info, long sector, int prot) { @@ -1457,7 +1457,7 @@ void flash_read_factory_serial (flash_info_t * info, void *buffer, int offset, flash_unmap(info, 0, FLASH_OFFSET_INTEL_PROTECTION, src); } -#endif /* CFG_FLASH_PROTECTION */ +#endif /* CONFIG_SYS_FLASH_PROTECTION */ /*----------------------------------------------------------------------- * Reverse the order of the erase regions in the CFI QRY structure. @@ -1501,7 +1501,7 @@ static int cmdset_intel_init(flash_info_t *info, struct cfi_qry *qry) cmdset_intel_read_jedec_ids(info); flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI); -#ifdef CFG_FLASH_PROTECTION +#ifdef CONFIG_SYS_FLASH_PROTECTION /* read legacy lock/unlock bit from intel flash */ if (info->ext_addr) { info->legacy_unlock = flash_read_uchar (info, @@ -1717,7 +1717,7 @@ static int flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry) { debug ("flash detect cfi\n"); - for (info->portwidth = CFG_FLASH_CFI_WIDTH; + for (info->portwidth = CONFIG_SYS_FLASH_CFI_WIDTH; info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) { for (info->chipwidth = FLASH_CFI_BY8; info->chipwidth <= info->portwidth; @@ -1793,7 +1793,7 @@ ulong flash_get_size (ulong base, int banknum) info->ext_addr = 0; info->cfi_version = 0; -#ifdef CFG_FLASH_PROTECTION +#ifdef CONFIG_SYS_FLASH_PROTECTION info->legacy_unlock = 0; #endif @@ -1882,7 +1882,7 @@ ulong flash_get_size (ulong base, int banknum) debug ("erase_region_count = %d erase_region_size = %d\n", erase_region_count, erase_region_size); for (j = 0; j < erase_region_count; j++) { - if (sect_cnt >= CFG_MAX_FLASH_SECT) { + if (sect_cnt >= CONFIG_SYS_MAX_FLASH_SECT) { printf("ERROR: too many flash sectors\n"); break; } @@ -1947,41 +1947,41 @@ unsigned long flash_init (void) { unsigned long size = 0; int i; -#if defined(CFG_FLASH_AUTOPROTECT_LIST) +#if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST) struct apl_s { ulong start; ulong size; - } apl[] = CFG_FLASH_AUTOPROTECT_LIST; + } apl[] = CONFIG_SYS_FLASH_AUTOPROTECT_LIST; #endif -#ifdef CFG_FLASH_PROTECTION +#ifdef CONFIG_SYS_FLASH_PROTECTION char *s = getenv("unlock"); #endif -#define BANK_BASE(i) (((unsigned long [CFI_MAX_FLASH_BANKS])CFG_FLASH_BANKS_LIST)[i]) +#define BANK_BASE(i) (((unsigned long [CFI_MAX_FLASH_BANKS])CONFIG_SYS_FLASH_BANKS_LIST)[i]) /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; if (!flash_detect_legacy (BANK_BASE(i), i)) flash_get_size (BANK_BASE(i), i); size += flash_info[i].size; if (flash_info[i].flash_id == FLASH_UNKNOWN) { -#ifndef CFG_FLASH_QUIET_TEST +#ifndef CONFIG_SYS_FLASH_QUIET_TEST printf ("## Unknown FLASH on Bank %d " "- Size = 0x%08lx = %ld MB\n", i+1, flash_info[i].size, flash_info[i].size << 20); -#endif /* CFG_FLASH_QUIET_TEST */ +#endif /* CONFIG_SYS_FLASH_QUIET_TEST */ } -#ifdef CFG_FLASH_PROTECTION +#ifdef CONFIG_SYS_FLASH_PROTECTION else if ((s != NULL) && (strcmp(s, "yes") == 0)) { /* * Only the U-Boot image and it's environment * is protected, all other sectors are * unprotected (unlocked) if flash hardware - * protection is used (CFG_FLASH_PROTECTION) + * protection is used (CONFIG_SYS_FLASH_PROTECTION) * and the environment variable "unlock" is * set to "yes". */ @@ -2022,15 +2022,15 @@ unsigned long flash_init (void) &flash_info[i]); } } -#endif /* CFG_FLASH_PROTECTION */ +#endif /* CONFIG_SYS_FLASH_PROTECTION */ } /* Monitor protection ON by default */ -#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE) +#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - flash_get_info(CFG_MONITOR_BASE)); + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, + flash_get_info(CONFIG_SYS_MONITOR_BASE)); #endif /* Environment protection ON by default */ @@ -2049,7 +2049,7 @@ unsigned long flash_init (void) flash_get_info(CONFIG_ENV_ADDR_REDUND)); #endif -#if defined(CFG_FLASH_AUTOPROTECT_LIST) +#if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST) for (i = 0; i < (sizeof(apl) / sizeof(struct apl_s)); i++) { debug("autoprotecting from %08x to %08x\n", apl[i].start, apl[i].start + apl[i].size - 1); diff --git a/drivers/mtd/dataflash.c b/drivers/mtd/dataflash.c index 049da69..201e518 100644 --- a/drivers/mtd/dataflash.c +++ b/drivers/mtd/dataflash.c @@ -40,12 +40,12 @@ int AT91F_DataflashInit (void) int dfcode; int part; int last_part; - int found[CFG_MAX_DATAFLASH_BANKS]; + int found[CONFIG_SYS_MAX_DATAFLASH_BANKS]; unsigned char protected; AT91F_SpiInit (); - for (i = 0; i < CFG_MAX_DATAFLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++) { found[i] = 0; dataflash_info[i].Desc.state = IDLE; dataflash_info[i].id = 0; @@ -179,7 +179,7 @@ void AT91F_DataflashSetEnv (void) unsigned char s[32]; /* Will fit a long int in hex */ unsigned long start; - for (i = 0, part= 0; i < CFG_MAX_DATAFLASH_BANKS; i++) { + for (i = 0, part= 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++) { for(j = 0; j= CFG_MAX_FLASH_SECT) { + if (sect_cnt >= CONFIG_SYS_MAX_FLASH_SECT) { printf("ERROR: too many flash sectors\n"); break; } diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c index 4351824..7dda6c4 100644 --- a/drivers/mtd/nand/fsl_elbc_nand.c +++ b/drivers/mtd/nand/fsl_elbc_nand.c @@ -693,7 +693,7 @@ static struct fsl_elbc_ctrl *elbc_ctrl; static void fsl_elbc_ctrl_init(void) { - immap_t *im = (immap_t *)CFG_IMMR; + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; elbc_ctrl = kzalloc(sizeof(*elbc_ctrl), GFP_KERNEL); if (!elbc_ctrl) diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c index 71a0e4b..eeb19ff 100644 --- a/drivers/mtd/nand/nand.c +++ b/drivers/mtd/nand/nand.c @@ -24,15 +24,15 @@ #include #include -#ifndef CFG_NAND_BASE_LIST -#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +#ifndef CONFIG_SYS_NAND_BASE_LIST +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #endif int nand_curr_device = -1; -nand_info_t nand_info[CFG_MAX_NAND_DEVICE]; +nand_info_t nand_info[CONFIG_SYS_MAX_NAND_DEVICE]; -static struct nand_chip nand_chip[CFG_MAX_NAND_DEVICE]; -static ulong base_address[CFG_MAX_NAND_DEVICE] = CFG_NAND_BASE_LIST; +static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; +static ulong base_address[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST; static const char default_nand_name[] = "nand"; @@ -61,7 +61,7 @@ void nand_init(void) { int i; unsigned int size = 0; - for (i = 0; i < CFG_MAX_NAND_DEVICE; i++) { + for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) { nand_init_chip(&nand_info[i], &nand_chip[i], base_address[i]); size += nand_info[i].size / 1024; if (nand_curr_device == -1) @@ -69,7 +69,7 @@ void nand_init(void) } printf("%u MiB\n", size / 1024); -#ifdef CFG_NAND_SELECT_DEVICE +#ifdef CONFIG_SYS_NAND_SELECT_DEVICE /* * Select the chip in the board/cpu specific driver */ diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 0913bb8..fe34a48 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -492,7 +492,7 @@ EXPORT_SYMBOL_GPL(nand_wait_ready); void nand_wait_ready(struct mtd_info *mtd) { struct nand_chip *chip = mtd->priv; - u32 timeo = (CFG_HZ * 20) / 1000; + u32 timeo = (CONFIG_SYS_HZ * 20) / 1000; reset_timer(); @@ -831,9 +831,9 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *this) int state = this->state; if (state == FL_ERASING) - timeo = (CFG_HZ * 400) / 1000; + timeo = (CONFIG_SYS_HZ * 400) / 1000; else - timeo = (CFG_HZ * 20) / 1000; + timeo = (CONFIG_SYS_HZ * 20) / 1000; if ((state == FL_ERASING) && (this->options & NAND_IS_AND)) this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1); diff --git a/drivers/mtd/nand/s3c64xx.c b/drivers/mtd/nand/s3c64xx.c index 159fe76..edaf55a 100644 --- a/drivers/mtd/nand/s3c64xx.c +++ b/drivers/mtd/nand/s3c64xx.c @@ -141,7 +141,7 @@ static int s3c_nand_device_ready(struct mtd_info *mtdinfo) return !!(readl(NFSTAT) & NFSTAT_RnB); } -#ifdef CFG_S3C_NAND_HWECC +#ifdef CONFIG_SYS_S3C_NAND_HWECC /* * This function is called before encoding ecc codes to ready ecc engine. * Written by jsgood @@ -256,7 +256,7 @@ static int s3c_nand_correct_data(struct mtd_info *mtd, u_char *dat, return ret; } -#endif /* CFG_S3C_NAND_HWECC */ +#endif /* CONFIG_SYS_S3C_NAND_HWECC */ /* * Board-specific NAND initialization. The following members of the @@ -297,7 +297,7 @@ int board_nand_init(struct nand_chip *nand) nand->read_buf = nand_read_buf; #endif -#ifdef CFG_S3C_NAND_HWECC +#ifdef CONFIG_SYS_S3C_NAND_HWECC nand->ecc.hwctl = s3c_nand_enable_hwecc; nand->ecc.calculate = s3c_nand_calculate_ecc; nand->ecc.correct = s3c_nand_correct_data; @@ -307,11 +307,11 @@ int board_nand_init(struct nand_chip *nand) * board one day, it will get more complicated... */ nand->ecc.mode = NAND_ECC_HW; - nand->ecc.size = CFG_NAND_ECCSIZE; - nand->ecc.bytes = CFG_NAND_ECCBYTES; + nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE; + nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES; #else nand->ecc.mode = NAND_ECC_SOFT; -#endif /* ! CFG_S3C_NAND_HWECC */ +#endif /* ! CONFIG_SYS_S3C_NAND_HWECC */ nand->priv = nand_cs + chip_n++; diff --git a/drivers/mtd/nand_legacy/nand_legacy.c b/drivers/mtd/nand_legacy/nand_legacy.c index bf5565a..407e901 100644 --- a/drivers/mtd/nand_legacy/nand_legacy.c +++ b/drivers/mtd/nand_legacy/nand_legacy.c @@ -66,7 +66,7 @@ struct nand_oob_config { int eccvalid_pos; } oob_config = { {0}, 0, 0}; -struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE] = {{0}}; +struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE] = {{0}}; int curr_device = -1; /* Current NAND Device */ @@ -982,7 +982,7 @@ static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len, #ifdef CONFIG_OMAP1510 archflashwp(0,0); #endif -#ifdef CFG_NAND_WP +#ifdef CONFIG_SYS_NAND_WP NAND_WP_OFF(); #endif @@ -1036,7 +1036,7 @@ out: #ifdef CONFIG_OMAP1510 archflashwp(0,1); #endif -#ifdef CFG_NAND_WP +#ifdef CONFIG_SYS_NAND_WP NAND_WP_ON(); #endif @@ -1235,7 +1235,7 @@ int nand_legacy_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean) #ifdef CONFIG_OMAP1510 archflashwp(0,0); #endif -#ifdef CFG_NAND_WP +#ifdef CONFIG_SYS_NAND_WP NAND_WP_OFF(); #endif NAND_ENABLE_CE(nand); /* set pin low */ @@ -1321,7 +1321,7 @@ out: #ifdef CONFIG_OMAP1510 archflashwp(0,1); #endif -#ifdef CFG_NAND_WP +#ifdef CONFIG_SYS_NAND_WP NAND_WP_ON(); #endif @@ -1358,7 +1358,7 @@ unsigned long nand_probe(unsigned long physadr) #endif oob_config.badblock_pos = 5; - for (i=0; iChipRevId) == T3_ASIC_REV_5701) { pDevice->UseTaggedStatus = TRUE; - pUmDevice->timer_interval = CFG_HZ; + pUmDevice->timer_interval = CONFIG_SYS_HZ; } else { - pUmDevice->timer_interval = CFG_HZ / 50; + pUmDevice->timer_interval = CONFIG_SYS_HZ / 50; } /* Grab name .... */ @@ -458,15 +458,15 @@ int eth_init (bd_t * bis) pUmDevice->rx_last_cnt = pUmDevice->tx_last_cnt = 0; /* delay for 4 seconds */ - pUmDevice->delayed_link_ind = (4 * CFG_HZ) / pUmDevice->timer_interval; + pUmDevice->delayed_link_ind = (4 * CONFIG_SYS_HZ) / pUmDevice->timer_interval; - pUmDevice->adaptive_expiry = CFG_HZ / pUmDevice->timer_interval; + pUmDevice->adaptive_expiry = CONFIG_SYS_HZ / pUmDevice->timer_interval; /* Sometimes we get spurious ints. after reset when link is down. */ /* This field tells the isr to service the int. even if there is */ /* no status block update. */ pUmDevice->adapter_just_inited = - (3 * CFG_HZ) / pUmDevice->timer_interval; + (3 * CONFIG_SYS_HZ) / pUmDevice->timer_interval; /* Initialize 570x */ if (LM_InitializeAdapter (pDevice) != LM_STATUS_SUCCESS) { @@ -1046,9 +1046,9 @@ LM_STATUS MM_GetConfig (PLM_DEVICE_BLOCK pDevice) if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) { pDevice->UseTaggedStatus = TRUE; - pUmDevice->timer_interval = CFG_HZ; + pUmDevice->timer_interval = CONFIG_SYS_HZ; } else { - pUmDevice->timer_interval = CFG_HZ / 50; + pUmDevice->timer_interval = CONFIG_SYS_HZ / 50; } pDevice->TxPacketDescCnt = tx_pkt_desc_cnt[index]; diff --git a/drivers/net/bfin_mac.c b/drivers/net/bfin_mac.c index c5e74b8..504fd10 100644 --- a/drivers/net/bfin_mac.c +++ b/drivers/net/bfin_mac.c @@ -466,7 +466,7 @@ ADI_ETHER_BUFFER *SetupTxBuffer(int no) return buf; } -#if defined(CONFIG_POST) && defined(CFG_POST_ETHER) +#if defined(CONFIG_POST) && defined(CONFIG_SYS_POST_ETHER) int ether_post_test(int flags) { uchar buf[64]; diff --git a/drivers/net/cs8900.c b/drivers/net/cs8900.c index ae1983a..35a9baf 100644 --- a/drivers/net/cs8900.c +++ b/drivers/net/cs8900.c @@ -90,7 +90,7 @@ static void eth_reset (void) udelay (200000); /* Wait until the chip is reset */ - tmo = get_timer (0) + 1 * CFG_HZ; + tmo = get_timer (0) + 1 * CONFIG_SYS_HZ; while ((((us = get_reg_init_bus (PP_SelfSTAT)) & PP_SelfSTAT_InitD) == 0) && tmo < get_timer (0)) /*NOP*/; @@ -244,7 +244,7 @@ retry: #ifdef DEBUG printf ("cs: unable to send packet; retrying...\n"); #endif - for (tmo = get_timer (0) + 5 * CFG_HZ; get_timer (0) < tmo;) + for (tmo = get_timer (0) + 5 * CONFIG_SYS_HZ; get_timer (0) < tmo;) /*NOP*/; eth_reset (); eth_reginit (); @@ -257,7 +257,7 @@ retry: CS8900_RTDATA = *addr++; /* wait for transfer to succeed */ - tmo = get_timer (0) + 5 * CFG_HZ; + tmo = get_timer (0) + 5 * CONFIG_SYS_HZ; while ((s = get_reg (PP_TER) & ~0x1F) == 0) { if (get_timer (0) >= tmo) break; diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c index 3a61b80..ffb739d 100644 --- a/drivers/net/dm9000x.c +++ b/drivers/net/dm9000x.c @@ -447,7 +447,7 @@ eth_send(volatile void *packet, int length) DM9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */ /* wait for end of transmission */ - tmo = get_timer(0) + 5 * CFG_HZ; + tmo = get_timer(0) + 5 * CONFIG_SYS_HZ; while ( !(DM9000_ior(DM9000_NSR) & (NSR_TX1END | NSR_TX2END)) || !(DM9000_ior(DM9000_ISR) & IMR_PTM) ) { if (get_timer(0) >= tmo) { diff --git a/drivers/net/eepro100.c b/drivers/net/eepro100.c index d6539c0..9c06b25 100644 --- a/drivers/net/eepro100.c +++ b/drivers/net/eepro100.c @@ -194,14 +194,14 @@ struct descriptor { /* A generic descriptor. */ unsigned char params[0]; }; -#define CFG_CMD_EL 0x8000 -#define CFG_CMD_SUSPEND 0x4000 -#define CFG_CMD_INT 0x2000 -#define CFG_CMD_IAS 0x0001 /* individual address setup */ -#define CFG_CMD_CONFIGURE 0x0002 /* configure */ +#define CONFIG_SYS_CMD_EL 0x8000 +#define CONFIG_SYS_CMD_SUSPEND 0x4000 +#define CONFIG_SYS_CMD_INT 0x2000 +#define CONFIG_SYS_CMD_IAS 0x0001 /* individual address setup */ +#define CONFIG_SYS_CMD_CONFIGURE 0x0002 /* configure */ -#define CFG_STATUS_C 0x8000 -#define CFG_STATUS_OK 0x2000 +#define CONFIG_SYS_STATUS_C 0x8000 +#define CONFIG_SYS_STATUS_OK 0x2000 /* Misc. */ @@ -529,7 +529,7 @@ static int eepro100_init (struct eth_device *dev, bd_t * bis) tx_next = ((tx_next + 1) % NUM_TX_DESC); cfg_cmd = (struct descriptor *) &tx_ring[tx_cur]; - cfg_cmd->command = cpu_to_le16 ((CFG_CMD_SUSPEND | CFG_CMD_CONFIGURE)); + cfg_cmd->command = cpu_to_le16 ((CONFIG_SYS_CMD_SUSPEND | CONFIG_SYS_CMD_CONFIGURE)); cfg_cmd->status = 0; cfg_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next])); @@ -537,7 +537,7 @@ static int eepro100_init (struct eth_device *dev, bd_t * bis) sizeof (i82558_config_cmd)); if (!wait_for_eepro100 (dev)) { - printf ("Error---CFG_CMD_CONFIGURE: Can not reset ethernet controller.\n"); + printf ("Error---CONFIG_SYS_CMD_CONFIGURE: Can not reset ethernet controller.\n"); goto Done; } @@ -545,7 +545,7 @@ static int eepro100_init (struct eth_device *dev, bd_t * bis) OUTW (dev, SCB_M | CU_START, SCBCmd); for (i = 0; - !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C); + !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C); i++) { if (i >= TOUT_LOOP) { printf ("%s: Tx error buffer not ready\n", dev->name); @@ -553,7 +553,7 @@ static int eepro100_init (struct eth_device *dev, bd_t * bis) } } - if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) { + if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) { printf ("TX error status = 0x%08X\n", le16_to_cpu (tx_ring[tx_cur].status)); goto Done; @@ -565,7 +565,7 @@ static int eepro100_init (struct eth_device *dev, bd_t * bis) tx_next = ((tx_next + 1) % NUM_TX_DESC); ias_cmd = (struct descriptor *) &tx_ring[tx_cur]; - ias_cmd->command = cpu_to_le16 ((CFG_CMD_SUSPEND | CFG_CMD_IAS)); + ias_cmd->command = cpu_to_le16 ((CONFIG_SYS_CMD_SUSPEND | CONFIG_SYS_CMD_IAS)); ias_cmd->status = 0; ias_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next])); @@ -581,7 +581,7 @@ static int eepro100_init (struct eth_device *dev, bd_t * bis) OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer); OUTW (dev, SCB_M | CU_START, SCBCmd); - for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C); + for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C); i++) { if (i >= TOUT_LOOP) { printf ("%s: Tx error buffer not ready\n", @@ -590,7 +590,7 @@ static int eepro100_init (struct eth_device *dev, bd_t * bis) } } - if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) { + if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) { printf ("TX error status = 0x%08X\n", le16_to_cpu (tx_ring[tx_cur].status)); goto Done; @@ -640,7 +640,7 @@ static int eepro100_send (struct eth_device *dev, volatile void *packet, int len OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer); OUTW (dev, SCB_M | CU_START, SCBCmd); - for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C); + for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C); i++) { if (i >= TOUT_LOOP) { printf ("%s: Tx error buffer not ready\n", dev->name); @@ -648,7 +648,7 @@ static int eepro100_send (struct eth_device *dev, volatile void *packet, int len } } - if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) { + if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) { printf ("TX error status = 0x%08X\n", le16_to_cpu (tx_ring[tx_cur].status)); goto Done; diff --git a/drivers/net/fsl_mcdmafec.c b/drivers/net/fsl_mcdmafec.c index 59524a5..d056010 100644 --- a/drivers/net/fsl_mcdmafec.c +++ b/drivers/net/fsl_mcdmafec.c @@ -56,12 +56,12 @@ DECLARE_GLOBAL_DATA_PTR; struct fec_info_dma fec_info[] = { -#ifdef CFG_FEC0_IOBASE +#ifdef CONFIG_SYS_FEC0_IOBASE { 0, /* index */ - CFG_FEC0_IOBASE, /* io base */ - CFG_FEC0_PINMUX, /* gpio pin muxing */ - CFG_FEC0_MIIBASE, /* mii base */ + CONFIG_SYS_FEC0_IOBASE, /* io base */ + CONFIG_SYS_FEC0_PINMUX, /* gpio pin muxing */ + CONFIG_SYS_FEC0_MIIBASE, /* mii base */ -1, /* phy_addr */ 0, /* duplex and speed */ 0, /* phy name */ @@ -83,17 +83,17 @@ struct fec_info_dma fec_info[] = { 0, /* cleanTbdNum */ }, #endif -#ifdef CFG_FEC1_IOBASE +#ifdef CONFIG_SYS_FEC1_IOBASE { 1, /* index */ - CFG_FEC1_IOBASE, /* io base */ - CFG_FEC1_PINMUX, /* gpio pin muxing */ - CFG_FEC1_MIIBASE, /* mii base */ + CONFIG_SYS_FEC1_IOBASE, /* io base */ + CONFIG_SYS_FEC1_PINMUX, /* gpio pin muxing */ + CONFIG_SYS_FEC1_MIIBASE, /* mii base */ -1, /* phy_addr */ 0, /* duplex and speed */ 0, /* phy name */ 0, /* phy name init */ -#ifdef CFG_DMA_USE_INTSRAM +#ifdef CONFIG_SYS_DMA_USE_INTSRAM (cbd_t *)DBUF_LENGTH, /* RX BD */ #else 0, /* RX BD */ @@ -203,7 +203,7 @@ static int fec_send(struct eth_device *dev, volatile void *packet, int length) miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &phyStatus); /* process all the consumed TBDs */ - while (info->cleanTbdNum < CFG_TX_ETH_BUFFER) { + while (info->cleanTbdNum < CONFIG_SYS_TX_ETH_BUFFER) { pUsedTbd = &info->txbd[info->usedTbdIdx]; if (pUsedTbd->cbd_sc & BD_ENET_TX_READY) { #ifdef ET_DEBUG @@ -214,14 +214,14 @@ static int fec_send(struct eth_device *dev, volatile void *packet, int length) } /* clean this buffer descriptor */ - if (info->usedTbdIdx == (CFG_TX_ETH_BUFFER - 1)) + if (info->usedTbdIdx == (CONFIG_SYS_TX_ETH_BUFFER - 1)) pUsedTbd->cbd_sc = BD_ENET_TX_WRAP; else pUsedTbd->cbd_sc = 0; /* update some indeces for a correct handling of the TBD ring */ info->cleanTbdNum++; - info->usedTbdIdx = (info->usedTbdIdx + 1) % CFG_TX_ETH_BUFFER; + info->usedTbdIdx = (info->usedTbdIdx + 1) % CONFIG_SYS_TX_ETH_BUFFER; } /* Check for valid length of data. */ @@ -240,7 +240,7 @@ static int fec_send(struct eth_device *dev, volatile void *packet, int length) pTbd->cbd_datlen = length; pTbd->cbd_bufaddr = (u32) packet; pTbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY; - info->txIdx = (info->txIdx + 1) % CFG_TX_ETH_BUFFER; + info->txIdx = (info->txIdx + 1) % CONFIG_SYS_TX_ETH_BUFFER; /* Enable DMA transmit task */ MCD_continDma(info->txTask); @@ -379,15 +379,15 @@ static int fec_init(struct eth_device *dev, bd_t * bd) fec_halt(dev); #if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \ - defined (CFG_DISCOVER_PHY) + defined (CONFIG_SYS_DISCOVER_PHY) mii_init(); set_fec_duplex_speed(fecp, bd, info->dup_spd); #else -#ifndef CFG_DISCOVER_PHY +#ifndef CONFIG_SYS_DISCOVER_PHY set_fec_duplex_speed(fecp, bd, (FECDUPLEX << 16) | FECSPEED); -#endif /* ifndef CFG_DISCOVER_PHY */ +#endif /* ifndef CONFIG_SYS_DISCOVER_PHY */ #endif /* CONFIG_CMD_MII || CONFIG_MII */ /* We use strictly polling mode only */ @@ -397,7 +397,7 @@ static int fec_init(struct eth_device *dev, bd_t * bd) fecp->eir = 0xffffffff; /* Set station address */ - if ((u32) fecp == CFG_FEC0_IOBASE) { + if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE) { fec_set_hwaddr(fecp, bd->bi_enetaddr); } else { fec_set_hwaddr(fecp, bd->bi_enet1addr); @@ -421,15 +421,15 @@ static int fec_init(struct eth_device *dev, bd_t * bd) /* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) * Settings: Last, Tx CRC */ - for (i = 0; i < CFG_TX_ETH_BUFFER; i++) { + for (i = 0; i < CONFIG_SYS_TX_ETH_BUFFER; i++) { info->txbd[i].cbd_sc = 0; info->txbd[i].cbd_datlen = 0; info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]); } - info->txbd[CFG_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP; + info->txbd[CONFIG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP; info->usedTbdIdx = 0; - info->cleanTbdNum = CFG_TX_ETH_BUFFER; + info->cleanTbdNum = CONFIG_SYS_TX_ETH_BUFFER; /* Set Rx FIFO alarm and granularity value */ fecp->rfcr = 0x0c000000; @@ -516,14 +516,14 @@ int mcdmafec_initialize(bd_t * bis) { struct eth_device *dev; int i; -#ifdef CFG_DMA_USE_INTSRAM - u32 tmp = CFG_INTSRAM + 0x2000; +#ifdef CONFIG_SYS_DMA_USE_INTSRAM + u32 tmp = CONFIG_SYS_INTSRAM + 0x2000; #endif for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) { dev = - (struct eth_device *)memalign(CFG_CACHELINE_SIZE, + (struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof *dev); if (dev == NULL) hang(); @@ -539,7 +539,7 @@ int mcdmafec_initialize(bd_t * bis) dev->recv = fec_recv; /* setup Receive and Transmit buffer descriptor */ -#ifdef CFG_DMA_USE_INTSRAM +#ifdef CONFIG_SYS_DMA_USE_INTSRAM fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp); tmp = (u32)fec_info[i].rxbd; fec_info[i].txbd = @@ -548,17 +548,17 @@ int mcdmafec_initialize(bd_t * bis) tmp = (u32)fec_info[i].txbd; fec_info[i].txbuf = (char *)((u32)fec_info[i].txbuf + tmp + - (CFG_TX_ETH_BUFFER * sizeof(cbd_t))); + (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); tmp = (u32)fec_info[i].txbuf; #else fec_info[i].rxbd = - (cbd_t *) memalign(CFG_CACHELINE_SIZE, + (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE, (PKTBUFSRX * sizeof(cbd_t))); fec_info[i].txbd = - (cbd_t *) memalign(CFG_CACHELINE_SIZE, - (CFG_TX_ETH_BUFFER * sizeof(cbd_t))); + (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE, + (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); fec_info[i].txbuf = - (char *)memalign(CFG_CACHELINE_SIZE, DBUF_LENGTH); + (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH); #endif #ifdef ET_DEBUG @@ -566,7 +566,7 @@ int mcdmafec_initialize(bd_t * bis) (int)fec_info[i].rxbd, (int)fec_info[i].txbd); #endif - fec_info[i].phy_name = (char *)memalign(CFG_CACHELINE_SIZE, 32); + fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32); eth_register(dev); diff --git a/drivers/net/lan91c96.c b/drivers/net/lan91c96.c index c23a400..318bdf4 100644 --- a/drivers/net/lan91c96.c +++ b/drivers/net/lan91c96.c @@ -267,7 +267,7 @@ static void smc_shutdown (void); static int poll4int (byte mask, int timeout) { - int tmo = get_timer (0) + timeout * CFG_HZ; + int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ; int is_timeout = 0; word old_bank = SMC_inw (LAN91C96_BANK_SELECT); diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 08bebf7..98e8c73 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -28,7 +28,7 @@ * allocate our own, but we need one such buffer in case a packet * wraps around the DMA ring so that we have to copy it. * - * Therefore, define CFG_RX_ETH_BUFFER to 1 in the board-specific + * Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific * configuration header. This way, the core allocates one RX buffer * and one TX buffer, each of which can hold a ethernet packet of * maximum size. @@ -52,11 +52,11 @@ #define barrier() asm volatile("" ::: "memory") -#define CFG_MACB_RX_BUFFER_SIZE 4096 -#define CFG_MACB_RX_RING_SIZE (CFG_MACB_RX_BUFFER_SIZE / 128) -#define CFG_MACB_TX_RING_SIZE 16 -#define CFG_MACB_TX_TIMEOUT 1000 -#define CFG_MACB_AUTONEG_TIMEOUT 5000000 +#define CONFIG_SYS_MACB_RX_BUFFER_SIZE 4096 +#define CONFIG_SYS_MACB_RX_RING_SIZE (CONFIG_SYS_MACB_RX_BUFFER_SIZE / 128) +#define CONFIG_SYS_MACB_TX_RING_SIZE 16 +#define CONFIG_SYS_MACB_TX_TIMEOUT 1000 +#define CONFIG_SYS_MACB_AUTONEG_TIMEOUT 5000000 struct macb_dma_desc { u32 addr; @@ -178,7 +178,7 @@ static int macb_send(struct eth_device *netdev, volatile void *packet, ctrl = length & TXBUF_FRMLEN_MASK; ctrl |= TXBUF_FRAME_END; - if (tx_head == (CFG_MACB_TX_RING_SIZE - 1)) { + if (tx_head == (CONFIG_SYS_MACB_TX_RING_SIZE - 1)) { ctrl |= TXBUF_WRAP; macb->tx_head = 0; } else @@ -193,7 +193,7 @@ static int macb_send(struct eth_device *netdev, volatile void *packet, * I guess this is necessary because the networking core may * re-use the transmit buffer as soon as we return... */ - for (i = 0; i <= CFG_MACB_TX_TIMEOUT; i++) { + for (i = 0; i <= CONFIG_SYS_MACB_TX_TIMEOUT; i++) { barrier(); ctrl = macb->tx_ring[tx_head].ctrl; if (ctrl & TXBUF_USED) @@ -203,7 +203,7 @@ static int macb_send(struct eth_device *netdev, volatile void *packet, dma_unmap_single(packet, length, paddr); - if (i <= CFG_MACB_TX_TIMEOUT) { + if (i <= CONFIG_SYS_MACB_TX_TIMEOUT) { if (ctrl & TXBUF_UNDERRUN) printf("%s: TX underrun\n", netdev->name); if (ctrl & TXBUF_EXHAUSTED) @@ -226,7 +226,7 @@ static void reclaim_rx_buffers(struct macb_device *macb, while (i > new_tail) { macb->rx_ring[i].addr &= ~RXADDR_USED; i++; - if (i > CFG_MACB_RX_RING_SIZE) + if (i > CONFIG_SYS_MACB_RX_RING_SIZE) i = 0; } @@ -265,7 +265,7 @@ static int macb_recv(struct eth_device *netdev) if (wrapped) { unsigned int headlen, taillen; - headlen = 128 * (CFG_MACB_RX_RING_SIZE + headlen = 128 * (CONFIG_SYS_MACB_RX_RING_SIZE - macb->rx_tail); taillen = length - headlen; memcpy((void *)NetRxPackets[0], @@ -276,11 +276,11 @@ static int macb_recv(struct eth_device *netdev) } NetReceive(buffer, length); - if (++rx_tail >= CFG_MACB_RX_RING_SIZE) + if (++rx_tail >= CONFIG_SYS_MACB_RX_RING_SIZE) rx_tail = 0; reclaim_rx_buffers(macb, rx_tail); } else { - if (++rx_tail >= CFG_MACB_RX_RING_SIZE) { + if (++rx_tail >= CONFIG_SYS_MACB_RX_RING_SIZE) { wrapped = 1; rx_tail = 0; } @@ -303,7 +303,7 @@ static void macb_phy_reset(struct macb_device *macb) macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE | BMCR_ANRESTART)); - for (i = 0; i < CFG_MACB_AUTONEG_TIMEOUT / 100; i++) { + for (i = 0; i < CONFIG_SYS_MACB_AUTONEG_TIMEOUT / 100; i++) { status = macb_mdio_read(macb, MII_BMSR); if (status & BMSR_ANEGCOMPLETE) break; @@ -337,7 +337,7 @@ static int macb_phy_init(struct macb_device *macb) /* Try to re-negotiate if we don't have link already. */ macb_phy_reset(macb); - for (i = 0; i < CFG_MACB_AUTONEG_TIMEOUT / 100; i++) { + for (i = 0; i < CONFIG_SYS_MACB_AUTONEG_TIMEOUT / 100; i++) { status = macb_mdio_read(macb, MII_BMSR); if (status & BMSR_LSTATUS) break; @@ -388,16 +388,16 @@ static int macb_init(struct eth_device *netdev, bd_t *bd) /* initialize DMA descriptors */ paddr = macb->rx_buffer_dma; - for (i = 0; i < CFG_MACB_RX_RING_SIZE; i++) { - if (i == (CFG_MACB_RX_RING_SIZE - 1)) + for (i = 0; i < CONFIG_SYS_MACB_RX_RING_SIZE; i++) { + if (i == (CONFIG_SYS_MACB_RX_RING_SIZE - 1)) paddr |= RXADDR_WRAP; macb->rx_ring[i].addr = paddr; macb->rx_ring[i].ctrl = 0; paddr += 128; } - for (i = 0; i < CFG_MACB_TX_RING_SIZE; i++) { + for (i = 0; i < CONFIG_SYS_MACB_TX_RING_SIZE; i++) { macb->tx_ring[i].addr = 0; - if (i == (CFG_MACB_TX_RING_SIZE - 1)) + if (i == (CONFIG_SYS_MACB_TX_RING_SIZE - 1)) macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP; else macb->tx_ring[i].ctrl = TXBUF_USED; @@ -473,12 +473,12 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) netdev = &macb->netdev; - macb->rx_buffer = dma_alloc_coherent(CFG_MACB_RX_BUFFER_SIZE, + macb->rx_buffer = dma_alloc_coherent(CONFIG_SYS_MACB_RX_BUFFER_SIZE, &macb->rx_buffer_dma); - macb->rx_ring = dma_alloc_coherent(CFG_MACB_RX_RING_SIZE + macb->rx_ring = dma_alloc_coherent(CONFIG_SYS_MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc), &macb->rx_ring_dma); - macb->tx_ring = dma_alloc_coherent(CFG_MACB_TX_RING_SIZE + macb->tx_ring = dma_alloc_coherent(CONFIG_SYS_MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc), &macb->tx_ring_dma); diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c index f93cf59..c00474e 100644 --- a/drivers/net/mcffec.c +++ b/drivers/net/mcffec.c @@ -51,12 +51,12 @@ DECLARE_GLOBAL_DATA_PTR; struct fec_info_s fec_info[] = { -#ifdef CFG_FEC0_IOBASE +#ifdef CONFIG_SYS_FEC0_IOBASE { 0, /* index */ - CFG_FEC0_IOBASE, /* io base */ - CFG_FEC0_PINMUX, /* gpio pin muxing */ - CFG_FEC0_MIIBASE, /* mii base */ + CONFIG_SYS_FEC0_IOBASE, /* io base */ + CONFIG_SYS_FEC0_PINMUX, /* gpio pin muxing */ + CONFIG_SYS_FEC0_MIIBASE, /* mii base */ -1, /* phy_addr */ 0, /* duplex and speed */ 0, /* phy name */ @@ -70,17 +70,17 @@ struct fec_info_s fec_info[] = { (struct fec_info_s *)-1, }, #endif -#ifdef CFG_FEC1_IOBASE +#ifdef CONFIG_SYS_FEC1_IOBASE { 1, /* index */ - CFG_FEC1_IOBASE, /* io base */ - CFG_FEC1_PINMUX, /* gpio pin muxing */ - CFG_FEC1_MIIBASE, /* mii base */ + CONFIG_SYS_FEC1_IOBASE, /* io base */ + CONFIG_SYS_FEC1_PINMUX, /* gpio pin muxing */ + CONFIG_SYS_FEC1_MIIBASE, /* mii base */ -1, /* phy_addr */ 0, /* duplex and speed */ 0, /* phy name */ 0, /* phy name init */ -#ifdef CFG_FEC_BUF_USE_SRAM +#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM (cbd_t *)DBUF_LENGTH, /* RX BD */ #else 0, /* RX BD */ @@ -103,7 +103,7 @@ void fec_reset(struct eth_device *dev); extern int fecpin_setclear(struct eth_device *dev, int setclear); -#ifdef CFG_DISCOVER_PHY +#ifdef CONFIG_SYS_DISCOVER_PHY extern void __mii_init(void); extern uint mii_send(uint mii_cmd); extern int mii_discover_phy(struct eth_device *dev); @@ -175,7 +175,7 @@ int fec_send(struct eth_device *dev, volatile void *packet, int length) /* Activate transmit Buffer Descriptor polling */ fecp->tdar = 0x01000000; /* Descriptor polling active */ -#ifndef CFG_FEC_BUF_USE_SRAM +#ifndef CONFIG_SYS_FEC_BUF_USE_SRAM /* * FEC unable to initial transmit data packet. * A nop will ensure the descriptor polling active completed. @@ -187,7 +187,7 @@ int fec_send(struct eth_device *dev, volatile void *packet, int length) #endif -#ifdef CFG_UNIFY_CACHE +#ifdef CONFIG_SYS_UNIFY_CACHE icache_invalid(); #endif @@ -222,9 +222,9 @@ int fec_recv(struct eth_device *dev) int length; for (;;) { -#ifndef CFG_FEC_BUF_USE_SRAM +#ifndef CONFIG_SYS_FEC_BUF_USE_SRAM #endif -#ifdef CFG_UNIFY_CACHE +#ifdef CONFIG_SYS_UNIFY_CACHE icache_invalid(); #endif /* section 16.9.23.2 */ @@ -435,15 +435,15 @@ int fec_init(struct eth_device *dev, bd_t * bd) fec_reset(dev); #if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \ - defined (CFG_DISCOVER_PHY) + defined (CONFIG_SYS_DISCOVER_PHY) mii_init(); setFecDuplexSpeed(fecp, bd, info->dup_spd); #else -#ifndef CFG_DISCOVER_PHY +#ifndef CONFIG_SYS_DISCOVER_PHY setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED); -#endif /* ifndef CFG_DISCOVER_PHY */ +#endif /* ifndef CONFIG_SYS_DISCOVER_PHY */ #endif /* CONFIG_CMD_MII || CONFIG_MII */ /* We use strictly polling mode only */ @@ -453,9 +453,9 @@ int fec_init(struct eth_device *dev, bd_t * bd) fecp->eir = 0xffffffff; /* Set station address */ - if ((u32) fecp == CFG_FEC0_IOBASE) { -#ifdef CFG_FEC1_IOBASE - volatile fec_t *fecp1 = (fec_t *) (CFG_FEC1_IOBASE); + if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE) { +#ifdef CONFIG_SYS_FEC1_IOBASE + volatile fec_t *fecp1 = (fec_t *) (CONFIG_SYS_FEC1_IOBASE); ea = &bd->bi_enet1addr[0]; fecp1->palr = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); @@ -466,14 +466,14 @@ int fec_init(struct eth_device *dev, bd_t * bd) (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); fecp->paur = (ea[4] << 24) | (ea[5] << 16); } else { -#ifdef CFG_FEC0_IOBASE - volatile fec_t *fecp0 = (fec_t *) (CFG_FEC0_IOBASE); +#ifdef CONFIG_SYS_FEC0_IOBASE + volatile fec_t *fecp0 = (fec_t *) (CONFIG_SYS_FEC0_IOBASE); ea = &bd->bi_enetaddr[0]; fecp0->palr = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); fecp0->paur = (ea[4] << 24) | (ea[5] << 16); #endif -#ifdef CFG_FEC1_IOBASE +#ifdef CONFIG_SYS_FEC1_IOBASE ea = &bd->bi_enet1addr[0]; fecp->palr = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); @@ -568,14 +568,14 @@ int mcffec_initialize(bd_t * bis) { struct eth_device *dev; int i; -#ifdef CFG_FEC_BUF_USE_SRAM - u32 tmp = CFG_INIT_RAM_ADDR + 0x1000; +#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM + u32 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000; #endif for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) { dev = - (struct eth_device *)memalign(CFG_CACHELINE_SIZE, + (struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof *dev); if (dev == NULL) hang(); @@ -591,7 +591,7 @@ int mcffec_initialize(bd_t * bis) dev->recv = fec_recv; /* setup Receive and Transmit buffer descriptor */ -#ifdef CFG_FEC_BUF_USE_SRAM +#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp); tmp = (u32)fec_info[i].rxbd; fec_info[i].txbd = @@ -600,17 +600,17 @@ int mcffec_initialize(bd_t * bis) tmp = (u32)fec_info[i].txbd; fec_info[i].txbuf = (char *)((u32)fec_info[i].txbuf + tmp + - (CFG_TX_ETH_BUFFER * sizeof(cbd_t))); + (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); tmp = (u32)fec_info[i].txbuf; #else fec_info[i].rxbd = - (cbd_t *) memalign(CFG_CACHELINE_SIZE, + (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE, (PKTBUFSRX * sizeof(cbd_t))); fec_info[i].txbd = - (cbd_t *) memalign(CFG_CACHELINE_SIZE, + (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE, (TX_BUF_CNT * sizeof(cbd_t))); fec_info[i].txbuf = - (char *)memalign(CFG_CACHELINE_SIZE, DBUF_LENGTH); + (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH); #endif #ifdef ET_DEBUG @@ -618,7 +618,7 @@ int mcffec_initialize(bd_t * bis) (int)fec_info[i].rxbd, (int)fec_info[i].txbd); #endif - fec_info[i].phy_name = (char *)memalign(CFG_CACHELINE_SIZE, 32); + fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32); eth_register(dev); diff --git a/drivers/net/ne2000_base.c b/drivers/net/ne2000_base.c index 4a07708..f93f932 100644 --- a/drivers/net/ne2000_base.c +++ b/drivers/net/ne2000_base.c @@ -740,7 +740,7 @@ int eth_send(volatile void *packet, int length) { pkey = -1; dp83902a_send((u8 *) packet, length, 666); - tmo = get_timer (0) + TOUT * CFG_HZ; + tmo = get_timer (0) + TOUT * CONFIG_SYS_HZ; while(1) { dp83902a_poll(); if (pkey != -1) { diff --git a/drivers/net/netarm_eth.c b/drivers/net/netarm_eth.c index c011809..c9e324e 100644 --- a/drivers/net/netarm_eth.c +++ b/drivers/net/netarm_eth.c @@ -56,7 +56,7 @@ static void na_mii_write (int reg, int value) int mii_addr; /* Select register */ - mii_addr = CFG_ETH_PHY_ADDR + reg; + mii_addr = CONFIG_SYS_ETH_PHY_ADDR + reg; SET_EADDR (NETARM_ETH_MII_ADDR, mii_addr); /* Write value */ SET_EADDR (NETARM_ETH_MII_WRITE, value); @@ -68,7 +68,7 @@ static unsigned int na_mii_read (int reg) int mii_addr, val; /* Select register */ - mii_addr = CFG_ETH_PHY_ADDR + reg; + mii_addr = CONFIG_SYS_ETH_PHY_ADDR + reg; SET_EADDR (NETARM_ETH_MII_ADDR, mii_addr); /* do one management cycle */ SET_EADDR (NETARM_ETH_MII_CMD, diff --git a/drivers/net/ns7520_eth.c b/drivers/net/ns7520_eth.c index e19c223..c28726e 100644 --- a/drivers/net/ns7520_eth.c +++ b/drivers/net/ns7520_eth.c @@ -86,8 +86,8 @@ static int nDebugLvl = DEBUG_ERROR_CRIT; # define ASSERT(expr, func) #endif /* DEBUG */ -#define NS7520_MII_NEG_DELAY (5*CFG_HZ) /* in s */ -#define TX_TIMEOUT (5*CFG_HZ) /* in s */ +#define NS7520_MII_NEG_DELAY (5*CONFIG_SYS_HZ) /* in s */ +#define TX_TIMEOUT (5*CONFIG_SYS_HZ) /* in s */ #define RX_STALL_WORKAROUND_CNT 100 static int ns7520_eth_reset(void); diff --git a/drivers/net/ns9750_eth.c b/drivers/net/ns9750_eth.c index cade831..d4901b4 100644 --- a/drivers/net/ns9750_eth.c +++ b/drivers/net/ns9750_eth.c @@ -90,8 +90,8 @@ static int nDebugLvl = DEBUG_ERROR_CRIT; # define ASSERT(expr, func) #endif /* DEBUG */ -#define NS9750_MII_NEG_DELAY (5*CFG_HZ) /* in s */ -#define TX_TIMEOUT (5*CFG_HZ) /* in s */ +#define NS9750_MII_NEG_DELAY (5*CONFIG_SYS_HZ) /* in s */ +#define TX_TIMEOUT (5*CONFIG_SYS_HZ) /* in s */ /* @TODO move it to eeprom.h */ #define FS_EEPROM_AUTONEG_MASK 0x7 diff --git a/drivers/net/phy/miiphybb.c b/drivers/net/phy/miiphybb.c index 6446012..e3c163a 100644 --- a/drivers/net/phy/miiphybb.c +++ b/drivers/net/phy/miiphybb.c @@ -39,7 +39,7 @@ static void miiphy_pre (char read, unsigned char addr, unsigned char reg) { int j; /* counter */ #if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM)) - volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT); + volatile ioport_t *iop = ioport_addr ((immap_t *) CONFIG_SYS_IMMR, MDIO_PORT); #endif /* @@ -124,7 +124,7 @@ int bb_miiphy_read (char *devname, unsigned char addr, short rdreg; /* register working value */ int j; /* counter */ #if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM)) - volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT); + volatile ioport_t *iop = ioport_addr ((immap_t *) CONFIG_SYS_IMMR, MDIO_PORT); #endif miiphy_pre (1, addr, reg); @@ -191,7 +191,7 @@ int bb_miiphy_write (char *devname, unsigned char addr, { int j; /* counter */ #if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM)) - volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT); + volatile ioport_t *iop = ioport_addr ((immap_t *) CONFIG_SYS_IMMR, MDIO_PORT); #endif miiphy_pre (0, addr, reg); diff --git a/drivers/net/sk98lin/h/skdrv1st.h b/drivers/net/sk98lin/h/skdrv1st.h index af34d7b..8d372b5 100644 --- a/drivers/net/sk98lin/h/skdrv1st.h +++ b/drivers/net/sk98lin/h/skdrv1st.h @@ -174,7 +174,7 @@ typedef struct s_AC SK_AC; #if 0 #define SK_TICKS_PER_SEC HZ #else -#define SK_TICKS_PER_SEC CFG_HZ +#define SK_TICKS_PER_SEC CONFIG_SYS_HZ #endif #define SK_MEM_MAPPED_IO diff --git a/drivers/net/sk98lin/h/skgehw.h b/drivers/net/sk98lin/h/skgehw.h index 52dc83f..8aad442 100644 --- a/drivers/net/sk98lin/h/skgehw.h +++ b/drivers/net/sk98lin/h/skgehw.h @@ -1107,10 +1107,10 @@ extern "C" { /* Values of connector and PMD type comply to SysKonnect internal std */ /* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */ -#define CFG_CHIP_R_MSK (0xf<<4) /* Bit 7.. 4: Chip Revision */ +#define CONFIG_SYS_CHIP_R_MSK (0xf<<4) /* Bit 7.. 4: Chip Revision */ /* Bit 3.. 2: reserved */ -#define CFG_DIS_M2_CLK BIT_1S /* Disable Clock for 2nd MAC */ -#define CFG_SNG_MAC BIT_0S /* MAC Config: 0=2 MACs / 1=1 MAC*/ +#define CONFIG_SYS_DIS_M2_CLK BIT_1S /* Disable Clock for 2nd MAC */ +#define CONFIG_SYS_SNG_MAC BIT_0S /* MAC Config: 0=2 MACs / 1=1 MAC*/ /* B2_CHIP_ID 8 bit Chip Identification Number */ #define CHIP_ID_GENESIS 0x0a /* Chip ID for GENESIS */ diff --git a/drivers/net/sk98lin/skgeinit.c b/drivers/net/sk98lin/skgeinit.c index ab740c7..df63f27 100644 --- a/drivers/net/sk98lin/skgeinit.c +++ b/drivers/net/sk98lin/skgeinit.c @@ -1882,10 +1882,10 @@ SK_IOC IoC) /* IO context */ /* read number of MACs */ SK_IN8(IoC, B2_MAC_CFG, &Byte); - pAC->GIni.GIMacsFound = (Byte & CFG_SNG_MAC) ? 1 : 2; + pAC->GIni.GIMacsFound = (Byte & CONFIG_SYS_SNG_MAC) ? 1 : 2; /* get Chip Revision Number */ - pAC->GIni.GIChipRev = (SK_U8)((Byte & CFG_CHIP_R_MSK) >> 4); + pAC->GIni.GIChipRev = (SK_U8)((Byte & CONFIG_SYS_CHIP_R_MSK) >> 4); /* get diff. PCI parameters */ SK_IN16(IoC, B0_CTST, &CtrlStat); diff --git a/drivers/net/sk98lin/u-boot_compat.h b/drivers/net/sk98lin/u-boot_compat.h index 1e385f8..cadf402 100644 --- a/drivers/net/sk98lin/u-boot_compat.h +++ b/drivers/net/sk98lin/u-boot_compat.h @@ -54,7 +54,7 @@ #define EAGAIN 2 #define EBUSY 3 -#define HZ CFG_HZ +#define HZ CONFIG_SYS_HZ #define printk printf diff --git a/drivers/net/smc91111.c b/drivers/net/smc91111.c index e8b235b..82abb02 100644 --- a/drivers/net/smc91111.c +++ b/drivers/net/smc91111.c @@ -383,7 +383,7 @@ static void smc_write_phy_register(byte phyreg, word phydata); static int poll4int (byte mask, int timeout) { - int tmo = get_timer (0) + timeout * CFG_HZ; + int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ; int is_timeout = 0; word old_bank = SMC_inw (BSR_REG); diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index e34076f..d7da081 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -305,8 +305,8 @@ static int init_phy(struct eth_device *dev) volatile tsec_t *regs = priv->regs; /* Assign a Physical address to the TBI */ - regs->tbipa = CFG_TBIPA_VALUE; - phyregs->tbipa = CFG_TBIPA_VALUE; + regs->tbipa = CONFIG_SYS_TBIPA_VALUE; + phyregs->tbipa = CONFIG_SYS_TBIPA_VALUE; asm("sync"); /* Reset MII (due to new addresses) */ @@ -1357,11 +1357,11 @@ struct phy_info phy_info_VSC8601 = { /* Override PHY config settings */ /* Configure some basic stuff */ {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, -#ifdef CFG_VSC8601_SKEWFIX +#ifdef CONFIG_SYS_VSC8601_SKEWFIX {MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL}, -#if defined(CFG_VSC8601_SKEW_TX) && defined(CFG_VSC8601_SKEW_RX) +#if defined(CONFIG_SYS_VSC8601_SKEW_TX) && defined(CONFIG_SYS_VSC8601_SKEW_RX) {MIIM_EXT_PAGE_ACCESS,1,NULL}, -#define VSC8101_SKEW (CFG_VSC8601_SKEW_TX<<14)|(CFG_VSC8601_SKEW_RX<<12) +#define VSC8101_SKEW (CONFIG_SYS_VSC8601_SKEW_TX<<14)|(CONFIG_SYS_VSC8601_SKEW_RX<<12) {MIIM_VSC8601_SKEW_CTRL,VSC8101_SKEW,NULL}, {MIIM_EXT_PAGE_ACCESS,0,NULL}, #endif diff --git a/drivers/net/tsi108_eth.c b/drivers/net/tsi108_eth.c index 50fa765..079354a 100644 --- a/drivers/net/tsi108_eth.c +++ b/drivers/net/tsi108_eth.c @@ -54,7 +54,7 @@ printf ("%s %d: " fmt, __FUNCTION__, __LINE__, ##args) #define RX_PRINT_ERRORS #define TX_PRINT_ERRORS -#define ETH_BASE (CFG_TSI108_CSR_BASE + 0x6000) +#define ETH_BASE (CONFIG_SYS_TSI108_CSR_BASE + 0x6000) #define ETH_PORT_OFFSET 0x400 diff --git a/drivers/net/vsc7385.c b/drivers/net/vsc7385.c index 4e7259f..ada42c4 100644 --- a/drivers/net/vsc7385.c +++ b/drivers/net/vsc7385.c @@ -35,13 +35,13 @@ int vsc7385_upload_firmware(void *firmware, unsigned int size) u8 *fw = firmware; unsigned int i; - u32 *gloreset = (u32 *) (CFG_VSC7385_BASE + 0x1c050); - u32 *icpu_ctrl = (u32 *) (CFG_VSC7385_BASE + 0x1c040); - u32 *icpu_addr = (u32 *) (CFG_VSC7385_BASE + 0x1c044); - u32 *icpu_data = (u32 *) (CFG_VSC7385_BASE + 0x1c048); - u32 *icpu_rom_map = (u32 *) (CFG_VSC7385_BASE + 0x1c070); + u32 *gloreset = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c050); + u32 *icpu_ctrl = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c040); + u32 *icpu_addr = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c044); + u32 *icpu_data = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c048); + u32 *icpu_rom_map = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c070); #ifdef DEBUG - u32 *chipid = (u32 *) (CFG_VSC7385_BASE + 0x1c060); + u32 *chipid = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c060); #endif out_be32(gloreset, 3); diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index b5eea89..41780db 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -157,7 +157,7 @@ pci_dev_t pci_find_devices(struct pci_device_id *ids, int index) for (hose = hose_head; hose; hose = hose->next) { -#ifdef CFG_SCSI_SCAN_BUS_REVERSE +#ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE for (bus = hose->last_busno; bus >= hose->first_busno; bus--) #else for (bus = hose->first_busno; bus <= hose->last_busno; bus++) diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index 2acf9bf..3844359 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -26,9 +26,9 @@ #define PCIAUTO_IDE_MODE_MASK 0x05 -/* the user can define CFG_PCI_CACHE_LINE_SIZE to avoid problems */ -#ifndef CFG_PCI_CACHE_LINE_SIZE -#define CFG_PCI_CACHE_LINE_SIZE 8 +/* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */ +#ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE +#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 #endif /* @@ -154,7 +154,7 @@ void pciauto_setup_device(struct pci_controller *hose, pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat); pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, - CFG_PCI_CACHE_LINE_SIZE); + CONFIG_SYS_PCI_CACHE_LINE_SIZE); pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); } diff --git a/drivers/pci/tsi108_pci.c b/drivers/pci/tsi108_pci.c index edd614f..d153fc6 100644 --- a/drivers/pci/tsi108_pci.c +++ b/drivers/pci/tsi108_pci.c @@ -47,32 +47,32 @@ void tsi108_clear_pci_error (void) * requests. */ /* Read PB Error Log Registers */ - err_stat = *(volatile u32 *)(CFG_TSI108_CSR_BASE + + err_stat = *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_ERRCS); - err_addr = *(volatile u32 *)(CFG_TSI108_CSR_BASE + + err_addr = *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_AERR); if (err_stat & PB_ERRCS_ES) { /* Clear PCI/X bus errors if applicable */ - if ((err_addr & 0xFF000000) == CFG_PCI_CFG_BASE) { + if ((err_addr & 0xFF000000) == CONFIG_SYS_PCI_CFG_BASE) { /* Clear error flag */ - *(u32 *) (CFG_TSI108_CSR_BASE + + *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_ERRCS) = PB_ERRCS_ES; /* Clear read error reported in PB_ISR */ - *(u32 *) (CFG_TSI108_CSR_BASE + + *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_ISR) = PB_ISR_PBS_RD_ERR; /* Clear errors reported by PCI CSR (Normally Master Abort) */ - pci_stat = *(volatile u32 *)(CFG_TSI108_CSR_BASE + + pci_stat = *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR); - *(volatile u32 *)(CFG_TSI108_CSR_BASE + + *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR) = pci_stat; - *(volatile u32 *)(CFG_TSI108_CSR_BASE + + *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_IRP_STAT) = PCI_IRP_STAT_P_CSR; } @@ -102,8 +102,8 @@ unsigned int __get_pci_config_dword (u32 addr) static int tsi108_read_config_dword (struct pci_controller *hose, pci_dev_t dev, int offset, u32 * value) { - dev &= (CFG_PCI_CFG_SIZE - 1); - dev |= (CFG_PCI_CFG_BASE | (offset & 0xfc)); + dev &= (CONFIG_SYS_PCI_CFG_SIZE - 1); + dev |= (CONFIG_SYS_PCI_CFG_BASE | (offset & 0xfc)); *value = __get_pci_config_dword(dev); if (0xFFFFFFFF == *value) tsi108_clear_pci_error (); @@ -113,8 +113,8 @@ static int tsi108_read_config_dword (struct pci_controller *hose, static int tsi108_write_config_dword (struct pci_controller *hose, pci_dev_t dev, int offset, u32 value) { - dev &= (CFG_PCI_CFG_SIZE - 1); - dev |= (CFG_PCI_CFG_BASE | (offset & 0xfc)); + dev &= (CONFIG_SYS_PCI_CFG_SIZE - 1); + dev |= (CONFIG_SYS_PCI_CFG_BASE | (offset & 0xfc)); out_le32 ((volatile unsigned *)dev, value); @@ -129,19 +129,19 @@ void pci_init_board (void) hose->last_busno = 0xff; pci_set_region (hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, PCI_REGION_MEM | PCI_REGION_MEMORY); + CONFIG_SYS_PCI_MEMORY_BUS, + CONFIG_SYS_PCI_MEMORY_PHYS, + CONFIG_SYS_PCI_MEMORY_SIZE, PCI_REGION_MEM | PCI_REGION_MEMORY); /* PCI memory space */ pci_set_region (hose->regions + 1, - CFG_PCI_MEM_BUS, - CFG_PCI_MEM_PHYS, CFG_PCI_MEM_SIZE, PCI_REGION_MEM); + CONFIG_SYS_PCI_MEM_BUS, + CONFIG_SYS_PCI_MEM_PHYS, CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM); /* PCI I/O space */ pci_set_region (hose->regions + 2, - CFG_PCI_IO_BUS, - CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO); + CONFIG_SYS_PCI_IO_BUS, + CONFIG_SYS_PCI_IO_PHYS, CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO); hose->region_count = 3; diff --git a/drivers/pci/w83c553f.c b/drivers/pci/w83c553f.c index d7355a4..8561422 100644 --- a/drivers/pci/w83c553f.c +++ b/drivers/pci/w83c553f.c @@ -42,7 +42,7 @@ out_be16((u16*) (addr),(val)); udelay(1); \ } while (0) -extern uint ide_bus_offset[CFG_IDE_MAXBUS]; +extern uint ide_bus_offset[CONFIG_SYS_IDE_MAXBUS]; void initialise_pic(void); void initialise_dma(void); @@ -105,7 +105,7 @@ void initialise_w83c553f(void) pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &ide_bus_offset[0]); ide_bus_offset[0] &= ~1; -#if CFG_IDE_MAXBUS > 1 +#if CONFIG_SYS_IDE_MAXBUS > 1 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2, &ide_bus_offset[1]); ide_bus_offset[1] &= ~1; #endif diff --git a/drivers/pcmcia/i82365.c b/drivers/pcmcia/i82365.c index 1e2431e..1bcb3a5 100644 --- a/drivers/pcmcia/i82365.c +++ b/drivers/pcmcia/i82365.c @@ -909,8 +909,8 @@ int i82365_init (void) mem.map = 0; mem.flags = MAP_ATTRIB | MAP_ACTIVE; mem.speed = 300; - mem.sys_start = CFG_PCMCIA_MEM_ADDR; - mem.sys_stop = CFG_PCMCIA_MEM_ADDR + CFG_PCMCIA_MEM_SIZE - 1; + mem.sys_start = CONFIG_SYS_PCMCIA_MEM_ADDR; + mem.sys_stop = CONFIG_SYS_PCMCIA_MEM_ADDR + CONFIG_SYS_PCMCIA_MEM_SIZE - 1; mem.card_start = 0; i365_set_mem_map (&socket, &mem); @@ -918,8 +918,8 @@ int i82365_init (void) mem.map = 1; mem.flags = MAP_ACTIVE; mem.speed = 300; - mem.sys_start = CFG_PCMCIA_MEM_ADDR + CFG_PCMCIA_MEM_SIZE; - mem.sys_stop = CFG_PCMCIA_MEM_ADDR + (2 * CFG_PCMCIA_MEM_SIZE) - 1; + mem.sys_start = CONFIG_SYS_PCMCIA_MEM_ADDR + CONFIG_SYS_PCMCIA_MEM_SIZE; + mem.sys_stop = CONFIG_SYS_PCMCIA_MEM_ADDR + (2 * CONFIG_SYS_PCMCIA_MEM_SIZE) - 1; mem.card_start = 0; i365_set_mem_map (&socket, &mem); @@ -988,8 +988,8 @@ static void i82365_dump_regions (pci_dev_t dev) { u_int tmp[2]; u_int *mem = (void *) socket.cb_phys; - u_char *cis = (void *) CFG_PCMCIA_MEM_ADDR; - u_char *ide = (void *) (CFG_ATA_BASE_ADDR + CFG_ATA_REG_OFFSET); + u_char *cis = (void *) CONFIG_SYS_PCMCIA_MEM_ADDR; + u_char *ide = (void *) (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_REG_OFFSET); pci_read_config_dword (dev, 0x00, tmp + 0); pci_read_config_dword (dev, 0x80, tmp + 1); diff --git a/drivers/pcmcia/marubun_pcmcia.c b/drivers/pcmcia/marubun_pcmcia.c index d075ba3..f715dec 100644 --- a/drivers/pcmcia/marubun_pcmcia.c +++ b/drivers/pcmcia/marubun_pcmcia.c @@ -38,20 +38,20 @@ #if defined(CONFIG_PCMCIA) /* MR-SHPC-01 register */ -#define MRSHPC_MODE (CFG_MARUBUN_MRSHPC + 4) -#define MRSHPC_OPTION (CFG_MARUBUN_MRSHPC + 6) -#define MRSHPC_CSR (CFG_MARUBUN_MRSHPC + 8) -#define MRSHPC_ISR (CFG_MARUBUN_MRSHPC + 10) -#define MRSHPC_ICR (CFG_MARUBUN_MRSHPC + 12) -#define MRSHPC_CPWCR (CFG_MARUBUN_MRSHPC + 14) -#define MRSHPC_MW0CR1 (CFG_MARUBUN_MRSHPC + 16) -#define MRSHPC_MW1CR1 (CFG_MARUBUN_MRSHPC + 18) -#define MRSHPC_IOWCR1 (CFG_MARUBUN_MRSHPC + 20) -#define MRSHPC_MW0CR2 (CFG_MARUBUN_MRSHPC + 22) -#define MRSHPC_MW1CR2 (CFG_MARUBUN_MRSHPC + 24) -#define MRSHPC_IOWCR2 (CFG_MARUBUN_MRSHPC + 26) -#define MRSHPC_CDCR (CFG_MARUBUN_MRSHPC + 28) -#define MRSHPC_PCIC_INFO (CFG_MARUBUN_MRSHPC + 30) +#define MRSHPC_MODE (CONFIG_SYS_MARUBUN_MRSHPC + 4) +#define MRSHPC_OPTION (CONFIG_SYS_MARUBUN_MRSHPC + 6) +#define MRSHPC_CSR (CONFIG_SYS_MARUBUN_MRSHPC + 8) +#define MRSHPC_ISR (CONFIG_SYS_MARUBUN_MRSHPC + 10) +#define MRSHPC_ICR (CONFIG_SYS_MARUBUN_MRSHPC + 12) +#define MRSHPC_CPWCR (CONFIG_SYS_MARUBUN_MRSHPC + 14) +#define MRSHPC_MW0CR1 (CONFIG_SYS_MARUBUN_MRSHPC + 16) +#define MRSHPC_MW1CR1 (CONFIG_SYS_MARUBUN_MRSHPC + 18) +#define MRSHPC_IOWCR1 (CONFIG_SYS_MARUBUN_MRSHPC + 20) +#define MRSHPC_MW0CR2 (CONFIG_SYS_MARUBUN_MRSHPC + 22) +#define MRSHPC_MW1CR2 (CONFIG_SYS_MARUBUN_MRSHPC + 24) +#define MRSHPC_IOWCR2 (CONFIG_SYS_MARUBUN_MRSHPC + 26) +#define MRSHPC_CDCR (CONFIG_SYS_MARUBUN_MRSHPC + 28) +#define MRSHPC_PCIC_INFO (CONFIG_SYS_MARUBUN_MRSHPC + 30) int pcmcia_on (void) { @@ -98,8 +98,8 @@ int pcmcia_on (void) outw(0x0000,MRSHPC_ISR); outw(0x2000,MRSHPC_ICR); - outb(0x00,(CFG_MARUBUN_MW2 + 0x206)); - outb(0x42,(CFG_MARUBUN_MW2 + 0x200)); + outb(0x00,(CONFIG_SYS_MARUBUN_MW2 + 0x206)); + outb(0x42,(CONFIG_SYS_MARUBUN_MW2 + 0x200)); return 0; } diff --git a/drivers/pcmcia/mpc8xx_pcmcia.c b/drivers/pcmcia/mpc8xx_pcmcia.c index 14477a4..95ea5e9 100644 --- a/drivers/pcmcia/mpc8xx_pcmcia.c +++ b/drivers/pcmcia/mpc8xx_pcmcia.c @@ -34,8 +34,8 @@ static u_int m8xx_get_speed(u_int ns, u_int is_io); /* look up table for pgcrx registers */ u_int *pcmcia_pgcrx[2] = { - &((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcra, - &((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb, + &((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcra, + &((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb, }; /* @@ -66,11 +66,11 @@ static const u_int m8xx_size_to_gray[M8XX_SIZES_NO] = #endif #if defined(CONFIG_LWMON) || defined(CONFIG_NSCU) -#define CFG_PCMCIA_TIMING ( PCMCIA_SHT(9) \ +#define CONFIG_SYS_PCMCIA_TIMING ( PCMCIA_SHT(9) \ | PCMCIA_SST(3) \ | PCMCIA_SL(12)) #else -#define CFG_PCMCIA_TIMING ( PCMCIA_SHT(2) \ +#define CONFIG_SYS_PCMCIA_TIMING ( PCMCIA_SHT(2) \ | PCMCIA_SST(4) \ | PCMCIA_SL(9)) #endif @@ -88,12 +88,12 @@ int pcmcia_on (void) debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n"); /* intialize the fixed memory windows */ - win = (pcmcia_win_t *)(&((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pbr0); - base = CFG_PCMCIA_MEM_ADDR; + win = (pcmcia_win_t *)(&((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pbr0); + base = CONFIG_SYS_PCMCIA_MEM_ADDR; - if((reg = m8xx_get_graycode(CFG_PCMCIA_MEM_SIZE)) == -1) { + if((reg = m8xx_get_graycode(CONFIG_SYS_PCMCIA_MEM_SIZE)) == -1) { printf ("Cannot set window size to 0x%08x\n", - CFG_PCMCIA_MEM_SIZE); + CONFIG_SYS_PCMCIA_MEM_SIZE); return (1); } @@ -125,7 +125,7 @@ int pcmcia_on (void) | PCMCIA_PRS_ATTR | slotbit | PCMCIA_PV - | CFG_PCMCIA_TIMING ); + | CONFIG_SYS_PCMCIA_TIMING ); break; } case 5: @@ -135,7 +135,7 @@ int pcmcia_on (void) | PCMCIA_PRS_IO | slotbit | PCMCIA_PV - | CFG_PCMCIA_TIMING ); + | CONFIG_SYS_PCMCIA_TIMING ); break; } case 6: @@ -145,7 +145,7 @@ int pcmcia_on (void) | PCMCIA_PRS_IO | slotbit | PCMCIA_PV - | CFG_PCMCIA_TIMING ); + | CONFIG_SYS_PCMCIA_TIMING ); break; } #endif /* CONFIG_IDE_8xx_PCCARD */ @@ -157,7 +157,7 @@ int pcmcia_on (void) | PCMCIA_PRS_IO | slotbit | PCMCIA_PV - | CFG_PCMCIA_TIMING ); + | CONFIG_SYS_PCMCIA_TIMING ); break; } #endif /* CONFIG_HMI10 */ @@ -168,7 +168,7 @@ int pcmcia_on (void) debug ("MemWin %d: PBR 0x%08lX POR %08lX\n", i, win->br, win->or); - base += CFG_PCMCIA_MEM_SIZE; + base += CONFIG_SYS_PCMCIA_MEM_SIZE; ++win; } @@ -198,14 +198,14 @@ int pcmcia_off (void) printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n"); /* clear interrupt state, and disable interrupts */ - ((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pscr = PCMCIA_MASK(_slot_); - ((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_per &= ~PCMCIA_MASK(_slot_); + ((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pscr = PCMCIA_MASK(_slot_); + ((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_per &= ~PCMCIA_MASK(_slot_); /* turn off interrupt and disable CxOE */ PCMCIA_PGCRX(_slot_) = __MY_PCMCIA_GCRX_CXOE; /* turn off memory windows */ - win = (pcmcia_win_t *)(&((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pbr0); + win = (pcmcia_win_t *)(&((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pbr0); for (i=0; iim_cpm.cp_pbdat |= 0x00000300; } static inline void power_on_5_0(int slot) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; immap->im_cpm.cp_pbdat &= ~(0x0000100); immap->im_cpm.cp_pbdir |= 0x00000300; } static inline void power_on_3_3(int slot) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; immap->im_cpm.cp_pbdat &= ~(0x0000200); immap->im_cpm.cp_pbdir |= 0x00000300; } @@ -97,7 +97,7 @@ static inline void power_on_3_3(int slot) static inline void power_config(int slot) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; /* * Configure Port C pins for * 5 Volts Enable and 3 Volts enable @@ -108,20 +108,20 @@ static inline void power_config(int slot) static inline void power_off(int slot) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; immap->im_ioport.iop_pcdat &= ~(0x0002 | 0x0004); } static inline void power_on_5_0(int slot) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; immap->im_ioport.iop_pcdat |= 0x0004; immap->im_ioport.iop_pcdir |= (0x0002 | 0x0004); } static inline void power_on_3_3(int slot) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; immap->im_ioport.iop_pcdat |= 0x0002; immap->im_ioport.iop_pcdir |= (0x0002 | 0x0004); } @@ -132,14 +132,14 @@ static inline void power_on_3_3(int slot) static inline int check_card_is_absent(int slot) { volatile pcmconf8xx_t *pcmp = - (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); return pcmp->pcmc_pipr & (0x10000000 >> (slot << 4)); } #else static inline int check_card_is_absent(int slot) { volatile pcmconf8xx_t *pcmp = - (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); return pcmp->pcmc_pipr & (0x18000000 >> (slot << 4)); } #endif @@ -153,9 +153,9 @@ static inline int check_card_is_absent(int slot) int pcmcia_hardware_enable(int slot) { volatile pcmconf8xx_t *pcmp = - (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); volatile sysconf8xx_t *sysp = - (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf)); + (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf)); uint reg, mask; debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); @@ -271,7 +271,7 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp) u_long reg; # ifdef DEBUG volatile pcmconf8xx_t *pcmp = - (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); # endif debug ("voltage_set: " PCMCIA_BOARD_MSG diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index 0d48360..ed7ed65 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -34,12 +34,12 @@ #ifdef CONFIG_UEC_ETH1 static uec_info_t eth1_uec_info = { .uf_info = { - .ucc_num = CFG_UEC1_UCC_NUM, - .rx_clock = CFG_UEC1_RX_CLK, - .tx_clock = CFG_UEC1_TX_CLK, - .eth_type = CFG_UEC1_ETH_TYPE, + .ucc_num = CONFIG_SYS_UEC1_UCC_NUM, + .rx_clock = CONFIG_SYS_UEC1_RX_CLK, + .tx_clock = CONFIG_SYS_UEC1_TX_CLK, + .eth_type = CONFIG_SYS_UEC1_ETH_TYPE, }, -#if (CFG_UEC1_ETH_TYPE == FAST_ETH) +#if (CONFIG_SYS_UEC1_ETH_TYPE == FAST_ETH) .num_threads_tx = UEC_NUM_OF_THREADS_1, .num_threads_rx = UEC_NUM_OF_THREADS_1, #else @@ -50,19 +50,19 @@ static uec_info_t eth1_uec_info = { .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, .tx_bd_ring_len = 16, .rx_bd_ring_len = 16, - .phy_address = CFG_UEC1_PHY_ADDR, - .enet_interface = CFG_UEC1_INTERFACE_MODE, + .phy_address = CONFIG_SYS_UEC1_PHY_ADDR, + .enet_interface = CONFIG_SYS_UEC1_INTERFACE_MODE, }; #endif #ifdef CONFIG_UEC_ETH2 static uec_info_t eth2_uec_info = { .uf_info = { - .ucc_num = CFG_UEC2_UCC_NUM, - .rx_clock = CFG_UEC2_RX_CLK, - .tx_clock = CFG_UEC2_TX_CLK, - .eth_type = CFG_UEC2_ETH_TYPE, + .ucc_num = CONFIG_SYS_UEC2_UCC_NUM, + .rx_clock = CONFIG_SYS_UEC2_RX_CLK, + .tx_clock = CONFIG_SYS_UEC2_TX_CLK, + .eth_type = CONFIG_SYS_UEC2_ETH_TYPE, }, -#if (CFG_UEC2_ETH_TYPE == FAST_ETH) +#if (CONFIG_SYS_UEC2_ETH_TYPE == FAST_ETH) .num_threads_tx = UEC_NUM_OF_THREADS_1, .num_threads_rx = UEC_NUM_OF_THREADS_1, #else @@ -73,19 +73,19 @@ static uec_info_t eth2_uec_info = { .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, .tx_bd_ring_len = 16, .rx_bd_ring_len = 16, - .phy_address = CFG_UEC2_PHY_ADDR, - .enet_interface = CFG_UEC2_INTERFACE_MODE, + .phy_address = CONFIG_SYS_UEC2_PHY_ADDR, + .enet_interface = CONFIG_SYS_UEC2_INTERFACE_MODE, }; #endif #ifdef CONFIG_UEC_ETH3 static uec_info_t eth3_uec_info = { .uf_info = { - .ucc_num = CFG_UEC3_UCC_NUM, - .rx_clock = CFG_UEC3_RX_CLK, - .tx_clock = CFG_UEC3_TX_CLK, - .eth_type = CFG_UEC3_ETH_TYPE, + .ucc_num = CONFIG_SYS_UEC3_UCC_NUM, + .rx_clock = CONFIG_SYS_UEC3_RX_CLK, + .tx_clock = CONFIG_SYS_UEC3_TX_CLK, + .eth_type = CONFIG_SYS_UEC3_ETH_TYPE, }, -#if (CFG_UEC3_ETH_TYPE == FAST_ETH) +#if (CONFIG_SYS_UEC3_ETH_TYPE == FAST_ETH) .num_threads_tx = UEC_NUM_OF_THREADS_1, .num_threads_rx = UEC_NUM_OF_THREADS_1, #else @@ -96,19 +96,19 @@ static uec_info_t eth3_uec_info = { .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, .tx_bd_ring_len = 16, .rx_bd_ring_len = 16, - .phy_address = CFG_UEC3_PHY_ADDR, - .enet_interface = CFG_UEC3_INTERFACE_MODE, + .phy_address = CONFIG_SYS_UEC3_PHY_ADDR, + .enet_interface = CONFIG_SYS_UEC3_INTERFACE_MODE, }; #endif #ifdef CONFIG_UEC_ETH4 static uec_info_t eth4_uec_info = { .uf_info = { - .ucc_num = CFG_UEC4_UCC_NUM, - .rx_clock = CFG_UEC4_RX_CLK, - .tx_clock = CFG_UEC4_TX_CLK, - .eth_type = CFG_UEC4_ETH_TYPE, + .ucc_num = CONFIG_SYS_UEC4_UCC_NUM, + .rx_clock = CONFIG_SYS_UEC4_RX_CLK, + .tx_clock = CONFIG_SYS_UEC4_TX_CLK, + .eth_type = CONFIG_SYS_UEC4_ETH_TYPE, }, -#if (CFG_UEC4_ETH_TYPE == FAST_ETH) +#if (CONFIG_SYS_UEC4_ETH_TYPE == FAST_ETH) .num_threads_tx = UEC_NUM_OF_THREADS_1, .num_threads_rx = UEC_NUM_OF_THREADS_1, #else @@ -119,19 +119,19 @@ static uec_info_t eth4_uec_info = { .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, .tx_bd_ring_len = 16, .rx_bd_ring_len = 16, - .phy_address = CFG_UEC4_PHY_ADDR, - .enet_interface = CFG_UEC4_INTERFACE_MODE, + .phy_address = CONFIG_SYS_UEC4_PHY_ADDR, + .enet_interface = CONFIG_SYS_UEC4_INTERFACE_MODE, }; #endif #ifdef CONFIG_UEC_ETH5 static uec_info_t eth5_uec_info = { .uf_info = { - .ucc_num = CFG_UEC5_UCC_NUM, - .rx_clock = CFG_UEC5_RX_CLK, - .tx_clock = CFG_UEC5_TX_CLK, - .eth_type = CFG_UEC5_ETH_TYPE, + .ucc_num = CONFIG_SYS_UEC5_UCC_NUM, + .rx_clock = CONFIG_SYS_UEC5_RX_CLK, + .tx_clock = CONFIG_SYS_UEC5_TX_CLK, + .eth_type = CONFIG_SYS_UEC5_ETH_TYPE, }, -#if (CFG_UEC5_ETH_TYPE == FAST_ETH) +#if (CONFIG_SYS_UEC5_ETH_TYPE == FAST_ETH) .num_threads_tx = UEC_NUM_OF_THREADS_1, .num_threads_rx = UEC_NUM_OF_THREADS_1, #else @@ -142,19 +142,19 @@ static uec_info_t eth5_uec_info = { .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, .tx_bd_ring_len = 16, .rx_bd_ring_len = 16, - .phy_address = CFG_UEC5_PHY_ADDR, - .enet_interface = CFG_UEC5_INTERFACE_MODE, + .phy_address = CONFIG_SYS_UEC5_PHY_ADDR, + .enet_interface = CONFIG_SYS_UEC5_INTERFACE_MODE, }; #endif #ifdef CONFIG_UEC_ETH6 static uec_info_t eth6_uec_info = { .uf_info = { - .ucc_num = CFG_UEC6_UCC_NUM, - .rx_clock = CFG_UEC6_RX_CLK, - .tx_clock = CFG_UEC6_TX_CLK, - .eth_type = CFG_UEC6_ETH_TYPE, + .ucc_num = CONFIG_SYS_UEC6_UCC_NUM, + .rx_clock = CONFIG_SYS_UEC6_RX_CLK, + .tx_clock = CONFIG_SYS_UEC6_TX_CLK, + .eth_type = CONFIG_SYS_UEC6_ETH_TYPE, }, -#if (CFG_UEC6_ETH_TYPE == FAST_ETH) +#if (CONFIG_SYS_UEC6_ETH_TYPE == FAST_ETH) .num_threads_tx = UEC_NUM_OF_THREADS_1, .num_threads_rx = UEC_NUM_OF_THREADS_1, #else @@ -165,8 +165,8 @@ static uec_info_t eth6_uec_info = { .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, .tx_bd_ring_len = 16, .rx_bd_ring_len = 16, - .phy_address = CFG_UEC6_PHY_ADDR, - .enet_interface = CFG_UEC6_INTERFACE_MODE, + .phy_address = CONFIG_SYS_UEC6_PHY_ADDR, + .enet_interface = CONFIG_SYS_UEC6_INTERFACE_MODE, }; #endif diff --git a/drivers/rtc/ds1306.c b/drivers/rtc/ds1306.c index 03c4089..75f88a9 100644 --- a/drivers/rtc/ds1306.c +++ b/drivers/rtc/ds1306.c @@ -86,7 +86,7 @@ static void init_spi (void); /* read clock time from DS1306 and return it in *tmp */ int rtc_get (struct rtc_time *tmp) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; unsigned char spi_byte; /* Data Byte */ init_spi (); /* set port B for software SPI */ @@ -143,7 +143,7 @@ int rtc_get (struct rtc_time *tmp) /* set clock time in DS1306 RTC and in MPC8xx RTC */ int rtc_set (struct rtc_time *tmp) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; init_spi (); /* set port B for software SPI */ @@ -218,7 +218,7 @@ int rtc_set (struct rtc_time *tmp) /* Initialize Port B for software SPI */ static void init_spi (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; /* Force output pins to begin at logic 0 */ immap->im_cpm.cp_pbdat &= ~(PB_SPI_CE | PB_SPIMOSI | PB_SPISCK); @@ -235,7 +235,7 @@ static void init_spi (void) /* NOTE: soft_spi_send() assumes that the I/O lines are configured already */ static void soft_spi_send (unsigned char n) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; unsigned char bitpos; /* bit position to receive */ unsigned char i; /* Loop Control */ @@ -264,7 +264,7 @@ static void soft_spi_send (unsigned char n) /* NOTE: soft_spi_read() assumes that the I/O lines are configured already */ static unsigned char soft_spi_read (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; unsigned char spi_byte = 0; /* Return value, assume success */ unsigned char bitpos; /* bit position to receive */ @@ -314,7 +314,7 @@ int rtc_get (struct rtc_time *tmp) * step just once. */ if (!slave) { - slave = spi_setup_slave(0, CFG_SPI_RTC_DEVID, 600000, + slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000, SPI_MODE_3 | SPI_CS_HIGH); if (!slave) return; @@ -377,7 +377,7 @@ int rtc_set (struct rtc_time *tmp) { /* Assuming Vcc = 2.0V (lowest speed) */ if (!slave) { - slave = spi_setup_slave(0, CFG_SPI_RTC_DEVID, 600000, + slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000, SPI_MODE_3 | SPI_CS_HIGH); if (!slave) return; @@ -408,7 +408,7 @@ void rtc_reset (void) { /* Assuming Vcc = 2.0V (lowest speed) */ if (!slave) { - slave = spi_setup_slave(0, CFG_SPI_RTC_DEVID, 600000, + slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000, SPI_MODE_3 | SPI_CS_HIGH); if (!slave) return; diff --git a/drivers/rtc/ds1307.c b/drivers/rtc/ds1307.c index afc4b78..0650d91 100644 --- a/drivers/rtc/ds1307.c +++ b/drivers/rtc/ds1307.c @@ -47,11 +47,11 @@ #endif /*---------------------------------------------------------------------*/ -#ifndef CFG_I2C_RTC_ADDR -# define CFG_I2C_RTC_ADDR 0x68 +#ifndef CONFIG_SYS_I2C_RTC_ADDR +# define CONFIG_SYS_I2C_RTC_ADDR 0x68 #endif -#if defined(CONFIG_RTC_DS1307) && (CFG_I2C_SPEED > 100000) +#if defined(CONFIG_RTC_DS1307) && (CONFIG_SYS_I2C_SPEED > 100000) # error The DS1307 is specified only up to 100kHz! #endif @@ -187,13 +187,13 @@ void rtc_reset (void) static uchar rtc_read (uchar reg) { - return (i2c_reg_read (CFG_I2C_RTC_ADDR, reg)); + return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); } static void rtc_write (uchar reg, uchar val) { - i2c_reg_write (CFG_I2C_RTC_ADDR, reg, val); + i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); } static unsigned bcd2bin (uchar n) diff --git a/drivers/rtc/ds1337.c b/drivers/rtc/ds1337.c index 509f81f..58e3966 100644 --- a/drivers/rtc/ds1337.c +++ b/drivers/rtc/ds1337.c @@ -160,10 +160,10 @@ int rtc_set (struct rtc_time *tmp) * SQW/INTB* pin and program it for 32,768 Hz output. Note that * according to the datasheet, turning on the square wave output * increases the current drain on the backup battery from about - * 600 nA to 2uA. Define CFG_RTC_DS1337_NOOSC if you wish to turn + * 600 nA to 2uA. Define CONFIG_SYS_RTC_DS1337_NOOSC if you wish to turn * off the OSC output. */ -#ifdef CFG_RTC_DS1337_NOOSC +#ifdef CONFIG_SYS_RTC_DS1337_NOOSC #define RTC_DS1337_RESET_VAL \ (RTC_CTL_BIT_INTCN | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2) #else @@ -182,13 +182,13 @@ void rtc_reset (void) static uchar rtc_read (uchar reg) { - return (i2c_reg_read (CFG_I2C_RTC_ADDR, reg)); + return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); } static void rtc_write (uchar reg, uchar val) { - i2c_reg_write (CFG_I2C_RTC_ADDR, reg, val); + i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); } static unsigned bcd2bin (uchar n) diff --git a/drivers/rtc/ds1374.c b/drivers/rtc/ds1374.c index 79a3d73..d61a228 100644 --- a/drivers/rtc/ds1374.c +++ b/drivers/rtc/ds1374.c @@ -48,11 +48,11 @@ #endif /*---------------------------------------------------------------------*/ -#ifndef CFG_I2C_RTC_ADDR -# define CFG_I2C_RTC_ADDR 0x68 +#ifndef CONFIG_SYS_I2C_RTC_ADDR +# define CONFIG_SYS_I2C_RTC_ADDR 0x68 #endif -#if defined(CONFIG_RTC_DS1374) && (CFG_I2C_SPEED > 400000) +#if defined(CONFIG_RTC_DS1374) && (CONFIG_SYS_I2C_SPEED > 400000) # error The DS1374 is specified up to 400kHz in fast mode! #endif @@ -239,22 +239,22 @@ void rtc_reset (void){ */ static uchar rtc_read (uchar reg) { - return (i2c_reg_read (CFG_I2C_RTC_ADDR, reg)); + return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); } static void rtc_write (uchar reg, uchar val, boolean_t set) { if (set == TRUE) { - val |= i2c_reg_read (CFG_I2C_RTC_ADDR, reg); - i2c_reg_write (CFG_I2C_RTC_ADDR, reg, val); + val |= i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg); + i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); } else { - val = i2c_reg_read (CFG_I2C_RTC_ADDR, reg) & ~val; - i2c_reg_write (CFG_I2C_RTC_ADDR, reg, val); + val = i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg) & ~val; + i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); } } static void rtc_write_raw (uchar reg, uchar val) { - i2c_reg_write (CFG_I2C_RTC_ADDR, reg, val); + i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); } #endif diff --git a/drivers/rtc/ds1556.c b/drivers/rtc/ds1556.c index 7574626..763d22a 100644 --- a/drivers/rtc/ds1556.c +++ b/drivers/rtc/ds1556.c @@ -43,7 +43,7 @@ static void rtc_write( unsigned int addr, uchar val); static uchar bin2bcd (unsigned int n); static unsigned bcd2bin(uchar c); -#define RTC_BASE ( CFG_NVRAM_SIZE + CFG_NVRAM_BASE_ADDR ) +#define RTC_BASE ( CONFIG_SYS_NVRAM_SIZE + CONFIG_SYS_NVRAM_BASE_ADDR ) #define RTC_YEAR ( RTC_BASE + 0xf ) #define RTC_MONTH ( RTC_BASE + 0xe ) diff --git a/drivers/rtc/ds164x.c b/drivers/rtc/ds164x.c index 00494b3..1e96679 100644 --- a/drivers/rtc/ds164x.c +++ b/drivers/rtc/ds164x.c @@ -49,7 +49,7 @@ static unsigned bcd2bin(uchar c); /* * DS164x registers layout */ -#define RTC_BASE ( CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE ) +#define RTC_BASE ( CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE ) #define RTC_YEAR ( RTC_BASE + 0x07 ) #define RTC_MONTH ( RTC_BASE + 0x06 ) diff --git a/drivers/rtc/ds174x.c b/drivers/rtc/ds174x.c index 43e6ab7..738d118 100644 --- a/drivers/rtc/ds174x.c +++ b/drivers/rtc/ds174x.c @@ -40,7 +40,7 @@ static void rtc_write( unsigned int addr, uchar val); static uchar bin2bcd (unsigned int n); static unsigned bcd2bin(uchar c); -#define RTC_BASE ( CFG_NVRAM_SIZE + CFG_NVRAM_BASE_ADDR ) +#define RTC_BASE ( CONFIG_SYS_NVRAM_SIZE + CONFIG_SYS_NVRAM_BASE_ADDR ) #define RTC_YEAR ( RTC_BASE + 7 ) #define RTC_MONTH ( RTC_BASE + 6 ) diff --git a/drivers/rtc/ds3231.c b/drivers/rtc/ds3231.c index da8a3e6..ef03358 100644 --- a/drivers/rtc/ds3231.c +++ b/drivers/rtc/ds3231.c @@ -177,13 +177,13 @@ void rtc_reset (void) static uchar rtc_read (uchar reg) { - return (i2c_reg_read (CFG_I2C_RTC_ADDR, reg)); + return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); } static void rtc_write (uchar reg, uchar val) { - i2c_reg_write (CFG_I2C_RTC_ADDR, reg, val); + i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); } static unsigned bcd2bin (uchar n) diff --git a/drivers/rtc/isl1208.c b/drivers/rtc/isl1208.c index 87f06cc..71f63d5 100644 --- a/drivers/rtc/isl1208.c +++ b/drivers/rtc/isl1208.c @@ -153,12 +153,12 @@ void rtc_reset (void) static uchar rtc_read (uchar reg) { - return (i2c_reg_read (CFG_I2C_RTC_ADDR, reg)); + return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); } static void rtc_write (uchar reg, uchar val) { - i2c_reg_write (CFG_I2C_RTC_ADDR, reg, val); + i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); } static unsigned bcd2bin (uchar n) diff --git a/drivers/rtc/m41t11.c b/drivers/rtc/m41t11.c index 0a9b12e..3a77c1b 100644 --- a/drivers/rtc/m41t11.c +++ b/drivers/rtc/m41t11.c @@ -35,15 +35,15 @@ is what should be done. #define CONFIG_RTC_M41T11 1 -#define CFG_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 #if 0 -#define CFG_M41T11_EXT_CENTURY_DATA +#define CONFIG_SYS_M41T11_EXT_CENTURY_DATA #else -#define CFG_M41T11_BASE_YEAR 2000 +#define CONFIG_SYS_M41T11_BASE_YEAR 2000 #endif */ -#if defined(CFG_I2C_RTC_ADDR) && defined(CONFIG_CMD_DATE) +#if defined(CONFIG_SYS_I2C_RTC_ADDR) && defined(CONFIG_CMD_DATE) static unsigned bcd2bin (uchar n) { @@ -75,7 +75,7 @@ static unsigned char bin2bcd (unsigned int n) #define RTC_CONTROL_ADDR 0x7 -#ifndef CFG_M41T11_EXT_CENTURY_DATA +#ifndef CONFIG_SYS_M41T11_EXT_CENTURY_DATA #define REG_CNT (RTC_REG_CNT+1) @@ -83,8 +83,8 @@ static unsigned char bin2bcd (unsigned int n) you only get 00-99 for the year we will asume you want from the year 2000 if you don't set the config */ -#ifndef CFG_M41T11_BASE_YEAR -#define CFG_M41T11_BASE_YEAR 2000 +#ifndef CONFIG_SYS_M41T11_BASE_YEAR +#define CONFIG_SYS_M41T11_BASE_YEAR 2000 #endif #else @@ -101,7 +101,7 @@ int rtc_get (struct rtc_time *tmp) int rel = 0; uchar data[RTC_REG_CNT]; - i2c_read(CFG_I2C_RTC_ADDR, RTC_SEC_ADDR, 1, data, RTC_REG_CNT); + i2c_read(CONFIG_SYS_I2C_RTC_ADDR, RTC_SEC_ADDR, 1, data, RTC_REG_CNT); if( data[RTC_SEC_ADDR] & 0x80 ){ printf( "m41t11 RTC Clock stopped!!!\n" ); @@ -112,14 +112,14 @@ int rtc_get (struct rtc_time *tmp) tmp->tm_hour = bcd2bin (data[RTC_HOUR_ADDR] & 0x3F); tmp->tm_mday = bcd2bin (data[RTC_DATE_ADDR] & 0x3F); tmp->tm_mon = bcd2bin (data[RTC_MONTH_ADDR]& 0x1F); -#ifndef CFG_M41T11_EXT_CENTURY_DATA - tmp->tm_year = CFG_M41T11_BASE_YEAR +#ifndef CONFIG_SYS_M41T11_EXT_CENTURY_DATA + tmp->tm_year = CONFIG_SYS_M41T11_BASE_YEAR + bcd2bin(data[RTC_YEARS_ADDR]) + ((data[RTC_HOUR_ADDR]&0x40) ? 100 : 0); #else { unsigned char cent; - i2c_read(CFG_I2C_RTC_ADDR, M41T11_YEAR_DATA, 1, ¢, M41T11_YEAR_SIZE); + i2c_read(CONFIG_SYS_I2C_RTC_ADDR, M41T11_YEAR_DATA, 1, ¢, M41T11_YEAR_SIZE); if( !(data[RTC_HOUR_ADDR] & 0x80) ){ printf( "m41t11 RTC: cann't keep track of years without CEB set\n" ); rel = -1; @@ -127,7 +127,7 @@ int rtc_get (struct rtc_time *tmp) if( (cent & 0x1) != ((data[RTC_HOUR_ADDR]&0x40)>>7) ){ /*century flip store off new year*/ cent += 1; - i2c_write(CFG_I2C_RTC_ADDR, M41T11_YEAR_DATA, 1, ¢, M41T11_YEAR_SIZE); + i2c_write(CONFIG_SYS_I2C_RTC_ADDR, M41T11_YEAR_DATA, 1, ¢, M41T11_YEAR_SIZE); } tmp->tm_year =((int)cent*100)+bcd2bin(data[RTC_YEARS_ADDR]); } @@ -161,21 +161,21 @@ int rtc_set (struct rtc_time *tmp) data[RTC_HOUR_ADDR] |= 0x80;/*we will always use CEB*/ data[RTC_YEARS_ADDR] = bin2bcd(tmp->tm_year%100);/*same thing either way*/ -#ifndef CFG_M41T11_EXT_CENTURY_DATA - if( ((tmp->tm_year - CFG_M41T11_BASE_YEAR) > 200) || - (tmp->tm_year < CFG_M41T11_BASE_YEAR) ){ +#ifndef CONFIG_SYS_M41T11_EXT_CENTURY_DATA + if( ((tmp->tm_year - CONFIG_SYS_M41T11_BASE_YEAR) > 200) || + (tmp->tm_year < CONFIG_SYS_M41T11_BASE_YEAR) ){ printf( "m41t11 RTC setting year out of range!!need recompile\n" ); } - data[RTC_HOUR_ADDR] |= (tmp->tm_year - CFG_M41T11_BASE_YEAR) > 100 ? 0x40 : 0; + data[RTC_HOUR_ADDR] |= (tmp->tm_year - CONFIG_SYS_M41T11_BASE_YEAR) > 100 ? 0x40 : 0; #else { unsigned char cent; cent = tmp->tm_year ? tmp->tm_year / 100 : 0; data[RTC_HOUR_ADDR] |= (cent & 0x1) ? 0x40 : 0; - i2c_write(CFG_I2C_RTC_ADDR, M41T11_YEAR_DATA, 1, ¢, M41T11_YEAR_SIZE); + i2c_write(CONFIG_SYS_I2C_RTC_ADDR, M41T11_YEAR_DATA, 1, ¢, M41T11_YEAR_SIZE); } #endif - i2c_write(CFG_I2C_RTC_ADDR, RTC_SEC_ADDR, 1, data, RTC_REG_CNT); + i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_SEC_ADDR, 1, data, RTC_REG_CNT); return 0; } @@ -184,13 +184,13 @@ void rtc_reset (void) { unsigned char val; /* clear all control & status registers */ - i2c_read(CFG_I2C_RTC_ADDR, RTC_SEC_ADDR, 1, &val, 1); + i2c_read(CONFIG_SYS_I2C_RTC_ADDR, RTC_SEC_ADDR, 1, &val, 1); val = val & 0x7F;/*make sure we are running*/ - i2c_write(CFG_I2C_RTC_ADDR, RTC_SEC_ADDR, 1, &val, RTC_REG_CNT); + i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_SEC_ADDR, 1, &val, RTC_REG_CNT); - i2c_read(CFG_I2C_RTC_ADDR, RTC_CONTROL_ADDR, 1, &val, 1); + i2c_read(CONFIG_SYS_I2C_RTC_ADDR, RTC_CONTROL_ADDR, 1, &val, 1); val = val & 0x3F;/*turn off freq test keep calibration*/ - i2c_write(CFG_I2C_RTC_ADDR, RTC_CONTROL_ADDR, 1, &val, 1); + i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_CONTROL_ADDR, 1, &val, 1); } int rtc_store(int addr, unsigned char* data, int size) @@ -198,12 +198,12 @@ int rtc_store(int addr, unsigned char* data, int size) /*don't let things wrap onto the time on a write*/ if( (addr+size) >= M41T11_STORAGE_SZ ) return 1; - return i2c_write( CFG_I2C_RTC_ADDR, REG_CNT+addr, 1, data, size ); + return i2c_write( CONFIG_SYS_I2C_RTC_ADDR, REG_CNT+addr, 1, data, size ); } int rtc_recall(int addr, unsigned char* data, int size) { - return i2c_read( CFG_I2C_RTC_ADDR, REG_CNT+addr, 1, data, size ); + return i2c_read( CONFIG_SYS_I2C_RTC_ADDR, REG_CNT+addr, 1, data, size ); } #endif diff --git a/drivers/rtc/m41t60.c b/drivers/rtc/m41t60.c index 71bfc32..e34a5f4 100644 --- a/drivers/rtc/m41t60.c +++ b/drivers/rtc/m41t60.c @@ -34,7 +34,7 @@ #include #include -#if defined(CFG_I2C_RTC_ADDR) && defined(CONFIG_CMD_DATE) +#if defined(CONFIG_SYS_I2C_RTC_ADDR) && defined(CONFIG_CMD_DATE) static unsigned bcd2bin(uchar n) { @@ -85,7 +85,7 @@ static void rtc_dump(char const *const label) { uchar data[8]; - if (i2c_read(CFG_I2C_RTC_ADDR, 0, 1, data, sizeof(data))) { + if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, data, sizeof(data))) { printf("I2C read failed in rtc_dump()\n"); return; } @@ -114,7 +114,7 @@ static uchar *rtc_validate(void) uchar min, date, month, years; rtc_dump("begin validate"); - if (i2c_read(CFG_I2C_RTC_ADDR, 0, 1, data, sizeof(data))) { + if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, data, sizeof(data))) { printf("I2C read failed in rtc_validate()\n"); return 0; } @@ -125,7 +125,7 @@ static uchar *rtc_validate(void) if (0x00 != (data[RTC_CTRL] & 0x80)) { printf("M41T60 RTC clock lost power.\n"); data[RTC_SEC] = 0x80; - if (i2c_write(CFG_I2C_RTC_ADDR, RTC_SEC, 1, data, 1)) { + if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_SEC, 1, data, 1)) { printf("I2C write failed in rtc_validate()\n"); return 0; } @@ -161,7 +161,7 @@ static uchar *rtc_validate(void) data[RTC_YEAR] = 0x00; data[RTC_CTRL] &= 0x7F; /* reset OUT bit */ - if (i2c_write(CFG_I2C_RTC_ADDR, 0, 1, data, sizeof(data))) { + if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, data, sizeof(data))) { printf("I2C write failed in rtc_validate()\n"); return 0; } @@ -212,7 +212,7 @@ int rtc_set(struct rtc_time *tmp) data[RTC_YEAR] = bin2bcd(tmp->tm_year % 100); data[RTC_MONTH] |= year2cb(tmp->tm_year) << 6; data[RTC_DAY] = bin2bcd(tmp->tm_wday + 1) & 0x07; - if (i2c_write(CFG_I2C_RTC_ADDR, 0, 1, data, RTC_REG_CNT)) { + if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, data, RTC_REG_CNT)) { printf("I2C write failed in rtc_set()\n"); return -1; } @@ -255,10 +255,10 @@ void rtc_reset(void) * Turn off frequency test. */ data[RTC_CTRL] &= 0xBF; - if (i2c_write(CFG_I2C_RTC_ADDR, RTC_CTRL, 1, data + RTC_CTRL, 1)) { + if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_CTRL, 1, data + RTC_CTRL, 1)) { printf("I2C write failed in rtc_reset()\n"); return; } rtc_dump("end reset"); } -#endif /* CONFIG_RTC_M41T60 && CFG_I2C_RTC_ADDR && CONFIG_CMD_DATE */ +#endif /* CONFIG_RTC_M41T60 && CONFIG_SYS_I2C_RTC_ADDR && CONFIG_CMD_DATE */ diff --git a/drivers/rtc/m41t62.c b/drivers/rtc/m41t62.c index 9b7c84a..cfe84f9 100644 --- a/drivers/rtc/m41t62.c +++ b/drivers/rtc/m41t62.c @@ -68,7 +68,7 @@ int rtc_get(struct rtc_time *tm) { u8 buf[M41T62_DATETIME_REG_SIZE]; - i2c_read(CFG_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE); + i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE); debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, " "mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n", @@ -104,7 +104,7 @@ int rtc_set(struct rtc_time *tm) tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, tm->tm_hour, tm->tm_min, tm->tm_sec); - i2c_read(CFG_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE); + i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE); /* Merge time-data and register flags into buf[0..7] */ buf[M41T62_REG_SSEC] = 0; @@ -123,7 +123,7 @@ int rtc_set(struct rtc_time *tm) /* assume 20YY not 19YY */ buf[M41T62_REG_YEAR] = BIN2BCD(tm->tm_year % 100); - if (i2c_write(CFG_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE)) { + if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE)) { printf("I2C write failed in %s()\n", __func__); return -1; } diff --git a/drivers/rtc/m48t35ax.c b/drivers/rtc/m48t35ax.c index e19b81b..1482edd 100644 --- a/drivers/rtc/m48t35ax.c +++ b/drivers/rtc/m48t35ax.c @@ -147,14 +147,14 @@ static uchar rtc_read (uchar reg) { uchar val; val = *(unsigned char *) - ((CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE - 8) + reg); + ((CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - 8) + reg); return val; } static void rtc_write (uchar reg, uchar val) { *(unsigned char *) - ((CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE - 8) + reg) = val; + ((CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - 8) + reg) = val; } static unsigned bcd2bin (uchar n) diff --git a/drivers/rtc/max6900.c b/drivers/rtc/max6900.c index 758d7b7..7c99c5e 100644 --- a/drivers/rtc/max6900.c +++ b/drivers/rtc/max6900.c @@ -34,20 +34,20 @@ #if defined(CONFIG_CMD_DATE) -#ifndef CFG_I2C_RTC_ADDR -#define CFG_I2C_RTC_ADDR 0x50 +#ifndef CONFIG_SYS_I2C_RTC_ADDR +#define CONFIG_SYS_I2C_RTC_ADDR 0x50 #endif /* ------------------------------------------------------------------------- */ static uchar rtc_read (uchar reg) { - return (i2c_reg_read (CFG_I2C_RTC_ADDR, reg)); + return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); } static void rtc_write (uchar reg, uchar val) { - i2c_reg_write (CFG_I2C_RTC_ADDR, reg, val); + i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); udelay(2500); } diff --git a/drivers/rtc/mc146818.c b/drivers/rtc/mc146818.c index 1225454..38484ce 100644 --- a/drivers/rtc/mc146818.c +++ b/drivers/rtc/mc146818.c @@ -38,7 +38,7 @@ static void rtc_write (uchar reg, uchar val); static uchar bin2bcd (unsigned int n); static unsigned bcd2bin(uchar c); -#define RTC_PORT_MC146818 CFG_ISA_IO_BASE_ADDRESS + 0x70 +#define RTC_PORT_MC146818 CONFIG_SYS_ISA_IO_BASE_ADDRESS + 0x70 #define RTC_SECONDS 0x00 #define RTC_SECONDS_ALARM 0x01 #define RTC_MINUTES 0x02 @@ -141,18 +141,18 @@ void rtc_reset (void) /* ------------------------------------------------------------------------- */ -#ifdef CFG_RTC_REG_BASE_ADDR +#ifdef CONFIG_SYS_RTC_REG_BASE_ADDR /* * use direct memory access */ static uchar rtc_read (uchar reg) { - return(in8(CFG_RTC_REG_BASE_ADDR+reg)); + return(in8(CONFIG_SYS_RTC_REG_BASE_ADDR+reg)); } static void rtc_write (uchar reg, uchar val) { - out8(CFG_RTC_REG_BASE_ADDR+reg, val); + out8(CONFIG_SYS_RTC_REG_BASE_ADDR+reg, val); } #else static uchar rtc_read (uchar reg) diff --git a/drivers/rtc/mcfrtc.c b/drivers/rtc/mcfrtc.c index c2af197..979c466 100644 --- a/drivers/rtc/mcfrtc.c +++ b/drivers/rtc/mcfrtc.c @@ -32,7 +32,7 @@ #undef RTC_DEBUG -#ifndef CFG_MCFRTC_BASE +#ifndef CONFIG_SYS_MCFRTC_BASE #error RTC_BASE is not defined! #endif @@ -41,7 +41,7 @@ int rtc_get(struct rtc_time *tmp) { - volatile rtc_t *rtc = (rtc_t *) (CFG_MCFRTC_BASE); + volatile rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE); int rtc_days, rtc_hrs, rtc_mins; int tim; @@ -70,7 +70,7 @@ int rtc_get(struct rtc_time *tmp) int rtc_set(struct rtc_time *tmp) { - volatile rtc_t *rtc = (rtc_t *) (CFG_MCFRTC_BASE); + volatile rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE); static int month_days[12] = { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 @@ -112,7 +112,7 @@ int rtc_set(struct rtc_time *tmp) void rtc_reset(void) { - volatile rtc_t *rtc = (rtc_t *) (CFG_MCFRTC_BASE); + volatile rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE); if ((rtc->cr & RTC_CR_EN) == 0) { printf("real-time-clock was stopped. Now starting...\n"); diff --git a/drivers/rtc/mpc5xxx.c b/drivers/rtc/mpc5xxx.c index 6231b9b..ec0b0ef 100644 --- a/drivers/rtc/mpc5xxx.c +++ b/drivers/rtc/mpc5xxx.c @@ -57,7 +57,7 @@ typedef struct rtc5200 { *****************************************************************************/ int rtc_get (struct rtc_time *tmp) { - RTC5200 *rtc = (RTC5200 *) (CFG_MBAR+0x800); + RTC5200 *rtc = (RTC5200 *) (CONFIG_SYS_MBAR+0x800); ulong time, date, time2; /* read twice to avoid getting a funny time when the second is just changing */ @@ -90,7 +90,7 @@ int rtc_get (struct rtc_time *tmp) *****************************************************************************/ int rtc_set (struct rtc_time *tmp) { - RTC5200 *rtc = (RTC5200 *) (CFG_MBAR+0x800); + RTC5200 *rtc = (RTC5200 *) (CONFIG_SYS_MBAR+0x800); ulong time, date, year; debug ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", diff --git a/drivers/rtc/mpc8xx.c b/drivers/rtc/mpc8xx.c index 2bbc5d3..1c24e59 100644 --- a/drivers/rtc/mpc8xx.c +++ b/drivers/rtc/mpc8xx.c @@ -37,7 +37,7 @@ int rtc_get (struct rtc_time *tmp) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; ulong tim; tim = immr->im_sit.sit_rtc; @@ -53,7 +53,7 @@ int rtc_get (struct rtc_time *tmp) int rtc_set (struct rtc_time *tmp) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; ulong tim; debug ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", diff --git a/drivers/rtc/pcf8563.c b/drivers/rtc/pcf8563.c index 2fe1e37..cd9fb65 100644 --- a/drivers/rtc/pcf8563.c +++ b/drivers/rtc/pcf8563.c @@ -129,12 +129,12 @@ void rtc_reset (void) static uchar rtc_read (uchar reg) { - return (i2c_reg_read (CFG_I2C_RTC_ADDR, reg)); + return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); } static void rtc_write (uchar reg, uchar val) { - i2c_reg_write (CFG_I2C_RTC_ADDR, reg, val); + i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); } static unsigned bcd2bin (uchar n) diff --git a/drivers/rtc/pl031.c b/drivers/rtc/pl031.c index 6c1e9bd..8b2b174 100644 --- a/drivers/rtc/pl031.c +++ b/drivers/rtc/pl031.c @@ -29,8 +29,8 @@ #if defined(CONFIG_CMD_DATE) -#ifndef CFG_RTC_PL031_BASE -#error CFG_RTC_PL031_BASE is not defined! +#ifndef CONFIG_SYS_RTC_PL031_BASE +#error CONFIG_SYS_RTC_PL031_BASE is not defined! #endif /* @@ -48,9 +48,9 @@ #define RTC_CR_START (1 << 0) #define RTC_WRITE_REG(addr, val) \ - (*(volatile unsigned int *)(CFG_RTC_PL031_BASE + (addr)) = (val)) + (*(volatile unsigned int *)(CONFIG_SYS_RTC_PL031_BASE + (addr)) = (val)) #define RTC_READ_REG(addr) \ - (*(volatile unsigned int *)(CFG_RTC_PL031_BASE + (addr))) + (*(volatile unsigned int *)(CONFIG_SYS_RTC_PL031_BASE + (addr))) static int pl031_initted = 0; diff --git a/drivers/rtc/rs5c372.c b/drivers/rtc/rs5c372.c index 82dd969..d6cd7c8 100644 --- a/drivers/rtc/rs5c372.c +++ b/drivers/rtc/rs5c372.c @@ -50,8 +50,8 @@ static unsigned int rtc_debug = DEBUG; #define rtc_debug 0 /* gcc will remove all the debug code for us */ #endif -#ifndef CFG_I2C_RTC_ADDR -#define CFG_I2C_RTC_ADDR 0x32 +#ifndef CONFIG_SYS_I2C_RTC_ADDR +#define CONFIG_SYS_I2C_RTC_ADDR 0x32 #endif #define RS5C372_RAM_SIZE 0x10 @@ -77,7 +77,7 @@ rs5c372_readram(unsigned char *buf, int len) { int ret; - ret = i2c_read(CFG_I2C_RTC_ADDR, 0, 0, buf, len); + ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, len); if (ret != 0) { printf("%s: failed to read\n", __FUNCTION__); return ret; @@ -117,7 +117,7 @@ rs5c372_enable(void) buf[14] = 0; /* reg. 13 */ buf[15] = 0; /* reg. 14 */ buf[16] = USE_24HOUR_MODE; /* reg. 15 */ - ret = i2c_write(CFG_I2C_RTC_ADDR, 0, 0, buf, RS5C372_RAM_SIZE+1); + ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, RS5C372_RAM_SIZE+1); if (ret != 0) { printf("%s: failed\n", __FUNCTION__); return; @@ -218,7 +218,7 @@ int rtc_set (struct rtc_time *tmp) memset(buf, 0, sizeof(buf)); /* only read register 15 */ - ret = i2c_read(CFG_I2C_RTC_ADDR, 0, 0, buf, 1); + ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 1); if (ret == 0) { /* need to save register 15 */ @@ -247,7 +247,7 @@ int rtc_set (struct rtc_time *tmp) printf("WARNING: year should be between 1970 and 2069!\n"); buf[7] = bin2bcd(tmp->tm_year % 100); - ret = i2c_write(CFG_I2C_RTC_ADDR, 0, 0, buf, 8); + ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 8); if (ret != 0) { printf("rs5c372_set_datetime(), i2c_master_send() returned %d\n",ret); return -1; diff --git a/drivers/rtc/rx8025.c b/drivers/rtc/rx8025.c index 9f4ce2f..da87394 100644 --- a/drivers/rtc/rx8025.c +++ b/drivers/rtc/rx8025.c @@ -42,8 +42,8 @@ #endif /*---------------------------------------------------------------------*/ -#ifndef CFG_I2C_RTC_ADDR -# define CFG_I2C_RTC_ADDR 0x32 +#ifndef CONFIG_SYS_I2C_RTC_ADDR +# define CONFIG_SYS_I2C_RTC_ADDR 0x32 #endif /* @@ -102,7 +102,7 @@ int rtc_get (struct rtc_time *tmp) uchar sec, min, hour, mday, wday, mon, year, ctl2; uchar buf[16]; - if (i2c_read(CFG_I2C_RTC_ADDR, 0, 0, buf, 16)) + if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 16)) printf("Error reading from RTC\n"); sec = rtc_read(RTC_SEC_REG_ADDR); @@ -189,7 +189,7 @@ void rtc_reset (void) uchar buf[16]; uchar ctl2; - if (i2c_read(CFG_I2C_RTC_ADDR, 0, 0, buf, 16)) + if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 16)) printf("Error reading from RTC\n"); ctl2 = rtc_read(RTC_CTL2_REG_ADDR); @@ -221,7 +221,7 @@ static void rtc_write (uchar reg, uchar val) uchar buf[2]; buf[0] = reg << 4; buf[1] = val; - if (i2c_write(CFG_I2C_RTC_ADDR, 0, 0, buf, 2) != 0) + if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 2) != 0) printf("Error writing to RTC\n"); } diff --git a/drivers/rtc/x1205.c b/drivers/rtc/x1205.c index 7a3b514..56115b0 100644 --- a/drivers/rtc/x1205.c +++ b/drivers/rtc/x1205.c @@ -96,7 +96,7 @@ static void rtc_write(int reg, u8 val) { - i2c_write(CFG_I2C_RTC_ADDR, reg, 2, &val, 1); + i2c_write(CONFIG_SYS_I2C_RTC_ADDR, reg, 2, &val, 1); } /* @@ -108,7 +108,7 @@ int rtc_get(struct rtc_time *tm) { u8 buf[8]; - i2c_read(CFG_I2C_RTC_ADDR, X1205_CCR_BASE, 2, buf, 8); + i2c_read(CONFIG_SYS_I2C_RTC_ADDR, X1205_CCR_BASE, 2, buf, 8); debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, " "mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n", diff --git a/drivers/serial/mcfuart.c b/drivers/serial/mcfuart.c index a1fcd05..e04fc29 100644 --- a/drivers/serial/mcfuart.c +++ b/drivers/serial/mcfuart.c @@ -41,7 +41,7 @@ int serial_init(void) volatile uart_t *uart; u32 counter; - uart = (volatile uart_t *)(CFG_UART_BASE); + uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE); uart_port_conf(); @@ -76,7 +76,7 @@ int serial_init(void) void serial_putc(const char c) { - volatile uart_t *uart = (volatile uart_t *)(CFG_UART_BASE); + volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE); if (c == '\n') serial_putc('\r'); @@ -96,7 +96,7 @@ void serial_puts(const char *s) int serial_getc(void) { - volatile uart_t *uart = (volatile uart_t *)(CFG_UART_BASE); + volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE); /* Wait for a character to arrive. */ while (!(uart->usr & UART_USR_RXRDY)) ; @@ -105,14 +105,14 @@ int serial_getc(void) int serial_tstc(void) { - volatile uart_t *uart = (volatile uart_t *)(CFG_UART_BASE); + volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE); return (uart->usr & UART_USR_RXRDY); } void serial_setbrg(void) { - volatile uart_t *uart = (volatile uart_t *)(CFG_UART_BASE); + volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE); u32 counter; counter = ((gd->bus_clk / gd->baudrate)) >> 5; diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 6b3f60e..93c2243 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -1,12 +1,12 @@ /* * COM1 NS16550 support * originally from linux source (arch/ppc/boot/ns16550.c) - * modified to use CFG_ISA_MEM and new defines + * modified to use CONFIG_SYS_ISA_MEM and new defines */ #include -#ifdef CFG_NS16550 +#ifdef CONFIG_SYS_NS16550 #include diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index b361eef..bce7548 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -23,7 +23,7 @@ #include -#ifdef CFG_NS16550_SERIAL +#ifdef CONFIG_SYS_NS16550_SERIAL #include #ifdef CONFIG_NS87308 @@ -48,13 +48,13 @@ DECLARE_GLOBAL_DATA_PTR; #error "Invalid console index value." #endif -#if CONFIG_CONS_INDEX == 1 && !defined(CFG_NS16550_COM1) +#if CONFIG_CONS_INDEX == 1 && !defined(CONFIG_SYS_NS16550_COM1) #error "Console port 1 defined but not configured." -#elif CONFIG_CONS_INDEX == 2 && !defined(CFG_NS16550_COM2) +#elif CONFIG_CONS_INDEX == 2 && !defined(CONFIG_SYS_NS16550_COM2) #error "Console port 2 defined but not configured." -#elif CONFIG_CONS_INDEX == 3 && !defined(CFG_NS16550_COM3) +#elif CONFIG_CONS_INDEX == 3 && !defined(CONFIG_SYS_NS16550_COM3) #error "Console port 3 defined but not configured." -#elif CONFIG_CONS_INDEX == 4 && !defined(CFG_NS16550_COM4) +#elif CONFIG_CONS_INDEX == 4 && !defined(CONFIG_SYS_NS16550_COM4) #error "Console port 4 defined but not configured." #endif @@ -62,23 +62,23 @@ DECLARE_GLOBAL_DATA_PTR; * the array is 0 based. */ static NS16550_t serial_ports[4] = { -#ifdef CFG_NS16550_COM1 - (NS16550_t)CFG_NS16550_COM1, +#ifdef CONFIG_SYS_NS16550_COM1 + (NS16550_t)CONFIG_SYS_NS16550_COM1, #else NULL, #endif -#ifdef CFG_NS16550_COM2 - (NS16550_t)CFG_NS16550_COM2, +#ifdef CONFIG_SYS_NS16550_COM2 + (NS16550_t)CONFIG_SYS_NS16550_COM2, #else NULL, #endif -#ifdef CFG_NS16550_COM3 - (NS16550_t)CFG_NS16550_COM3, +#ifdef CONFIG_SYS_NS16550_COM3 + (NS16550_t)CONFIG_SYS_NS16550_COM3, #else NULL, #endif -#ifdef CFG_NS16550_COM4 - (NS16550_t)CFG_NS16550_COM4 +#ifdef CONFIG_SYS_NS16550_COM4 + (NS16550_t)CONFIG_SYS_NS16550_COM4 #else NULL #endif @@ -126,7 +126,7 @@ static int calc_divisor (NS16550_t port) { #ifdef CONFIG_OMAP1510 /* If can't cleanly clock 115200 set div to 1 */ - if ((CFG_NS16550_CLK == 12000000) && (gd->baudrate == 115200)) { + if ((CONFIG_SYS_NS16550_CLK == 12000000) && (gd->baudrate == 115200)) { port->osc_12m_sel = OSC_12M_SEL; /* enable 6.5 * divisor */ return (1); /* return 1 for base divisor */ } @@ -134,7 +134,7 @@ static int calc_divisor (NS16550_t port) #endif #ifdef CONFIG_OMAP1610 /* If can't cleanly clock 115200 set div to 1 */ - if ((CFG_NS16550_CLK == 48000000) && (gd->baudrate == 115200)) { + if ((CONFIG_SYS_NS16550_CLK == 48000000) && (gd->baudrate == 115200)) { return (26); /* return 26 for base divisor */ } #endif @@ -146,11 +146,11 @@ static int calc_divisor (NS16550_t port) #endif /* Compute divisor value. Normally, we should simply return: - * CFG_NS16550_CLK) / MODE_X_DIV / gd->baudrate + * CONFIG_SYS_NS16550_CLK) / MODE_X_DIV / gd->baudrate * but we need to round that value by adding 0.5. * Rounding is especially important at high baud rates. */ - return (CFG_NS16550_CLK + (gd->baudrate * (MODE_X_DIV / 2))) / + return (CONFIG_SYS_NS16550_CLK + (gd->baudrate * (MODE_X_DIV / 2))) / (MODE_X_DIV * gd->baudrate); } @@ -163,19 +163,19 @@ int serial_init (void) initialise_ns87308(); #endif -#ifdef CFG_NS16550_COM1 +#ifdef CONFIG_SYS_NS16550_COM1 clock_divisor = calc_divisor(serial_ports[0]); NS16550_init(serial_ports[0], clock_divisor); #endif -#ifdef CFG_NS16550_COM2 +#ifdef CONFIG_SYS_NS16550_COM2 clock_divisor = calc_divisor(serial_ports[1]); NS16550_init(serial_ports[1], clock_divisor); #endif -#ifdef CFG_NS16550_COM3 +#ifdef CONFIG_SYS_NS16550_COM3 clock_divisor = calc_divisor(serial_ports[2]); NS16550_init(serial_ports[2], clock_divisor); #endif -#ifdef CFG_NS16550_COM4 +#ifdef CONFIG_SYS_NS16550_COM4 clock_divisor = calc_divisor(serial_ports[3]); NS16550_init(serial_ports[3], clock_divisor); #endif diff --git a/drivers/spi/mpc8xxx_spi.c b/drivers/spi/mpc8xxx_spi.c index 9eaf986..c4b36f0 100644 --- a/drivers/spi/mpc8xxx_spi.c +++ b/drivers/spi/mpc8xxx_spi.c @@ -67,7 +67,7 @@ void spi_free_slave(struct spi_slave *slave) void spi_init(void) { - volatile spi8xxx_t *spi = &((immap_t *) (CFG_IMMR))->spi; + volatile spi8xxx_t *spi = &((immap_t *) (CONFIG_SYS_IMMR))->spi; /* * SPI pins on the MPC83xx are not muxed, so all we do is initialize @@ -94,7 +94,7 @@ void spi_release_bus(struct spi_slave *slave) int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { - volatile spi8xxx_t *spi = &((immap_t *) (CFG_IMMR))->spi; + volatile spi8xxx_t *spi = &((immap_t *) (CONFIG_SYS_IMMR))->spi; unsigned int tmpdout, tmpdin, event; int numBlks = bitlen / 32 + (bitlen % 32 ? 1 : 0); int tm, isRead = 0; diff --git a/drivers/spi/soft_spi.c b/drivers/spi/soft_spi.c index 25b589a..13df8cb 100644 --- a/drivers/spi/soft_spi.c +++ b/drivers/spi/soft_spi.c @@ -59,7 +59,7 @@ static inline struct soft_spi_slave *to_soft_spi(struct spi_slave *slave) void spi_init (void) { #ifdef SPI_INIT - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; SPI_INIT; #endif @@ -95,8 +95,8 @@ void spi_free_slave(struct spi_slave *slave) int spi_claim_bus(struct spi_slave *slave) { -#ifdef CFG_IMMR - volatile immap_t *immr = (immap_t *)CFG_IMMR; +#ifdef CONFIG_SYS_IMMR + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; #endif struct soft_spi_slave *ss = to_soft_spi(slave); @@ -132,8 +132,8 @@ void spi_release_bus(struct spi_slave *slave) int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { -#ifdef CFG_IMMR - volatile immap_t *immr = (immap_t *)CFG_IMMR; +#ifdef CONFIG_SYS_IMMR + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; #endif struct soft_spi_slave *ss = to_soft_spi(slave); uchar tmpdin = 0; diff --git a/drivers/usb/sl811_usb.c b/drivers/usb/sl811_usb.c index 159cc25..48f1ee9 100644 --- a/drivers/usb/sl811_usb.c +++ b/drivers/usb/sl811_usb.c @@ -111,7 +111,7 @@ static void inline sl811_write_buf(__u8 offset, __u8 *buf, __u8 size) int usb_init_kup4x (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; int i; unsigned char tmp; @@ -265,7 +265,7 @@ static int sl811_send_packet(struct usb_device *dev, unsigned long pipe, __u8 *b sl811_write(SL811_CTRL_A, ctrl); while (!(sl811_read(SL811_INTRSTS) & SL811_INTR_DONE_A)) { - if (5*CFG_HZ < get_timer(time_start)) { + if (5*CONFIG_SYS_HZ < get_timer(time_start)) { printf("USB transmit timed out\n"); return -USB_ST_CRC_ERR; } diff --git a/drivers/usb/usb_ohci.c b/drivers/usb/usb_ohci.c index da11ecb..c1aac33 100644 --- a/drivers/usb/usb_ohci.c +++ b/drivers/usb/usb_ohci.c @@ -73,7 +73,7 @@ defined(CONFIG_440EP) || \ defined(CONFIG_PCI_OHCI) || \ defined(CONFIG_MPC5200) || \ - defined(CFG_OHCI_USE_NPS) + defined(CONFIG_SYS_OHCI_USE_NPS) # define OHCI_USE_NPS /* force NoPowerSwitching mode */ #endif @@ -89,13 +89,13 @@ /* * e.g. PCI controllers need this */ -#ifdef CFG_OHCI_SWAP_REG_ACCESS +#ifdef CONFIG_SYS_OHCI_SWAP_REG_ACCESS # define readl(a) __swap_32(*((volatile u32 *)(a))) # define writel(a, b) (*((volatile u32 *)(b)) = __swap_32((volatile u32)a)) #else # define readl(a) (*((volatile u32 *)(a))) # define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a)) -#endif /* CFG_OHCI_SWAP_REG_ACCESS */ +#endif /* CONFIG_SYS_OHCI_SWAP_REG_ACCESS */ #define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) @@ -129,13 +129,13 @@ static struct pci_device_id ehci_pci_ids[] = { #define info(format, arg...) do {} while(0) #endif -#ifdef CFG_OHCI_BE_CONTROLLER +#ifdef CONFIG_SYS_OHCI_BE_CONTROLLER # define m16_swap(x) cpu_to_be16(x) # define m32_swap(x) cpu_to_be32(x) #else # define m16_swap(x) cpu_to_le16(x) # define m32_swap(x) cpu_to_le32(x) -#endif /* CFG_OHCI_BE_CONTROLLER */ +#endif /* CONFIG_SYS_OHCI_BE_CONTROLLER */ /* global ohci_t */ static ohci_t gohci; @@ -1819,13 +1819,13 @@ int usb_lowlevel_init(void) pci_dev_t pdev; #endif -#ifdef CFG_USB_OHCI_CPU_INIT +#ifdef CONFIG_SYS_USB_OHCI_CPU_INIT /* cpu dependant init */ if(usb_cpu_init()) return -1; #endif -#ifdef CFG_USB_OHCI_BOARD_INIT +#ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT /* board dependant init */ if(usb_board_init()) return -1; @@ -1873,21 +1873,21 @@ int usb_lowlevel_init(void) } else return -1; #else - gohci.regs = (struct ohci_regs *)CFG_USB_OHCI_REGS_BASE; + gohci.regs = (struct ohci_regs *)CONFIG_SYS_USB_OHCI_REGS_BASE; #endif gohci.flags = 0; - gohci.slot_name = CFG_USB_OHCI_SLOT_NAME; + gohci.slot_name = CONFIG_SYS_USB_OHCI_SLOT_NAME; if (hc_reset (&gohci) < 0) { hc_release_ohci (&gohci); err ("can't reset usb-%s", gohci.slot_name); -#ifdef CFG_USB_OHCI_BOARD_INIT +#ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT /* board dependant cleanup */ usb_board_init_fail(); #endif -#ifdef CFG_USB_OHCI_CPU_INIT +#ifdef CONFIG_SYS_USB_OHCI_CPU_INIT /* cpu dependant cleanup */ usb_cpu_init_fail(); #endif @@ -1901,12 +1901,12 @@ int usb_lowlevel_init(void) err ("can't start usb-%s", gohci.slot_name); hc_release_ohci (&gohci); /* Initialization failed */ -#ifdef CFG_USB_OHCI_BOARD_INIT +#ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT /* board dependant cleanup */ usb_board_stop(); #endif -#ifdef CFG_USB_OHCI_CPU_INIT +#ifdef CONFIG_SYS_USB_OHCI_CPU_INIT /* cpu dependant cleanup */ usb_cpu_stop(); #endif @@ -1932,13 +1932,13 @@ int usb_lowlevel_stop(void) /* call hc_release_ohci() here ? */ hc_reset (&gohci); -#ifdef CFG_USB_OHCI_BOARD_INIT +#ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT /* board dependant cleanup */ if(usb_board_stop()) return -1; #endif -#ifdef CFG_USB_OHCI_CPU_INIT +#ifdef CONFIG_SYS_USB_OHCI_CPU_INIT /* cpu dependant cleanup */ if(usb_cpu_stop()) return -1; diff --git a/drivers/usb/usb_ohci.h b/drivers/usb/usb_ohci.h index 7a04bf5..c1af547 100644 --- a/drivers/usb/usb_ohci.h +++ b/drivers/usb/usb_ohci.h @@ -155,8 +155,8 @@ struct ohci_hcca { /* * Maximum number of root hub ports. */ -#ifndef CFG_USB_OHCI_MAX_ROOT_PORTS -# error "CFG_USB_OHCI_MAX_ROOT_PORTS undefined!" +#ifndef CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS +# error "CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS undefined!" #endif /* @@ -191,7 +191,7 @@ struct ohci_regs { __u32 a; __u32 b; __u32 status; - __u32 portstatus[CFG_USB_OHCI_MAX_ROOT_PORTS]; + __u32 portstatus[CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS]; } roothub; } __attribute((aligned(32))); diff --git a/drivers/usb/usbdcore_mpc8xx.c b/drivers/usb/usbdcore_mpc8xx.c index 122793c..fa02003 100644 --- a/drivers/usb/usbdcore_mpc8xx.c +++ b/drivers/usb/usbdcore_mpc8xx.c @@ -133,7 +133,7 @@ static void mpc8xx_udc_advance_rx (volatile cbd_t ** rx_cbdp, int epid); int udc_init (void) { /* Init various pointers */ - immr = (immap_t *) CFG_IMMR; + immr = (immap_t *) CONFIG_SYS_IMMR; cp = (cpm8xx_t *) & (immr->im_cpm); usb_paramp = (usb_pram_t *) & (cp->cp_dparam[PROFF_USB]); usbp = (usb_t *) & (cp->cp_scc[0]); @@ -752,7 +752,7 @@ static short mpc8xx_udc_handle_txerr () static void mpc8xx_udc_advance_rx (volatile cbd_t ** rx_cbdp, int epid) { if ((*rx_cbdp)->cbd_sc & RX_BD_W) { - *rx_cbdp = (volatile cbd_t *) (endpoints[epid]->rbase + CFG_IMMR); + *rx_cbdp = (volatile cbd_t *) (endpoints[epid]->rbase + CONFIG_SYS_IMMR); } else { (*rx_cbdp)++; @@ -780,7 +780,7 @@ static void mpc8xx_udc_flush_tx_fifo (int epid) usbp->uscom = 0x40 | 0; /* reset ring */ - tx_cbdp = (cbd_t *) (endpoints[epid]->tbptr + CFG_IMMR); + tx_cbdp = (cbd_t *) (endpoints[epid]->tbptr + CONFIG_SYS_IMMR); tx_cbdp->cbd_sc = (TX_BD_I | TX_BD_W); @@ -886,7 +886,7 @@ static int mpc8xx_udc_ep_tx (struct usb_endpoint_instance *epi) } ep = epi->endpoint_address & 0x03; - tx_cbdp = (cbd_t *) (endpoints[ep]->tbptr + CFG_IMMR); + tx_cbdp = (cbd_t *) (endpoints[ep]->tbptr + CONFIG_SYS_IMMR); if (tx_cbdp->cbd_sc & TX_BD_R || usbp->usber & USB_E_TXB) { mpc8xx_udc_flush_tx_fifo (ep); @@ -903,7 +903,7 @@ static int mpc8xx_udc_ep_tx (struct usb_endpoint_instance *epi) return -1; } - tx_cbdp = (cbd_t *) (endpoints[ep]->tbptr + CFG_IMMR); + tx_cbdp = (cbd_t *) (endpoints[ep]->tbptr + CONFIG_SYS_IMMR); while (tx_cbdp->cbd_sc & TX_BD_R) { }; tx_cbdp->cbd_sc = (tx_cbdp->cbd_sc & TX_BD_W); @@ -1187,10 +1187,10 @@ static void mpc8xx_udc_clock_init (volatile immap_t * immr, volatile cpm8xx_t * cp) { -#if defined(CFG_USB_EXTC_CLK) +#if defined(CONFIG_SYS_USB_EXTC_CLK) /* This has been tested with a 48MHz crystal on CLK6 */ - switch (CFG_USB_EXTC_CLK) { + switch (CONFIG_SYS_USB_EXTC_CLK) { case 1: immr->im_ioport.iop_papar |= 0x0100; immr->im_ioport.iop_padir &= ~0x0100; @@ -1216,7 +1216,7 @@ static void mpc8xx_udc_clock_init (volatile immap_t * immr, break; } -#elif defined(CFG_USB_BRGCLK) +#elif defined(CONFIG_SYS_USB_BRGCLK) /* This has been tested with brgclk == 50MHz */ int divisor = 0; @@ -1233,7 +1233,7 @@ static void mpc8xx_udc_clock_init (volatile immap_t * immr, divisor = (gd->cpu_clk / 48000000L) - 1; cp->cp_sicr &= ~0x0000003F; - switch (CFG_USB_BRGCLK) { + switch (CONFIG_SYS_USB_BRGCLK) { case 1: cp->cp_brgc1 |= (divisor | CPM_BRG_EN); cp->cp_sicr &= ~0x2F; @@ -1256,7 +1256,7 @@ static void mpc8xx_udc_clock_init (volatile immap_t * immr, } #else -#error "CFG_USB_EXTC_CLK or CFG_USB_BRGCLK must be defined" +#error "CONFIG_SYS_USB_EXTC_CLK or CONFIG_SYS_USB_BRGCLK must be defined" #endif } diff --git a/drivers/video/ati_radeon_fb.c b/drivers/video/ati_radeon_fb.c index 650380b..9ebb0b0 100644 --- a/drivers/video/ati_radeon_fb.c +++ b/drivers/video/ati_radeon_fb.c @@ -653,7 +653,7 @@ void *video_hw_init(void) tmp = 0; - videomode = CFG_DEFAULT_VIDEO_MODE; + videomode = CONFIG_SYS_DEFAULT_VIDEO_MODE; /* get video mode via environment */ if ((penv = getenv ("videomode")) != NULL) { /* deceide if it is a string */ @@ -672,7 +672,7 @@ void *video_hw_init(void) break; } if (i == VESA_MODES_COUNT) { - printf ("no VESA Mode found, switching to mode 0x%x ", CFG_DEFAULT_VIDEO_MODE); + printf ("no VESA Mode found, switching to mode 0x%x ", CONFIG_SYS_DEFAULT_VIDEO_MODE); i = 0; } res_mode = (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].resindex]; @@ -732,7 +732,7 @@ void *video_hw_init(void) break; } - pGD->isaBase = CFG_ISA_IO_BASE_ADDRESS; + pGD->isaBase = CONFIG_SYS_ISA_IO_BASE_ADDRESS; pGD->pciBase = rinfo->fb_base_phys; pGD->frameAdrs = rinfo->fb_base_phys; pGD->memSize = 64 * 1024 * 1024; diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index fe418f1..779aa4b 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -61,7 +61,7 @@ CONFIG_CONSOLE_CURSOR - on/off drawing cursor is done with delay loop in VIDEO_TSTC_FCT (i8042) - CFG_CONSOLE_BLINK_COUNT - value for delay loop - blink rate + CONFIG_SYS_CONSOLE_BLINK_COUNT - value for delay loop - blink rate CONFIG_CONSOLE_TIME - display time/date in upper right corner, needs CONFIG_CMD_DATE and CONFIG_CONSOLE_CURSOR CONFIG_VIDEO_LOGO - display Linux Logo in upper left corner @@ -824,19 +824,19 @@ int video_display_bitmap (ulong bmp_image, int x, int y) /* * Could be a gzipped bmp image, try to decrompress... */ - len = CFG_VIDEO_LOGO_MAX_SIZE; - dst = malloc(CFG_VIDEO_LOGO_MAX_SIZE); + len = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE; + dst = malloc(CONFIG_SYS_VIDEO_LOGO_MAX_SIZE); if (dst == NULL) { printf("Error: malloc in gunzip failed!\n"); return(1); } - if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE, (uchar *)bmp_image, &len) != 0) { + if (gunzip(dst, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE, (uchar *)bmp_image, &len) != 0) { printf ("Error: no valid bmp or bmp.gz image at %lx\n", bmp_image); free(dst); return 1; } - if (len == CFG_VIDEO_LOGO_MAX_SIZE) { - printf("Image could be truncated (increase CFG_VIDEO_LOGO_MAX_SIZE)!\n"); + if (len == CONFIG_SYS_VIDEO_LOGO_MAX_SIZE) { + printf("Image could be truncated (increase CONFIG_SYS_VIDEO_LOGO_MAX_SIZE)!\n"); } /* diff --git a/drivers/video/ct69000.c b/drivers/video/ct69000.c index cae662e..ae219cc 100644 --- a/drivers/video/ct69000.c +++ b/drivers/video/ct69000.c @@ -1107,7 +1107,7 @@ video_hw_init (void) pGD->gdfIndex = GDF_24BIT_888RGB; break; } - pGD->isaBase = CFG_ISA_IO_BASE_ADDRESS; + pGD->isaBase = CONFIG_SYS_ISA_IO_BASE_ADDRESS; pGD->pciBase = pci_mem_base; pGD->frameAdrs = pci_mem_base; pGD->memSize = chips_param->max_mem; diff --git a/drivers/video/mb862xx.c b/drivers/video/mb862xx.c index d47cb03..22a85d1 100644 --- a/drivers/video/mb862xx.c +++ b/drivers/video/mb862xx.c @@ -358,7 +358,7 @@ void *video_hw_init (void) #endif #if (defined(CONFIG_LWMON5) || \ - defined(CONFIG_SOCRATES)) && !(CONFIG_POST & CFG_POST_SYSMON) + defined(CONFIG_SOCRATES)) && !(CONFIG_POST & CONFIG_SYS_POST_SYSMON) /* Lamp on */ board_backlight_switch (1); #endif diff --git a/drivers/video/smiLynxEM.c b/drivers/video/smiLynxEM.c index 390dd56..59b43ef 100644 --- a/drivers/video/smiLynxEM.c +++ b/drivers/video/smiLynxEM.c @@ -596,7 +596,7 @@ void *video_hw_init (void) tmp = 0; - videomode = CFG_DEFAULT_VIDEO_MODE; + videomode = CONFIG_SYS_DEFAULT_VIDEO_MODE; /* get video mode via environment */ if ((penv = getenv ("videomode")) != NULL) { /* deceide if it is a string */ @@ -615,7 +615,7 @@ void *video_hw_init (void) break; } if (i == VESA_MODES_COUNT) { - printf ("no VESA Mode found, switching to mode 0x%x ", CFG_DEFAULT_VIDEO_MODE); + printf ("no VESA Mode found, switching to mode 0x%x ", CONFIG_SYS_DEFAULT_VIDEO_MODE); i = 0; } res_mode = @@ -669,7 +669,7 @@ void *video_hw_init (void) break; } - pGD->isaBase = CFG_ISA_IO; + pGD->isaBase = CONFIG_SYS_ISA_IO; pGD->pciBase = pci_mem_base; pGD->dprBase = (pci_mem_base + 0x400000 + 0x8000); pGD->vprBase = (pci_mem_base + 0x400000 + 0xc000); diff --git a/drivers/video/videomodes.c b/drivers/video/videomodes.c index c81e5bc..d27ce1d 100644 --- a/drivers/video/videomodes.c +++ b/drivers/video/videomodes.c @@ -23,7 +23,7 @@ /************************************************************************ Get Parameters for the video mode: - The default video mode can be defined in CFG_DEFAULT_VIDEO_MODE. + The default video mode can be defined in CONFIG_SYS_DEFAULT_VIDEO_MODE. If undefined, default video mode is set to 0x301 Parameters can be set via the variable "videomode" in the environment. 2 diferent ways are possible: diff --git a/drivers/video/videomodes.h b/drivers/video/videomodes.h index e2dffe7..0d7c335 100644 --- a/drivers/video/videomodes.h +++ b/drivers/video/videomodes.h @@ -22,8 +22,8 @@ */ -#ifndef CFG_DEFAULT_VIDEO_MODE -#define CFG_DEFAULT_VIDEO_MODE 0x301 +#ifndef CONFIG_SYS_DEFAULT_VIDEO_MODE +#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x301 #endif /* Some mode definitions */ -- cgit v1.1 From a21ca95f8b9dca22714952b348e4905ac157b5cd Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Fri, 17 Oct 2008 13:52:51 +0200 Subject: mgsuvd: fix compiler warning when using soft_i2c driver Signed-off-by: Heiko Schocher --- drivers/i2c/soft_i2c.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers') diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index 508d3d7..ebe60e2 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -28,6 +28,7 @@ #include #ifdef CONFIG_MPC8260 /* only valid for MPC8260 */ #include +#include #endif #ifdef CONFIG_AT91RM9200 /* need this for the at91rm9200 */ #include @@ -39,6 +40,9 @@ #ifdef CONFIG_LPC2292 #include #endif +#ifdef CONFIG_MPC866 /* only valid for MPC866 */ +#include +#endif #include /* #define DEBUG_I2C */ -- cgit v1.1 From e1f7d22b8b52fc08c4d17a6a7db1e664281aed63 Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Thu, 9 Oct 2008 01:25:55 -0500 Subject: fsl_law clear enable before changing. Debug sessions may have left enabled laws. Changing lawbar with an unkown enabled tgtid could cause problems. Signed-off-by: Ed Swarthout --- drivers/misc/fsl_law.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c index 64df1c9..44c9e91 100644 --- a/drivers/misc/fsl_law.c +++ b/drivers/misc/fsl_law.c @@ -52,6 +52,7 @@ void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id) gd->used_laws |= (1 << idx); + out_be32(lawar, 0); out_be32(lawbar, addr >> 12); out_be32(lawar, LAWAR_EN | ((u32)id << 20) | (u32)sz); -- cgit v1.1