From b6ccd2c9dee758a70e761403a41e60c31a1cfcec Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Fri, 4 Feb 2011 09:00:43 +0530 Subject: fsl_pci: Add support for FSL PCIe controllers v2.x FSL PCIe controller v2.1: - New MSI inbound window - Same Inbound windows address as PCIe controller v1.x Added new pit_t member(pmit) to struct ccsr_pci for MSI inbound window FSL PCIe controller v2.2 and v2.3: - Different addresses for PCIe inbound window 3,2,1 - Exposed PCIe inbound window 0 - New PCIe interrupt status register Added new Interrupt Status register to struct ccsr_pci & updated pit_t array size to reflect the 4 inbound windows. To maintain backward compatiblilty, on V2.2 or greater controllers we start with inbound window 1 and leave inbound 0 with its default value (which maps to CCSRBAR). Signed-off-by: Prabhakar Kushwaha Signed-off-by: Kumar Gala --- drivers/pci/fsl_pci_init.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index dc34bd6..ab461b4 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2010 Freescale Semiconductor, Inc. + * Copyright 2007-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the Free @@ -223,6 +223,7 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) u32 cfg_data = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_data; u16 temp16; u32 temp32; + u32 block_rev; int enabled, r, inbound = 0; u16 ltssm; u8 temp8, pcie_cap; @@ -232,13 +233,20 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) /* Initialize ATMU registers based on hose regions and flags */ volatile pot_t *po = &pci->pot[1]; /* skip 0 */ - volatile pit_t *pi = &pci->pit[2]; /* ranges from: 3 to 1 */ + volatile pit_t *pi; u64 out_hi = 0, out_lo = -1ULL; u32 pcicsrbar, pcicsrbar_sz; pci_setup_indirect(hose, cfg_addr, cfg_data); + block_rev = in_be32(&pci->block_rev1); + if (PEX_IP_BLK_REV_2_2 <= block_rev) { + pi = &pci->pit[2]; /* 0xDC0 */ + } else { + pi = &pci->pit[3]; /* 0xDE0 */ + } + /* Handle setup of outbound windows first */ for (r = 0; r < hose->region_count; r++) { unsigned long flags = hose->regions[r].flags; -- cgit v1.1 From 7639675131673e8f1582d760203a9af34fba9e79 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 3 Feb 2011 09:02:13 -0600 Subject: powerpc/8xxx: Fix LAW init to respect pre-initialized entries If some pre-boot or earlier stage bootloader (NAND SPL) has setup LAW entries consider them good and mark them used. In the NAND SPL case we skip re-initializing based on the law_table since the SPL phase already did that. Signed-off-by: Kumar Gala --- drivers/misc/fsl_law.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'drivers') diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c index 031c974..3233ff2 100644 --- a/drivers/misc/fsl_law.c +++ b/drivers/misc/fsl_law.c @@ -24,6 +24,7 @@ */ #include +#include #include #include @@ -246,6 +247,25 @@ void init_laws(void) #error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes #endif + /* + * Any LAWs that were set up before we booted assume they are meant to + * be around and mark them used. + */ + for (i = 0; i < FSL_HW_NUM_LAWS; i++) { + u32 lawar = in_be32(LAWAR_ADDR(i)); + + if (lawar & LAW_EN) + gd->used_laws |= (1 << i); + } + +#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) + /* + * in NAND boot we've already parsed the law_table and setup those LAWs + * so don't do it again. + */ + return; +#endif + for (i = 0; i < num_law_entries; i++) { if (law_table[i].index == -1) set_next_law(law_table[i].addr, law_table[i].size, -- cgit v1.1 From 298f8af17b5056fd4135708c1745572f351bd339 Mon Sep 17 00:00:00 2001 From: Zhao Chenhui Date: Sun, 13 Mar 2011 10:00:40 -0500 Subject: echi: add ULI1575 PCI ID Add ULI1575 EHCI controller to the list of the supported devices. Signed-off-by: Zhao Chenhui Acked-by: Remy Bohmer Signed-off-by: Kumar Gala --- drivers/usb/host/ehci-pci.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c index cff3438..bf490b0 100644 --- a/drivers/usb/host/ehci-pci.c +++ b/drivers/usb/host/ehci-pci.c @@ -29,6 +29,7 @@ static struct pci_device_id ehci_pci_ids[] = { /* Please add supported PCI EHCI controller ids here */ {0x1033, 0x00E0}, + {0x10b9, 0x5239}, /* ULI1575 PCI EHCI module ids */ {0, 0} }; #endif -- cgit v1.1 From 19d68d202786efe7400dc2a6412c2d06b2ab38ec Mon Sep 17 00:00:00 2001 From: Li Yang Date: Thu, 27 Jan 2011 19:02:50 +0800 Subject: tsec: add AR8021 PHY support Signed-off-by: Li Yang --- drivers/net/tsec.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'drivers') diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 9c8fe62..9a91b9e 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -1810,6 +1810,28 @@ static struct phy_info phy_info_rtl8211b = { }, }; +struct phy_info phy_info_AR8021 = { + 0x4dd04, + "AR8021", + 4, + (struct phy_cmd[]) { /* config */ + {MII_BMCR, BMCR_RESET, NULL}, + {MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART, NULL}, + {0x1d, 0x05, NULL}, + {0x1e, 0x3D47, NULL}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + {MII_BMSR, miim_read, NULL}, + {MII_BMSR, miim_read, &mii_parse_sr}, + {MII_BMSR, miim_read, &mii_parse_link}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + } +}; + static struct phy_info *phy_info[] = { &phy_info_cis8204, &phy_info_cis8201, @@ -1832,6 +1854,7 @@ static struct phy_info *phy_info[] = { &phy_info_VSC8221, &phy_info_dp83865, &phy_info_rtl8211b, + &phy_info_AR8021, &phy_info_generic, /* must be last; has ID 0 and 32 bit mask */ NULL }; -- cgit v1.1