From 2ec4d10b65d1f7d45098606e9a6857d587c3027c Mon Sep 17 00:00:00 2001 From: Andrea Merello Date: Thu, 26 May 2016 18:24:28 +0200 Subject: phy: atheros: add support for RGMII_ID, RGMII_TXID and RGMII_RXID This adds support for internal delay on RX and TX on RGMII interface for the AR8035 phy. This is basically the same Linux driver do. Tested on a Zynq Zturn board (for which u-boot support in is my tree; first patch waiting ML approval) Signed-off-by: Andrea Merello Reviewed-by: Marek Vasut Acked-by: Marek Vasut Acked-by: Joe Hershberger --- drivers/net/phy/atheros.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'drivers') diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index e57c412..694a338 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -31,6 +31,22 @@ static int ar8035_config(struct phy_device *phydev) regval = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, (regval|0x0100)); + if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || + (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) { + /* select debug reg 5 */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x5); + /* enable tx delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x0100); + } + + if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || + (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)) { + /* select debug reg 0 */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x0); + /* enable rx delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x8000); + } + phydev->supported = phydev->drv->features; genphy_config_aneg(phydev); -- cgit v1.1 From ce412b79e72557702185443501478646a938b5fe Mon Sep 17 00:00:00 2001 From: Mugunthan V N Date: Thu, 13 Oct 2016 19:33:36 +0530 Subject: drivers: net: phy: atheros: add separate config for AR8031 In the current driver implementation, config() callback is common for AR8035 and AR8031 phy. In config() callback, driver tries to configure MMD Access Control Register and MMD Access Address Data Register unconditionally for both phy versions which leads to auto negotiation failure in AM335x EVMsk second port which uses AR8031 Giga bit RGMII phy. Fixing this by adding separate config for AR8031 phy. Reviewed-by: Sekhar Nori Signed-off-by: Mugunthan V N Acked-by: Joe Hershberger --- drivers/net/phy/atheros.c | 37 ++++++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index 694a338..b34cdd3 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -8,6 +8,15 @@ */ #include +#define AR803x_PHY_DEBUG_ADDR_REG 0x1d +#define AR803x_PHY_DEBUG_DATA_REG 0x1e + +#define AR803x_DEBUG_REG_5 0x5 +#define AR803x_RGMII_TX_CLK_DLY 0x100 + +#define AR803x_DEBUG_REG_0 0x0 +#define AR803x_RGMII_RX_CLK_DLY 0x8000 + static int ar8021_config(struct phy_device *phydev) { phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); @@ -17,6 +26,32 @@ static int ar8021_config(struct phy_device *phydev) return 0; } +static int ar8031_config(struct phy_device *phydev) +{ + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { + phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, + AR803x_DEBUG_REG_5); + phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, + AR803x_RGMII_TX_CLK_DLY); + } + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { + phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, + AR803x_DEBUG_REG_0); + phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, + AR803x_RGMII_RX_CLK_DLY); + } + + phydev->supported = phydev->drv->features; + + genphy_config_aneg(phydev); + genphy_restart_aneg(phydev); + + return 0; +} + static int ar8035_config(struct phy_device *phydev) { int regval; @@ -70,7 +105,7 @@ static struct phy_driver AR8031_driver = { .uid = 0x4dd074, .mask = 0xffffffef, .features = PHY_GBIT_FEATURES, - .config = ar8035_config, + .config = ar8031_config, .startup = genphy_startup, .shutdown = genphy_shutdown, }; -- cgit v1.1 From ab9715303d0b32e9a71dfa9c43d6629f54e2f236 Mon Sep 17 00:00:00 2001 From: Mugunthan V N Date: Thu, 13 Oct 2016 19:33:38 +0530 Subject: driver: net: cpsw: add support for RGMII id mode support and RMII clock source selection cpsw driver supports only selection of phy mode in control module but control module has more setting like RGMII ID mode selection, RMII clock source selection. So ported to cpsw-phy-sel driver from kernel to u-boot. Signed-off-by: Mugunthan V N Signed-off-by: Lokesh Vutla Acked-by: Joe Hershberger --- drivers/net/cpsw.c | 157 ++++++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 143 insertions(+), 14 deletions(-) (limited to 'drivers') diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index d17505e..d1f024e 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -225,6 +225,18 @@ struct cpdma_chan { void *hdp, *cp, *rxfree; }; +/* AM33xx SoC specific definitions for the CONTROL port */ +#define AM33XX_GMII_SEL_MODE_MII 0 +#define AM33XX_GMII_SEL_MODE_RMII 1 +#define AM33XX_GMII_SEL_MODE_RGMII 2 + +#define AM33XX_GMII_SEL_RGMII1_IDMODE BIT(4) +#define AM33XX_GMII_SEL_RGMII2_IDMODE BIT(5) +#define AM33XX_GMII_SEL_RMII1_IO_CLK_EN BIT(6) +#define AM33XX_GMII_SEL_RMII2_IO_CLK_EN BIT(7) + +#define GMII_SEL_MODE_MASK 0x3 + #define desc_write(desc, fld, val) __raw_writel((u32)(val), &(desc)->fld) #define desc_read(desc, fld) __raw_readl(&(desc)->fld) #define desc_read_ptr(desc, fld) ((void *)__raw_readl(&(desc)->fld)) @@ -1150,12 +1162,129 @@ static inline fdt_addr_t cpsw_get_addr_by_node(const void *fdt, int node) false); } +static void cpsw_gmii_sel_am3352(struct cpsw_priv *priv, + phy_interface_t phy_mode) +{ + u32 reg; + u32 mask; + u32 mode = 0; + bool rgmii_id = false; + int slave = priv->data.active_slave; + + reg = readl(priv->data.gmii_sel); + + switch (phy_mode) { + case PHY_INTERFACE_MODE_RMII: + mode = AM33XX_GMII_SEL_MODE_RMII; + break; + + case PHY_INTERFACE_MODE_RGMII: + mode = AM33XX_GMII_SEL_MODE_RGMII; + break; + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + mode = AM33XX_GMII_SEL_MODE_RGMII; + rgmii_id = true; + break; + + case PHY_INTERFACE_MODE_MII: + default: + mode = AM33XX_GMII_SEL_MODE_MII; + break; + }; + + mask = GMII_SEL_MODE_MASK << (slave * 2) | BIT(slave + 6); + mode <<= slave * 2; + + if (priv->data.rmii_clock_external) { + if (slave == 0) + mode |= AM33XX_GMII_SEL_RMII1_IO_CLK_EN; + else + mode |= AM33XX_GMII_SEL_RMII2_IO_CLK_EN; + } + + if (rgmii_id) { + if (slave == 0) + mode |= AM33XX_GMII_SEL_RGMII1_IDMODE; + else + mode |= AM33XX_GMII_SEL_RGMII2_IDMODE; + } + + reg &= ~mask; + reg |= mode; + + writel(reg, priv->data.gmii_sel); +} + +static void cpsw_gmii_sel_dra7xx(struct cpsw_priv *priv, + phy_interface_t phy_mode) +{ + u32 reg; + u32 mask; + u32 mode = 0; + int slave = priv->data.active_slave; + + reg = readl(priv->data.gmii_sel); + + switch (phy_mode) { + case PHY_INTERFACE_MODE_RMII: + mode = AM33XX_GMII_SEL_MODE_RMII; + break; + + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + mode = AM33XX_GMII_SEL_MODE_RGMII; + break; + + case PHY_INTERFACE_MODE_MII: + default: + mode = AM33XX_GMII_SEL_MODE_MII; + break; + }; + + switch (slave) { + case 0: + mask = GMII_SEL_MODE_MASK; + break; + case 1: + mask = GMII_SEL_MODE_MASK << 4; + mode <<= 4; + break; + default: + dev_err(priv->dev, "invalid slave number...\n"); + return; + } + + if (priv->data.rmii_clock_external) + dev_err(priv->dev, "RMII External clock is not supported\n"); + + reg &= ~mask; + reg |= mode; + + writel(reg, priv->data.gmii_sel); +} + +static void cpsw_phy_sel(struct cpsw_priv *priv, const char *compat, + phy_interface_t phy_mode) +{ + if (!strcmp(compat, "ti,am3352-cpsw-phy-sel")) + cpsw_gmii_sel_am3352(priv, phy_mode); + if (!strcmp(compat, "ti,am43xx-cpsw-phy-sel")) + cpsw_gmii_sel_am3352(priv, phy_mode); + else if (!strcmp(compat, "ti,dra7xx-cpsw-phy-sel")) + cpsw_gmii_sel_dra7xx(priv, phy_mode); +} + static int cpsw_eth_ofdata_to_platdata(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); struct cpsw_priv *priv = dev_get_priv(dev); struct gpio_desc *mode_gpios; const char *phy_mode; + const char *phy_sel_compat = NULL; const void *fdt = gd->fdt_blob; int node = dev->of_offset; int subnode; @@ -1271,6 +1400,17 @@ static int cpsw_eth_ofdata_to_platdata(struct udevice *dev) error("Not able to get gmii_sel reg address\n"); return -ENOENT; } + + if (fdt_get_property(fdt, subnode, "rmii-clock-ext", + NULL)) + priv->data.rmii_clock_external = true; + + phy_sel_compat = fdt_getprop(fdt, subnode, "compatible", + NULL); + if (!phy_sel_compat) { + error("Not able to get gmii_sel compatible\n"); + return -ENOENT; + } } } @@ -1293,20 +1433,9 @@ static int cpsw_eth_ofdata_to_platdata(struct udevice *dev) debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); return -EINVAL; } - switch (pdata->phy_interface) { - case PHY_INTERFACE_MODE_MII: - writel(MII_MODE_ENABLE, priv->data.gmii_sel); - break; - case PHY_INTERFACE_MODE_RMII: - writel(RMII_MODE_ENABLE, priv->data.gmii_sel); - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_ID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_TXID: - writel(RGMII_MODE_ENABLE, priv->data.gmii_sel); - break; - } + + /* Select phy interface in control module */ + cpsw_phy_sel(priv, phy_sel_compat, pdata->phy_interface); return 0; } -- cgit v1.1 From 65d4d00abc9166c0f837e9ca08b2d4453241e68c Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Fri, 26 Aug 2016 17:30:25 +1200 Subject: net: Add support for mv88e609x switches The Marvell Link Street mv88e60xx is a series of FastEthernet switch chips, some of which also support Gigabit ports. It is similar to the mv88e61xx series which support Gigabit on all ports. The main difference is the number of ports. Which affects the PORT_COUNT define and the size of the mask passed to mv88e61xx_port_set_vlan(). Other than that it's just a matter of adding the appropriate chip IDs. Signed-off-by: Chris Packham Cc: Joshua Scott Acked-by: Joe Hershberger --- drivers/net/phy/mv88e61xx.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index 74d5609..7385848 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -40,7 +40,7 @@ #define PHY_AUTONEGOTIATE_TIMEOUT 5000 -#define PORT_COUNT 7 +#define PORT_COUNT 11 #define PORT_MASK ((1 << PORT_COUNT) - 1) /* Device addresses */ @@ -167,6 +167,8 @@ #endif /* ID register values for different switch models */ +#define PORT_SWITCH_ID_6096 0x0980 +#define PORT_SWITCH_ID_6097 0x0990 #define PORT_SWITCH_ID_6172 0x1720 #define PORT_SWITCH_ID_6176 0x1760 #define PORT_SWITCH_ID_6240 0x2400 @@ -580,7 +582,7 @@ static int mv88e61xx_port_enable(struct phy_device *phydev, u8 port) } static int mv88e61xx_port_set_vlan(struct phy_device *phydev, u8 port, - u8 mask) + u16 mask) { int val; @@ -974,9 +976,21 @@ static struct phy_driver mv88e61xx_driver = { .shutdown = &genphy_shutdown, }; +static struct phy_driver mv88e609x_driver = { + .name = "Marvell MV88E609x", + .uid = 0x1410c89, + .mask = 0xfffffff0, + .features = PHY_GBIT_FEATURES, + .probe = mv88e61xx_probe, + .config = mv88e61xx_phy_config, + .startup = mv88e61xx_phy_startup, + .shutdown = &genphy_shutdown, +}; + int phy_mv88e61xx_init(void) { phy_register(&mv88e61xx_driver); + phy_register(&mv88e609x_driver); return 0; } -- cgit v1.1 From b755abecd45d6c5e1589ec4b17b6189a9dcbdac0 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Fri, 26 Aug 2016 17:30:26 +1200 Subject: net: mv88e61xx: Add support for fixed links On some boards these switches are wired directly into a SERDES interface on another Ethernet MAC. Add the ability to specify these kinds of boards using CONFIG_MV88E61XX_FIXED_PORTS which defines a bit mask of these fixed ports. Signed-off-by: Chris Packham Acked-by: Joe Hershberger --- drivers/net/phy/mv88e61xx.c | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) (limited to 'drivers') diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index 7385848..a2fd168 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -103,8 +103,16 @@ #define PORT_REG_STATUS_CMODE_1000BASE_X 0x9 #define PORT_REG_STATUS_CMODE_SGMII 0xa +#define PORT_REG_PHYS_CTRL_PCS_AN_EN BIT(10) +#define PORT_REG_PHYS_CTRL_PCS_AN_RST BIT(9) +#define PORT_REG_PHYS_CTRL_FC_VALUE BIT(7) +#define PORT_REG_PHYS_CTRL_FC_FORCE BIT(6) #define PORT_REG_PHYS_CTRL_LINK_VALUE BIT(5) #define PORT_REG_PHYS_CTRL_LINK_FORCE BIT(4) +#define PORT_REG_PHYS_CTRL_DUPLEX_VALUE BIT(3) +#define PORT_REG_PHYS_CTRL_DUPLEX_FORCE BIT(2) +#define PORT_REG_PHYS_CTRL_SPD1000 BIT(1) +#define PORT_REG_PHYS_CTRL_SPD_MASK (BIT(1) | BIT(0)) #define PORT_REG_CTRL_PSTATE_SHIFT 0 #define PORT_REG_CTRL_PSTATE_WIDTH 2 @@ -166,6 +174,14 @@ #error Define CONFIG_MV88E61XX_CPU_PORT to the port the CPU is attached to #endif +/* + * These are ports without PHYs that may be wired directly + * to other serdes interfaces + */ +#ifndef CONFIG_MV88E61XX_FIXED_PORTS +#define CONFIG_MV88E61XX_FIXED_PORTS 0 +#endif + /* ID register values for different switch models */ #define PORT_SWITCH_ID_6096 0x0980 #define PORT_SWITCH_ID_6097 0x0990 @@ -793,6 +809,27 @@ static int mv88e61xx_phy_setup(struct phy_device *phydev, u8 phy) return 0; } +static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port) +{ + int val; + + val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL); + if (val < 0) + return val; + + val &= ~(PORT_REG_PHYS_CTRL_SPD_MASK | + PORT_REG_PHYS_CTRL_FC_VALUE); + val |= PORT_REG_PHYS_CTRL_PCS_AN_EN | + PORT_REG_PHYS_CTRL_PCS_AN_RST | + PORT_REG_PHYS_CTRL_FC_FORCE | + PORT_REG_PHYS_CTRL_DUPLEX_VALUE | + PORT_REG_PHYS_CTRL_DUPLEX_FORCE | + PORT_REG_PHYS_CTRL_SPD1000; + + return mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL, + val); +} + static int mv88e61xx_phy_config_port(struct phy_device *phydev, u8 phy) { int val; @@ -911,6 +948,12 @@ static int mv88e61xx_phy_config(struct phy_device *phydev) /* Return success if any PHY succeeds */ ret = 0; + } else if ((1 << i) & CONFIG_MV88E61XX_FIXED_PORTS) { + res = mv88e61xx_fixed_port_setup(phydev, i); + if (res < 0) { + printf("Error configuring port %i\n", i); + continue; + } } } -- cgit v1.1 From 6723b235520190bdc774760126fc063ec794c37f Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Mon, 29 Aug 2016 20:54:02 +1200 Subject: net: mvneta: fix typo in comment Signed-off-by: Chris Packham Acked-by: Joe Hershberger --- drivers/net/mvneta.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c index 51bb569..00f378f 100644 --- a/drivers/net/mvneta.c +++ b/drivers/net/mvneta.c @@ -1619,7 +1619,7 @@ static int mvneta_probe(struct udevice *dev) /* * Allocate buffer area for descs and rx_buffers. This is only * done once for all interfaces. As only one interface can - * be active. Make this area DMA save by disabling the D-cache + * be active. Make this area DMA safe by disabling the D-cache */ if (!buffer_loc.tx_descs) { /* Align buffer area for descs and rx_buffers to 1MiB */ -- cgit v1.1 From 7377647a3678c50c1913f05d8ad8d685b05e52d1 Mon Sep 17 00:00:00 2001 From: Peter Chubb Date: Wed, 14 Sep 2016 01:29:03 +0000 Subject: rtl8169: fix cache misalignment message on transmit. The call to flush cache on the transmit buffer was misplaced (for very short packets) and asked to flush less than a cacheline. Move the flush cache call to after a short packet has been padded to minimum length (so the padding is flushed too), and round the size up to a cacheline. Signed-off-by: Peter Chubb Acked-by: Joe Hershberger --- drivers/net/rtl8169.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c index 1cc0b40..a3f4423 100644 --- a/drivers/net/rtl8169.c +++ b/drivers/net/rtl8169.c @@ -629,11 +629,12 @@ static int rtl_send_common(pci_dev_t dev, unsigned long dev_iobase, /* point to the current txb incase multiple tx_rings are used */ ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE]; memcpy(ptxb, (char *)packet, (int)length); - rtl_flush_buffer(ptxb, length); while (len < ETH_ZLEN) ptxb[len++] = '\0'; + rtl_flush_buffer(ptxb, ALIGN(len, RTL8169_ALIGN)); + tpc->TxDescArray[entry].buf_Haddr = 0; #ifdef CONFIG_DM_ETH tpc->TxDescArray[entry].buf_addr = cpu_to_le32( -- cgit v1.1 From c9abfbdd66ed97e1cac8553d0b31bd23f68480a9 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 15 Sep 2016 12:53:22 -0600 Subject: net: smsc95xx: fix DM MAC address reading eth-uclass.c expects DM-capable Ethernet adapters to implement ops-> read_rom_hwaddr(), or for some other mechanism to set pdata->enetaddr, or for the user to set environment variable $usbethaddr. Without any of these, it will refuse to initialize the device since no valid MAC address is known. Implement this function for the smsc95xx driver. With this feature implemented, there is no point smsc95xx_init_common() re-reading the MAC address from ROM, so ifdef out this code when DM_ETH is enabled. This allows (at least) the built-in Ethernet on the NVIDIA Harmony board to operate again. Fixes: 0990fcb77219 ("net: smsc95xx: Add driver-model support") Signed-off-by: Stephen Warren Acked-by: Joe Hershberger --- drivers/usb/eth/smsc95xx.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'drivers') diff --git a/drivers/usb/eth/smsc95xx.c b/drivers/usb/eth/smsc95xx.c index 7d9abfd..d4c8ea4 100644 --- a/drivers/usb/eth/smsc95xx.c +++ b/drivers/usb/eth/smsc95xx.c @@ -519,9 +519,11 @@ static int smsc95xx_init_common(struct usb_device *udev, struct ueth_data *dev, debug("timeout waiting for PHY Reset\n"); return -ETIMEDOUT; } +#ifndef CONFIG_DM_ETH if (!priv->have_hwaddr && smsc95xx_init_mac_address(enetaddr, udev) == 0) priv->have_hwaddr = 1; +#endif if (!priv->have_hwaddr) { puts("Error: SMSC95xx: No MAC address set - set usbethaddr\n"); return -EADDRNOTAVAIL; @@ -1022,6 +1024,19 @@ int smsc95xx_write_hwaddr(struct udevice *dev) return smsc95xx_write_hwaddr_common(udev, priv, pdata->enetaddr); } +int smsc95xx_read_rom_hwaddr(struct udevice *dev) +{ + struct usb_device *udev = dev_get_parent_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + int ret; + + ret = smsc95xx_init_mac_address(pdata->enetaddr, udev); + if (ret) + memset(pdata->enetaddr, 0, 6); + + return 0; +} + static int smsc95xx_eth_probe(struct udevice *dev) { struct smsc95xx_private *priv = dev_get_priv(dev); @@ -1037,6 +1052,7 @@ static const struct eth_ops smsc95xx_eth_ops = { .free_pkt = smsc95xx_free_pkt, .stop = smsc95xx_eth_stop, .write_hwaddr = smsc95xx_write_hwaddr, + .read_rom_hwaddr = smsc95xx_read_rom_hwaddr, }; U_BOOT_DRIVER(smsc95xx_eth) = { -- cgit v1.1