From 46683f3da191a4c2156d5473c23b9923c461912c Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Fri, 22 Jul 2016 17:22:50 +0800 Subject: mmc-uclass: correct the device number Not like the mmc-legacy which the devnum starts from 1, it starts from 0 in mmc-uclass, so the device number should be (devnum + 1) in get_mmc_num(). Signed-off-by: Kever Yang Acked-by: Simon Glass Reviewed-by: Jaehoon Chung --- drivers/mmc/mmc-uclass.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c index 38ced41..f262c6e 100644 --- a/drivers/mmc/mmc-uclass.c +++ b/drivers/mmc/mmc-uclass.c @@ -111,18 +111,18 @@ struct mmc *find_mmc_device(int dev_num) int get_mmc_num(void) { - return max(blk_find_max_devnum(IF_TYPE_MMC), 0); + return max((blk_find_max_devnum(IF_TYPE_MMC) + 1), 0); } int mmc_get_next_devnum(void) { int ret; - ret = get_mmc_num(); + ret = blk_find_max_devnum(IF_TYPE_MMC); if (ret < 0) return ret; - return ret + 1; + return ret; } struct blk_desc *mmc_get_blk_desc(struct mmc *mmc) -- cgit v1.1 From 2b51784aef46523ed70916b09de125bc5fbefa25 Mon Sep 17 00:00:00 2001 From: John Keeping Date: Mon, 25 Jul 2016 10:02:05 +0100 Subject: rockchip: rk3288: Fix pinctrl for GPIO bank 0 Bank 0 is the "PMU GPIO" bank which is controlled by the PMU registers rather than the GRF registers. In the GRF the top half of the register is used as a mask so that some bits can be updated without affecting the others, but in the PMU this feature is not provided and the top half of the register is reserved. Take the same approach as the Linux driver to update the value via read-modify-write but setting the mask for only the bits that have changed. The PMU registers ignore the top 16 bits so this works for both GRF and PMU iomux registers. Signed-off-by: John Keeping Reviewed-by: Kever Yang --- drivers/pinctrl/rockchip/pinctrl_rk3288.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3288.c b/drivers/pinctrl/rockchip/pinctrl_rk3288.c index ae8a4f1..0322264 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3288.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3288.c @@ -588,6 +588,7 @@ static int rk3288_pinctrl_set_pins(struct udevice *dev, int banknum, int index, struct rk3288_pinctrl_priv *priv = dev_get_priv(dev); uint shift, ind = index; uint mask; + uint value; u32 *addr; int ret; @@ -596,7 +597,18 @@ static int rk3288_pinctrl_set_pins(struct udevice *dev, int banknum, int index, &mask); if (ret) return ret; - rk_clrsetreg(addr, mask << shift, muxval << shift); + + /* + * PMU_GPIO0 registers cannot be selectively written so we cannot use + * rk_clrsetreg() here. However, the upper 16 bits are reserved and + * are ignored when written, so we can use the same code as for the + * other GPIO banks providing that we preserve the value of the other + * bits. + */ + value = readl(addr); + value &= ~(mask << shift); + value |= (mask << (shift + 16)) | (muxval << shift); + writel(value, addr); /* Handle pullup/pulldown */ if (flags) { @@ -614,7 +626,12 @@ static int rk3288_pinctrl_set_pins(struct udevice *dev, int banknum, int index, addr = &priv->grf->gpio1_p[banknum - 1][ind]; debug("%s: addr=%p, val=%x, shift=%x\n", __func__, addr, val, shift); - rk_clrsetreg(addr, 3 << shift, val << shift); + + /* As above, rk_clrsetreg() cannot be used here. */ + value = readl(addr); + value &= ~(mask << shift); + value |= (3 << (shift + 16)) | (val << shift); + writel(value, addr); } return 0; -- cgit v1.1