From cd1011db80287eef933d1599b74cff1116c93134 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Mon, 21 Sep 2009 11:20:31 -0500 Subject: tsec: Remove PHY command relocation fixups Signed-off-by: Peter Tyser --- drivers/net/tsec.c | 49 ------------------------------------------------- 1 file changed, 49 deletions(-) (limited to 'drivers') diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 5c3d261..3f74118 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -35,8 +35,6 @@ typedef volatile struct rtxbd { #define MAXCONTROLLERS (8) -static int relocated = 0; - static struct tsec_private *privlist[MAXCONTROLLERS]; static int num_tsecs = 0; @@ -59,7 +57,6 @@ uint read_phy_reg(struct tsec_private *priv, uint regnum); struct phy_info *get_phy_info(struct eth_device *dev); void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd); static void adjust_link(struct eth_device *dev); -static void relocate_cmds(void); #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ && !defined(BITBANGMII) static int tsec_miiphy_write(char *devname, unsigned char addr, @@ -321,9 +318,6 @@ static int init_phy(struct eth_device *dev) asm("sync"); while (priv->phyregs->miimind & MIIMIND_BUSY) ; - if (0 == relocated) - relocate_cmds(); - /* Get the cmd structure corresponding to the attached * PHY */ curphy = get_phy_info(dev); @@ -1800,49 +1794,6 @@ void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd) } } -/* Relocate the function pointers in the phy cmd lists */ -static void relocate_cmds(void) -{ - struct phy_cmd **cmdlistptr; - struct phy_cmd *cmd; - int i, j, k; - - for (i = 0; phy_info[i]; i++) { - /* First thing's first: relocate the pointers to the - * PHY command structures (the structs were done) */ - phy_info[i] = (struct phy_info *)((uint) phy_info[i] - + gd->reloc_off); - phy_info[i]->name += gd->reloc_off; - phy_info[i]->config = - (struct phy_cmd *)((uint) phy_info[i]->config - + gd->reloc_off); - phy_info[i]->startup = - (struct phy_cmd *)((uint) phy_info[i]->startup - + gd->reloc_off); - phy_info[i]->shutdown = - (struct phy_cmd *)((uint) phy_info[i]->shutdown - + gd->reloc_off); - - cmdlistptr = &phy_info[i]->config; - j = 0; - for (; cmdlistptr <= &phy_info[i]->shutdown; cmdlistptr++) { - k = 0; - for (cmd = *cmdlistptr; - cmd->mii_reg != miim_end; - cmd++) { - /* Only relocate non-NULL pointers */ - if (cmd->funct) - cmd->funct += gd->reloc_off; - - k++; - } - j++; - } - } - - relocated = 1; -} - #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ && !defined(BITBANGMII) -- cgit v1.1 From 6385b28116f775da4771b768ba9bf93c3aaaf26e Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Mon, 21 Sep 2009 11:20:32 -0500 Subject: fpga: Remove relocation fixups PPC boards are the only users of the current FPGA code which is littered with manual relocation fixups. Now that proper relocation is supported for PPC boards, remove FPGA manual relocation. Signed-off-by: Peter Tyser --- drivers/fpga/ACEX1K.c | 96 ------------------------ drivers/fpga/altera.c | 39 ---------- drivers/fpga/cyclon2.c | 91 ----------------------- drivers/fpga/fpga.c | 53 ++------------ drivers/fpga/spartan2.c | 187 ----------------------------------------------- drivers/fpga/spartan3.c | 185 ---------------------------------------------- drivers/fpga/stratixII.c | 24 ------ drivers/fpga/virtex2.c | 118 ------------------------------ drivers/fpga/xilinx.c | 42 ----------- 9 files changed, 5 insertions(+), 830 deletions(-) (limited to 'drivers') diff --git a/drivers/fpga/ACEX1K.c b/drivers/fpga/ACEX1K.c index 3f79677..06b4247 100644 --- a/drivers/fpga/ACEX1K.c +++ b/drivers/fpga/ACEX1K.c @@ -51,7 +51,6 @@ static int ACEX1K_ps_load( Altera_desc *desc, void *buf, size_t bsize ); static int ACEX1K_ps_dump( Altera_desc *desc, void *buf, size_t bsize ); /* static int ACEX1K_ps_info( Altera_desc *desc ); */ -static int ACEX1K_ps_reloc( Altera_desc *desc, ulong reloc_offset ); /* ------------------------------------------------------------------------- */ /* ACEX1K Generic Implementation */ @@ -101,31 +100,6 @@ int ACEX1K_info( Altera_desc *desc ) } -int ACEX1K_reloc (Altera_desc * desc, ulong reloc_offset) -{ - int ret_val = FPGA_FAIL; /* assume a failure */ - - if (desc->family != Altera_ACEX1K) { - printf ("%s: Unsupported family type, %d\n", - __FUNCTION__, desc->family); - return FPGA_FAIL; - } else - switch (desc->iface) { - case passive_serial: - ret_val = ACEX1K_ps_reloc (desc, reloc_offset); - break; - - /* Add new interface types here */ - - default: - printf ("%s: Unsupported interface type, %d\n", - __FUNCTION__, desc->iface); - } - - return ret_val; -} - - /* ------------------------------------------------------------------------- */ /* ACEX1K Passive Serial Generic Implementation */ @@ -290,73 +264,3 @@ static int ACEX1K_ps_dump (Altera_desc * desc, void *buf, size_t bsize) __FUNCTION__); return FPGA_FAIL; } - -static int ACEX1K_ps_reloc (Altera_desc * desc, ulong reloc_offset) -{ - int ret_val = FPGA_FAIL; /* assume the worst */ - Altera_ACEX1K_Passive_Serial_fns *fn_r, *fn = - (Altera_ACEX1K_Passive_Serial_fns *) (desc->iface_fns); - - if (fn) { - ulong addr; - - /* Get the relocated table address */ - addr = (ulong) fn + reloc_offset; - fn_r = (Altera_ACEX1K_Passive_Serial_fns *) addr; - - if (!fn_r->relocated) { - - if (memcmp (fn_r, fn, - sizeof (Altera_ACEX1K_Passive_Serial_fns)) - == 0) { - /* good copy of the table, fix the descriptor pointer */ - desc->iface_fns = fn_r; - } else { - PRINTF ("%s: Invalid function table at 0x%p\n", - __FUNCTION__, fn_r); - return FPGA_FAIL; - } - - PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__, - desc); - - addr = (ulong) (fn->pre) + reloc_offset; - fn_r->pre = (Altera_pre_fn) addr; - - addr = (ulong) (fn->config) + reloc_offset; - fn_r->config = (Altera_config_fn) addr; - - addr = (ulong) (fn->status) + reloc_offset; - fn_r->status = (Altera_status_fn) addr; - - addr = (ulong) (fn->done) + reloc_offset; - fn_r->done = (Altera_done_fn) addr; - - addr = (ulong) (fn->clk) + reloc_offset; - fn_r->clk = (Altera_clk_fn) addr; - - addr = (ulong) (fn->data) + reloc_offset; - fn_r->data = (Altera_data_fn) addr; - - addr = (ulong) (fn->abort) + reloc_offset; - fn_r->abort = (Altera_abort_fn) addr; - - addr = (ulong) (fn->post) + reloc_offset; - fn_r->post = (Altera_post_fn) addr; - - fn_r->relocated = TRUE; - - } else { - /* this table has already been moved */ - /* XXX - should check to see if the descriptor is correct */ - desc->iface_fns = fn_r; - } - - ret_val = FPGA_SUCCESS; - } else { - printf ("%s: NULL Interface function table!\n", __FUNCTION__); - } - - return ret_val; - -} diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c index 09dc0b2..650f2ec 100644 --- a/drivers/fpga/altera.c +++ b/drivers/fpga/altera.c @@ -211,45 +211,6 @@ int altera_info( Altera_desc *desc ) return ret_val; } -int altera_reloc( Altera_desc *desc, ulong reloc_offset) -{ - int ret_val = FPGA_FAIL; /* assume a failure */ - - if (!altera_validate (desc, (char *)__FUNCTION__)) { - printf ("%s: Invalid device descriptor\n", __FUNCTION__); - } else { - switch (desc->family) { - case Altera_ACEX1K: -#if defined(CONFIG_FPGA_ACEX1K) - ret_val = ACEX1K_reloc (desc, reloc_offset); -#else - printf ("%s: No support for ACEX devices.\n", - __FUNCTION__); -#endif - break; -#if defined(CONFIG_FPGA_STRATIX_II) - case Altera_StratixII: - ret_val = StratixII_reloc (desc, reloc_offset); - break; -#endif - case Altera_CYC2: -#if defined(CONFIG_FPGA_CYCLON2) - ret_val = CYC2_reloc (desc, reloc_offset); -#else - printf ("%s: No support for CYCLON II devices.\n", - __FUNCTION__); -#endif - break; - /* Add new family types here */ - default: - printf ("%s: Unsupported family type, %d\n", - __FUNCTION__, desc->family); - } - } - - return ret_val; -} - /* ------------------------------------------------------------------------- */ static int altera_validate (Altera_desc * desc, const char *fn) diff --git a/drivers/fpga/cyclon2.c b/drivers/fpga/cyclon2.c index 3ed64b2..4622b4e 100644 --- a/drivers/fpga/cyclon2.c +++ b/drivers/fpga/cyclon2.c @@ -50,7 +50,6 @@ static int CYC2_ps_load( Altera_desc *desc, void *buf, size_t bsize ); static int CYC2_ps_dump( Altera_desc *desc, void *buf, size_t bsize ); /* static int CYC2_ps_info( Altera_desc *desc ); */ -static int CYC2_ps_reloc( Altera_desc *desc, ulong reloc_offset ); /* ------------------------------------------------------------------------- */ /* CYCLON2 Generic Implementation */ @@ -99,30 +98,6 @@ int CYC2_info( Altera_desc *desc ) return FPGA_SUCCESS; } -int CYC2_reloc (Altera_desc * desc, ulong reloc_offset) -{ - int ret_val = FPGA_FAIL; /* assume a failure */ - - if (desc->family != Altera_CYC2) { - printf ("%s: Unsupported family type, %d\n", - __FUNCTION__, desc->family); - return FPGA_FAIL; - } else - switch (desc->iface) { - case passive_serial: - ret_val = CYC2_ps_reloc (desc, reloc_offset); - break; - - /* Add new interface types here */ - - default: - printf ("%s: Unsupported interface type, %d\n", - __FUNCTION__, desc->iface); - } - - return ret_val; -} - /* ------------------------------------------------------------------------- */ /* CYCLON2 Passive Serial Generic Implementation */ static int CYC2_ps_load (Altera_desc * desc, void *buf, size_t bsize) @@ -233,69 +208,3 @@ static int CYC2_ps_dump (Altera_desc * desc, void *buf, size_t bsize) __FUNCTION__); return FPGA_FAIL; } - -static int CYC2_ps_reloc (Altera_desc * desc, ulong reloc_offset) -{ - int ret_val = FPGA_FAIL; /* assume the worst */ - Altera_CYC2_Passive_Serial_fns *fn_r, *fn = - (Altera_CYC2_Passive_Serial_fns *) (desc->iface_fns); - - if (fn) { - ulong addr; - - /* Get the relocated table address */ - addr = (ulong) fn + reloc_offset; - fn_r = (Altera_CYC2_Passive_Serial_fns *) addr; - - if (!fn_r->relocated) { - - if (memcmp (fn_r, fn, - sizeof (Altera_CYC2_Passive_Serial_fns)) - == 0) { - /* good copy of the table, fix the descriptor pointer */ - desc->iface_fns = fn_r; - } else { - PRINTF ("%s: Invalid function table at 0x%p\n", - __FUNCTION__, fn_r); - return FPGA_FAIL; - } - - PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__, - desc); - - addr = (ulong) (fn->pre) + reloc_offset; - fn_r->pre = (Altera_pre_fn) addr; - - addr = (ulong) (fn->config) + reloc_offset; - fn_r->config = (Altera_config_fn) addr; - - addr = (ulong) (fn->status) + reloc_offset; - fn_r->status = (Altera_status_fn) addr; - - addr = (ulong) (fn->done) + reloc_offset; - fn_r->done = (Altera_done_fn) addr; - - addr = (ulong) (fn->write) + reloc_offset; - fn_r->write = (Altera_write_fn) addr; - - addr = (ulong) (fn->abort) + reloc_offset; - fn_r->abort = (Altera_abort_fn) addr; - - addr = (ulong) (fn->post) + reloc_offset; - fn_r->post = (Altera_post_fn) addr; - - fn_r->relocated = TRUE; - - } else { - /* this table has already been moved */ - /* XXX - should check to see if the descriptor is correct */ - desc->iface_fns = fn_r; - } - - ret_val = FPGA_SUCCESS; - } else { - printf ("%s: NULL Interface function table!\n", __FUNCTION__); - } - - return ret_val; -} diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c index 67a6c30..5659517 100644 --- a/drivers/fpga/fpga.c +++ b/drivers/fpga/fpga.c @@ -46,7 +46,6 @@ #endif /* Local static data */ -static ulong relocation_offset = 0; static int next_desc = FPGA_INVALID_DEVICE; static fpga_desc desc_table[CONFIG_MAX_FPGA_DEVICES]; @@ -153,46 +152,12 @@ static int fpga_dev_info( int devnum ) } -/* fpga_reloc - * generic multiplexing code - */ -int fpga_reloc( fpga_type devtype, void *desc, ulong reloc_off ) -{ - int ret_val = FPGA_FAIL; - - PRINTF( "%s: Relocating Device of type %d @ 0x%p with offset %lx\n", - __FUNCTION__, devtype, desc, reloc_off ); - - switch ( devtype ) { - case fpga_xilinx: -#if defined(CONFIG_FPGA_XILINX) - ret_val = xilinx_reloc( desc, reloc_off ); -#else - fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" ); -#endif - break; - case fpga_altera: -#if defined(CONFIG_FPGA_ALTERA) - ret_val = altera_reloc( desc, reloc_off ); -#else - fpga_no_sup( (char *)__FUNCTION__, "Altera devices" ); -#endif - break; - default: - printf( "%s: Invalid or unsupported device type %d\n", - __FUNCTION__, devtype ); - } - - return ret_val; -} - /* ------------------------------------------------------------------------- */ /* fgpa_init is usually called from misc_init_r() and MUST be called * before any of the other fpga functions are used. */ -void fpga_init( ulong reloc_off ) +void fpga_init(void) { - relocation_offset = reloc_off; next_desc = 0; memset( desc_table, 0, sizeof(desc_table)); @@ -208,9 +173,7 @@ int fpga_count( void ) } /* fpga_add - * Attempts to relocate the device/board specific interface code - * to the proper RAM locations and adds the device descriptor to - * the device table. + * Add the device descriptor to the device table. */ int fpga_add( fpga_type devtype, void *desc ) { @@ -221,15 +184,9 @@ int fpga_add( fpga_type devtype, void *desc ) } else if (( devtype > fpga_min_type ) && ( devtype < fpga_undefined )) { if ( desc ) { if ( next_desc < CONFIG_MAX_FPGA_DEVICES ) { - if ( fpga_reloc( devtype, desc, relocation_offset ) - == FPGA_SUCCESS ) { - devnum = next_desc; - desc_table[next_desc].devtype = devtype; - desc_table[next_desc++].devdesc = desc; - } else { - printf( "%s: Unable to relocate device interface table!\n", - __FUNCTION__ ); - } + devnum = next_desc; + desc_table[next_desc].devtype = devtype; + desc_table[next_desc++].devdesc = desc; } else { printf( "%s: Exceeded Max FPGA device count\n", __FUNCTION__ ); } diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c index d745334..cd16a9c 100644 --- a/drivers/fpga/spartan2.c +++ b/drivers/fpga/spartan2.c @@ -51,12 +51,10 @@ static int Spartan2_sp_load( Xilinx_desc *desc, void *buf, size_t bsize ); static int Spartan2_sp_dump( Xilinx_desc *desc, void *buf, size_t bsize ); /* static int Spartan2_sp_info( Xilinx_desc *desc ); */ -static int Spartan2_sp_reloc( Xilinx_desc *desc, ulong reloc_offset ); static int Spartan2_ss_load( Xilinx_desc *desc, void *buf, size_t bsize ); static int Spartan2_ss_dump( Xilinx_desc *desc, void *buf, size_t bsize ); /* static int Spartan2_ss_info( Xilinx_desc *desc ); */ -static int Spartan2_ss_reloc( Xilinx_desc *desc, ulong reloc_offset ); /* ------------------------------------------------------------------------- */ /* Spartan-II Generic Implementation */ @@ -112,33 +110,6 @@ int Spartan2_info( Xilinx_desc *desc ) } -int Spartan2_reloc (Xilinx_desc * desc, ulong reloc_offset) -{ - int ret_val = FPGA_FAIL; /* assume a failure */ - - if (desc->family != Xilinx_Spartan2) { - printf ("%s: Unsupported family type, %d\n", - __FUNCTION__, desc->family); - return FPGA_FAIL; - } else - switch (desc->iface) { - case slave_serial: - ret_val = Spartan2_ss_reloc (desc, reloc_offset); - break; - - case slave_parallel: - ret_val = Spartan2_sp_reloc (desc, reloc_offset); - break; - - default: - printf ("%s: Unsupported interface type, %d\n", - __FUNCTION__, desc->iface); - } - - return ret_val; -} - - /* ------------------------------------------------------------------------- */ /* Spartan-II Slave Parallel Generic Implementation */ @@ -340,93 +311,6 @@ static int Spartan2_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize) } -static int Spartan2_sp_reloc (Xilinx_desc * desc, ulong reloc_offset) -{ - int ret_val = FPGA_FAIL; /* assume the worst */ - Xilinx_Spartan2_Slave_Parallel_fns *fn_r, *fn = - (Xilinx_Spartan2_Slave_Parallel_fns *) (desc->iface_fns); - - if (fn) { - ulong addr; - - /* Get the relocated table address */ - addr = (ulong) fn + reloc_offset; - fn_r = (Xilinx_Spartan2_Slave_Parallel_fns *) addr; - - if (!fn_r->relocated) { - - if (memcmp (fn_r, fn, - sizeof (Xilinx_Spartan2_Slave_Parallel_fns)) - == 0) { - /* good copy of the table, fix the descriptor pointer */ - desc->iface_fns = fn_r; - } else { - PRINTF ("%s: Invalid function table at 0x%p\n", - __FUNCTION__, fn_r); - return FPGA_FAIL; - } - - PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__, - desc); - - addr = (ulong) (fn->pre) + reloc_offset; - fn_r->pre = (Xilinx_pre_fn) addr; - - addr = (ulong) (fn->pgm) + reloc_offset; - fn_r->pgm = (Xilinx_pgm_fn) addr; - - addr = (ulong) (fn->init) + reloc_offset; - fn_r->init = (Xilinx_init_fn) addr; - - addr = (ulong) (fn->done) + reloc_offset; - fn_r->done = (Xilinx_done_fn) addr; - - addr = (ulong) (fn->clk) + reloc_offset; - fn_r->clk = (Xilinx_clk_fn) addr; - - addr = (ulong) (fn->err) + reloc_offset; - fn_r->err = (Xilinx_err_fn) addr; - - addr = (ulong) (fn->cs) + reloc_offset; - fn_r->cs = (Xilinx_cs_fn) addr; - - addr = (ulong) (fn->wr) + reloc_offset; - fn_r->wr = (Xilinx_wr_fn) addr; - - addr = (ulong) (fn->rdata) + reloc_offset; - fn_r->rdata = (Xilinx_rdata_fn) addr; - - addr = (ulong) (fn->wdata) + reloc_offset; - fn_r->wdata = (Xilinx_wdata_fn) addr; - - addr = (ulong) (fn->busy) + reloc_offset; - fn_r->busy = (Xilinx_busy_fn) addr; - - addr = (ulong) (fn->abort) + reloc_offset; - fn_r->abort = (Xilinx_abort_fn) addr; - - if (fn->post) { - addr = (ulong) (fn->post) + reloc_offset; - fn_r->post = (Xilinx_post_fn) addr; - } - - fn_r->relocated = TRUE; - - } else { - /* this table has already been moved */ - /* XXX - should check to see if the descriptor is correct */ - desc->iface_fns = fn_r; - } - - ret_val = FPGA_SUCCESS; - } else { - printf ("%s: NULL Interface function table!\n", __FUNCTION__); - } - - return ret_val; - -} - /* ------------------------------------------------------------------------- */ static int Spartan2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) @@ -580,74 +464,3 @@ static int Spartan2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize) __FUNCTION__); return FPGA_FAIL; } - -static int Spartan2_ss_reloc (Xilinx_desc * desc, ulong reloc_offset) -{ - int ret_val = FPGA_FAIL; /* assume the worst */ - Xilinx_Spartan2_Slave_Serial_fns *fn_r, *fn = - (Xilinx_Spartan2_Slave_Serial_fns *) (desc->iface_fns); - - if (fn) { - ulong addr; - - /* Get the relocated table address */ - addr = (ulong) fn + reloc_offset; - fn_r = (Xilinx_Spartan2_Slave_Serial_fns *) addr; - - if (!fn_r->relocated) { - - if (memcmp (fn_r, fn, - sizeof (Xilinx_Spartan2_Slave_Serial_fns)) - == 0) { - /* good copy of the table, fix the descriptor pointer */ - desc->iface_fns = fn_r; - } else { - PRINTF ("%s: Invalid function table at 0x%p\n", - __FUNCTION__, fn_r); - return FPGA_FAIL; - } - - PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__, - desc); - - if (fn->pre) { - addr = (ulong) (fn->pre) + reloc_offset; - fn_r->pre = (Xilinx_pre_fn) addr; - } - - addr = (ulong) (fn->pgm) + reloc_offset; - fn_r->pgm = (Xilinx_pgm_fn) addr; - - addr = (ulong) (fn->init) + reloc_offset; - fn_r->init = (Xilinx_init_fn) addr; - - addr = (ulong) (fn->done) + reloc_offset; - fn_r->done = (Xilinx_done_fn) addr; - - addr = (ulong) (fn->clk) + reloc_offset; - fn_r->clk = (Xilinx_clk_fn) addr; - - addr = (ulong) (fn->wr) + reloc_offset; - fn_r->wr = (Xilinx_wr_fn) addr; - - if (fn->post) { - addr = (ulong) (fn->post) + reloc_offset; - fn_r->post = (Xilinx_post_fn) addr; - } - - fn_r->relocated = TRUE; - - } else { - /* this table has already been moved */ - /* XXX - should check to see if the descriptor is correct */ - desc->iface_fns = fn_r; - } - - ret_val = FPGA_SUCCESS; - } else { - printf ("%s: NULL Interface function table!\n", __FUNCTION__); - } - - return ret_val; - -} diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c index 8bb2449..0fe3041 100644 --- a/drivers/fpga/spartan3.c +++ b/drivers/fpga/spartan3.c @@ -56,12 +56,10 @@ static int Spartan3_sp_load( Xilinx_desc *desc, void *buf, size_t bsize ); static int Spartan3_sp_dump( Xilinx_desc *desc, void *buf, size_t bsize ); /* static int Spartan3_sp_info( Xilinx_desc *desc ); */ -static int Spartan3_sp_reloc( Xilinx_desc *desc, ulong reloc_offset ); static int Spartan3_ss_load( Xilinx_desc *desc, void *buf, size_t bsize ); static int Spartan3_ss_dump( Xilinx_desc *desc, void *buf, size_t bsize ); /* static int Spartan3_ss_info( Xilinx_desc *desc ); */ -static int Spartan3_ss_reloc( Xilinx_desc *desc, ulong reloc_offset ); /* ------------------------------------------------------------------------- */ /* Spartan-II Generic Implementation */ @@ -117,33 +115,6 @@ int Spartan3_info( Xilinx_desc *desc ) } -int Spartan3_reloc (Xilinx_desc * desc, ulong reloc_offset) -{ - int ret_val = FPGA_FAIL; /* assume a failure */ - - if (desc->family != Xilinx_Spartan3) { - printf ("%s: Unsupported family type, %d\n", - __FUNCTION__, desc->family); - return FPGA_FAIL; - } else - switch (desc->iface) { - case slave_serial: - ret_val = Spartan3_ss_reloc (desc, reloc_offset); - break; - - case slave_parallel: - ret_val = Spartan3_sp_reloc (desc, reloc_offset); - break; - - default: - printf ("%s: Unsupported interface type, %d\n", - __FUNCTION__, desc->iface); - } - - return ret_val; -} - - /* ------------------------------------------------------------------------- */ /* Spartan-II Slave Parallel Generic Implementation */ @@ -347,91 +318,6 @@ static int Spartan3_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize) } -static int Spartan3_sp_reloc (Xilinx_desc * desc, ulong reloc_offset) -{ - int ret_val = FPGA_FAIL; /* assume the worst */ - Xilinx_Spartan3_Slave_Parallel_fns *fn_r, *fn = - (Xilinx_Spartan3_Slave_Parallel_fns *) (desc->iface_fns); - - if (fn) { - ulong addr; - - /* Get the relocated table address */ - addr = (ulong) fn + reloc_offset; - fn_r = (Xilinx_Spartan3_Slave_Parallel_fns *) addr; - - if (!fn_r->relocated) { - - if (memcmp (fn_r, fn, - sizeof (Xilinx_Spartan3_Slave_Parallel_fns)) - == 0) { - /* good copy of the table, fix the descriptor pointer */ - desc->iface_fns = fn_r; - } else { - PRINTF ("%s: Invalid function table at 0x%p\n", - __FUNCTION__, fn_r); - return FPGA_FAIL; - } - - PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__, - desc); - - addr = (ulong) (fn->pre) + reloc_offset; - fn_r->pre = (Xilinx_pre_fn) addr; - - addr = (ulong) (fn->pgm) + reloc_offset; - fn_r->pgm = (Xilinx_pgm_fn) addr; - - addr = (ulong) (fn->init) + reloc_offset; - fn_r->init = (Xilinx_init_fn) addr; - - addr = (ulong) (fn->done) + reloc_offset; - fn_r->done = (Xilinx_done_fn) addr; - - addr = (ulong) (fn->clk) + reloc_offset; - fn_r->clk = (Xilinx_clk_fn) addr; - - addr = (ulong) (fn->err) + reloc_offset; - fn_r->err = (Xilinx_err_fn) addr; - - addr = (ulong) (fn->cs) + reloc_offset; - fn_r->cs = (Xilinx_cs_fn) addr; - - addr = (ulong) (fn->wr) + reloc_offset; - fn_r->wr = (Xilinx_wr_fn) addr; - - addr = (ulong) (fn->rdata) + reloc_offset; - fn_r->rdata = (Xilinx_rdata_fn) addr; - - addr = (ulong) (fn->wdata) + reloc_offset; - fn_r->wdata = (Xilinx_wdata_fn) addr; - - addr = (ulong) (fn->busy) + reloc_offset; - fn_r->busy = (Xilinx_busy_fn) addr; - - addr = (ulong) (fn->abort) + reloc_offset; - fn_r->abort = (Xilinx_abort_fn) addr; - - addr = (ulong) (fn->post) + reloc_offset; - fn_r->post = (Xilinx_post_fn) addr; - - fn_r->relocated = TRUE; - - } else { - /* this table has already been moved */ - /* XXX - should check to see if the descriptor is correct */ - desc->iface_fns = fn_r; - } - - ret_val = FPGA_SUCCESS; - } else { - printf ("%s: NULL Interface function table!\n", __FUNCTION__); - } - - return ret_val; - -} - /* ------------------------------------------------------------------------- */ static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) @@ -587,74 +473,3 @@ static int Spartan3_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize) __FUNCTION__); return FPGA_FAIL; } - -static int Spartan3_ss_reloc (Xilinx_desc * desc, ulong reloc_offset) -{ - int ret_val = FPGA_FAIL; /* assume the worst */ - Xilinx_Spartan3_Slave_Serial_fns *fn_r, *fn = - (Xilinx_Spartan3_Slave_Serial_fns *) (desc->iface_fns); - - if (fn) { - ulong addr; - - /* Get the relocated table address */ - addr = (ulong) fn + reloc_offset; - fn_r = (Xilinx_Spartan3_Slave_Serial_fns *) addr; - - if (!fn_r->relocated) { - - if (memcmp (fn_r, fn, - sizeof (Xilinx_Spartan3_Slave_Serial_fns)) - == 0) { - /* good copy of the table, fix the descriptor pointer */ - desc->iface_fns = fn_r; - } else { - PRINTF ("%s: Invalid function table at 0x%p\n", - __FUNCTION__, fn_r); - return FPGA_FAIL; - } - - PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__, - desc); - - if (fn->pre) { - addr = (ulong) (fn->pre) + reloc_offset; - fn_r->pre = (Xilinx_pre_fn) addr; - } - - addr = (ulong) (fn->pgm) + reloc_offset; - fn_r->pgm = (Xilinx_pgm_fn) addr; - - addr = (ulong) (fn->init) + reloc_offset; - fn_r->init = (Xilinx_init_fn) addr; - - addr = (ulong) (fn->done) + reloc_offset; - fn_r->done = (Xilinx_done_fn) addr; - - addr = (ulong) (fn->clk) + reloc_offset; - fn_r->clk = (Xilinx_clk_fn) addr; - - addr = (ulong) (fn->wr) + reloc_offset; - fn_r->wr = (Xilinx_wr_fn) addr; - - if (fn->post) { - addr = (ulong) (fn->post) + reloc_offset; - fn_r->post = (Xilinx_post_fn) addr; - } - - fn_r->relocated = TRUE; - - } else { - /* this table has already been moved */ - /* XXX - should check to see if the descriptor is correct */ - desc->iface_fns = fn_r; - } - - ret_val = FPGA_SUCCESS; - } else { - printf ("%s: NULL Interface function table!\n", __FUNCTION__); - } - - return ret_val; - -} diff --git a/drivers/fpga/stratixII.c b/drivers/fpga/stratixII.c index 7556dbf..8a3a7d8 100644 --- a/drivers/fpga/stratixII.c +++ b/drivers/fpga/stratixII.c @@ -77,30 +77,6 @@ int StratixII_info (Altera_desc * desc) return FPGA_SUCCESS; } -int StratixII_reloc (Altera_desc * desc, ulong reloc_offset) -{ - int i; - uint32_t dest = (uint32_t) desc & 0xff000000; - - /* we assume a relocated code and non relocated code has different upper 8 bits */ - if (dest != ((uint32_t) desc->iface_fns & 0xff000000)) { - desc->iface_fns = - (void *)((uint32_t) (desc->iface_fns) + reloc_offset); - } - for (i = 0; i < sizeof (altera_board_specific_func) / sizeof (void *); - i++) { - if (dest != - ((uint32_t) (((void **)(desc->iface_fns))[i]) & 0xff000000)) - { - ((void **)(desc->iface_fns))[i] = - (void - *)(((uint32_t) (((void **)(desc->iface_fns))[i])) + - reloc_offset); - } - } - return FPGA_SUCCESS; -} - int StratixII_ps_fpp_dump (Altera_desc * desc, void *buf, size_t bsize) { printf ("Stratix II Fast Passive Parallel dump is not implemented\n"); diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index 50d0921..d1b4d15 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -103,11 +103,9 @@ static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize); static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize); -static int Virtex2_ssm_reloc (Xilinx_desc * desc, ulong reloc_offset); static int Virtex2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize); static int Virtex2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize); -static int Virtex2_ss_reloc (Xilinx_desc * desc, ulong reloc_offset); int Virtex2_load (Xilinx_desc * desc, void *buf, size_t bsize) { @@ -158,31 +156,6 @@ int Virtex2_info (Xilinx_desc * desc) return FPGA_SUCCESS; } -int Virtex2_reloc (Xilinx_desc * desc, ulong reloc_offset) -{ - int ret_val = FPGA_FAIL; - - if (desc->family != Xilinx_Virtex2) { - printf ("%s: Unsupported family type, %d\n", - __FUNCTION__, desc->family); - return FPGA_FAIL; - } else - switch (desc->iface) { - case slave_serial: - ret_val = Virtex2_ss_reloc (desc, reloc_offset); - break; - - case slave_selectmap: - ret_val = Virtex2_ssm_reloc (desc, reloc_offset); - break; - - default: - printf ("%s: Unsupported interface type, %d\n", - __FUNCTION__, desc->iface); - } - return ret_val; -} - /* * Virtex-II Slave SelectMap configuration loader. Configuration via * SelectMap is as follows: @@ -448,81 +421,6 @@ static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize) return ret_val; } -/* - * Relocate the addresses in the function table from FLASH (or ROM, - * or whatever) to RAM. - */ -static int Virtex2_ssm_reloc (Xilinx_desc * desc, ulong reloc_offset) -{ - ulong addr; - int ret_val = FPGA_FAIL; - Xilinx_Virtex2_Slave_SelectMap_fns *fn_r, *fn = - (Xilinx_Virtex2_Slave_SelectMap_fns *) (desc->iface_fns); - - if (fn) { - /* - * Get the relocated table address - */ - addr = (ulong) fn + reloc_offset; - fn_r = (Xilinx_Virtex2_Slave_SelectMap_fns *) addr; - - /* - * Check to see if the table has already been relocated. If not, do - * a sanity check to make sure there is a faithful copy of the - * FLASH based function table in RAM, then adjust the table. - */ - if (!fn_r->relocated) { - if (memcmp - (fn_r, fn, sizeof (Xilinx_Virtex2_Slave_SelectMap_fns)) - == 0) { - desc->iface_fns = fn_r; - } else { - PRINTF ("%s:%d: Invalid function table at 0x%p\n", - __FUNCTION__, __LINE__, fn_r); - return FPGA_FAIL; - } - - PRINTF ("%s:%d: Relocating descriptor at 0x%p\n", - __FUNCTION__, __LINE__, desc); - - addr = (ulong) (fn->pre) + reloc_offset; - fn_r->pre = (Xilinx_pre_fn) addr; - addr = (ulong) (fn->pgm) + reloc_offset; - fn_r->pgm = (Xilinx_pgm_fn) addr; - addr = (ulong) (fn->init) + reloc_offset; - fn_r->init = (Xilinx_init_fn) addr; - addr = (ulong) (fn->done) + reloc_offset; - fn_r->done = (Xilinx_done_fn) addr; - addr = (ulong) (fn->err) + reloc_offset; - fn_r->err = (Xilinx_err_fn) addr; - addr = (ulong) (fn->clk) + reloc_offset; - fn_r->clk = (Xilinx_clk_fn) addr; - addr = (ulong) (fn->cs) + reloc_offset; - fn_r->cs = (Xilinx_cs_fn) addr; - addr = (ulong) (fn->wr) + reloc_offset; - fn_r->wr = (Xilinx_wr_fn) addr; - addr = (ulong) (fn->rdata) + reloc_offset; - fn_r->rdata = (Xilinx_rdata_fn) addr; - addr = (ulong) (fn->wdata) + reloc_offset; - fn_r->wdata = (Xilinx_wdata_fn) addr; - addr = (ulong) (fn->busy) + reloc_offset; - fn_r->busy = (Xilinx_busy_fn) addr; - addr = (ulong) (fn->abort) + reloc_offset; - fn_r->abort = (Xilinx_abort_fn) addr; - addr = (ulong) (fn->post) + reloc_offset; - fn_r->post = (Xilinx_post_fn) addr; - fn_r->relocated = TRUE; - } else { - printf ("%s:%d: Function table @0x%p has already been relocated\n", __FUNCTION__, __LINE__, fn_r); - desc->iface_fns = fn_r; - } - ret_val = FPGA_SUCCESS; - } else { - printf ("%s: NULL Interface function table!\n", __FUNCTION__); - } - return ret_val; -} - static int Virtex2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) { printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__); @@ -535,20 +433,4 @@ static int Virtex2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize) return FPGA_FAIL; } -static int Virtex2_ss_reloc (Xilinx_desc * desc, ulong reloc_offset) -{ - int ret_val = FPGA_FAIL; - Xilinx_Virtex2_Slave_Serial_fns *fn = - (Xilinx_Virtex2_Slave_Serial_fns *) (desc->iface_fns); - - if (fn) { - printf ("%s:%d: Slave Serial Loading is unsupported\n", - __FUNCTION__, __LINE__); - } else { - printf ("%s:%d: NULL Interface function table!\n", - __FUNCTION__, __LINE__); - } - return ret_val; -} - /* vim: set ts=4 tw=78: */ diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index 7b5e8c5..08dfdec 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -238,48 +238,6 @@ int xilinx_info (Xilinx_desc * desc) return ret_val; } -int xilinx_reloc (Xilinx_desc * desc, ulong reloc_offset) -{ - int ret_val = FPGA_FAIL; /* assume a failure */ - - if (!xilinx_validate (desc, (char *)__FUNCTION__)) { - printf ("%s: Invalid device descriptor\n", __FUNCTION__); - } else - switch (desc->family) { - case Xilinx_Spartan2: -#if defined(CONFIG_FPGA_SPARTAN2) - ret_val = Spartan2_reloc (desc, reloc_offset); -#else - printf ("%s: No support for Spartan-II devices.\n", - __FUNCTION__); -#endif - break; - case Xilinx_Spartan3: -#if defined(CONFIG_FPGA_SPARTAN3) - ret_val = Spartan3_reloc (desc, reloc_offset); -#else - printf ("%s: No support for Spartan-III devices.\n", - __FUNCTION__); -#endif - break; - case Xilinx_Virtex2: -#if defined(CONFIG_FPGA_VIRTEX2) - ret_val = Virtex2_reloc (desc, reloc_offset); -#else - printf ("%s: No support for Virtex-II devices.\n", - __FUNCTION__); -#endif - break; - /* Add new family types here */ - default: - printf ("%s: Unsupported family type, %d\n", - __FUNCTION__, desc->family); - } - - return ret_val; -} - - /* ------------------------------------------------------------------------- */ static int xilinx_validate (Xilinx_desc * desc, char *fn) -- cgit v1.1 From 521af04d853361b49344b61892eb0618f9f713c5 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Mon, 21 Sep 2009 11:20:36 -0500 Subject: Conditionally perform common relocation fixups Add #ifdefs where necessary to not perform relocation fixups. This allows boards/architectures which support relocation to trim a decent chunk of code. Note that this patch doesn't add #ifdefs to architecture-specific code which does not support relocation. Signed-off-by: Peter Tyser --- drivers/mtd/nand/nand.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c index 9065fa9..47d6872 100644 --- a/drivers/mtd/nand/nand.c +++ b/drivers/mtd/nand/nand.c @@ -54,8 +54,10 @@ static void nand_init_chip(struct mtd_info *mtd, struct nand_chip *nand, if (nand_scan(mtd, maxchips) == 0) { if (!mtd->name) mtd->name = (char *)default_nand_name; +#ifndef CONFIG_RELOC_FIXUP_WORKS else mtd->name += gd->reloc_off; +#endif #ifdef CONFIG_MTD_DEVICE /* -- cgit v1.1 From c0b46d8ead3c6c5b569c83544fd71b9d73356869 Mon Sep 17 00:00:00 2001 From: James Clough Date: Thu, 10 Sep 2009 09:11:50 +0200 Subject: net: Fix problem with 405EZ ethernet interrupt On 405EZ the RX-/TX-interrupts are coalesced into one IRQ bit in the UIC. We need to acknowledge the RX-/TX-interrupts in the SDR0_ICINTSTAT reg as well. This problem was introduced with commit d1631fe1 [ppc4xx: Consolidate PPC4xx UIC defines] Signed-off-by: James Clough Signed-off-by: Stefan Roese Signed-off-by: Ben Warren --- drivers/net/4xx_enet.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'drivers') diff --git a/drivers/net/4xx_enet.c b/drivers/net/4xx_enet.c index afd1084..f2c9be0 100644 --- a/drivers/net/4xx_enet.c +++ b/drivers/net/4xx_enet.c @@ -1717,6 +1717,15 @@ int enetInt (struct eth_device *dev) rc = 0; } } +#if defined(CONFIG_405EZ) + /* + * On 405EZ the RX-/TX-interrupts are coalesced into + * one IRQ bit in the UIC. We need to acknowledge the + * RX-/TX-interrupts in the SDR0_ICINTSTAT reg as well. + */ + mtsdr(SDR0_ICINTSTAT, + SDR_ICRX_STAT | SDR_ICTX0_STAT | SDR_ICTX1_STAT); +#endif /* defined(CONFIG_405EZ) */ } while (serviced); return (rc); -- cgit v1.1 From 32e7f239dda8638377edb0d3e7ac269cabbafbe6 Mon Sep 17 00:00:00 2001 From: Prafulla Wadaskar Date: Mon, 21 Sep 2009 20:28:18 +0530 Subject: net: phy: mv88e61xx.c : fixed build warning MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit following build warning was observed mv88e61xx.c: In function ‘mv88e61xx_busychk’: mv88e61xx.c:208: warning: dereferencing type-punned pointer will break strict-aliasing rules This patch fixes the same Patch tested for rd6281a board build Signed-off-by: Prafulla Wadaskar Signed-off-by: Ben Warren --- drivers/net/phy/mv88e61xx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index 3754e8b..2d1de02 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -201,11 +201,11 @@ static void mv88e61xx_port_vlan_config(struct mv88e61xx_config *swconfig, */ static int mv88e61xx_busychk(char *name) { - u32 reg = 0; + u16 reg = 0; u32 timeout = MV88E61XX_PHY_TIMEOUT; do { RD_PHY(name, MV88E61XX_GLB2REG_DEVADR, - MV88E61XX_PHY_CMD, (u16 *) & reg); + MV88E61XX_PHY_CMD, ®); if (timeout-- == 0) { printf("SMI busy timeout\n"); return -1; -- cgit v1.1 From 7194ab809532eeca3e2ee5dc12017cb901cc5842 Mon Sep 17 00:00:00 2001 From: Ben Warren Date: Sun, 4 Oct 2009 22:37:03 -0700 Subject: Convert SMC91111 Ethernet driver to CONFIG_NET_MULTI API All in-tree boards that use this controller have CONFIG_NET_MULTI added Also: - changed CONFIG_DRIVER_SMC91111 to CONFIG_SMC91111 - cleaned up line lengths - modified all boards that override weak function in this driver - modified all eeprom standalone apps to work with new driver - updated blackfin standalone EEPROM app after testing Signed-off-by: Ben Warren Signed-off-by: Mike Frysinger --- drivers/net/Makefile | 2 +- drivers/net/smc91111.c | 611 +++++++++++++++++-------------------------------- drivers/net/smc91111.h | 192 ++++++++-------- 3 files changed, 309 insertions(+), 496 deletions(-) (limited to 'drivers') diff --git a/drivers/net/Makefile b/drivers/net/Makefile index be5c484..fc9887b 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -64,7 +64,7 @@ COBJS-$(CONFIG_RTL8139) += rtl8139.o COBJS-$(CONFIG_RTL8169) += rtl8169.o COBJS-$(CONFIG_DRIVER_S3C4510_ETH) += s3c4510b_eth.o COBJS-$(CONFIG_SH_ETHER) += sh_eth.o -COBJS-$(CONFIG_DRIVER_SMC91111) += smc91111.o +COBJS-$(CONFIG_SMC91111) += smc91111.o COBJS-$(CONFIG_SMC911X) += smc911x.o COBJS-$(CONFIG_TIGON3) += tigon3.o bcm570x_autoneg.o 5701rls.o COBJS-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o diff --git a/drivers/net/smc91111.c b/drivers/net/smc91111.c index b41e4d2..54a1bfb 100644 --- a/drivers/net/smc91111.c +++ b/drivers/net/smc91111.c @@ -62,6 +62,7 @@ #include #include #include +#include #include "smc91111.h" #include @@ -122,17 +123,15 @@ static const char version[] = . what you are doing. . -------------------------------------------------------------------------*/ -#define CARDNAME "LAN91C111" /* Memory sizing constant */ #define LAN91C111_MEMORY_MULTIPLIER (1024*2) #ifndef CONFIG_SMC91111_BASE -#define CONFIG_SMC91111_BASE 0x20000300 +#error "SMC91111 Base address must be passed to initialization funciton" +/* #define CONFIG_SMC91111_BASE 0x20000300 */ #endif -#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE - #define SMC_DEV_NAME "SMC91111" #define SMC_PHY_ADDR 0x0000 #define SMC_ALLOC_MAX_TRY 5 @@ -147,73 +146,18 @@ static const char version[] = #else #undef USE_32_BIT #endif -/*----------------------------------------------------------------- - . - . The driver can be entered at any of the following entry points. - . - .------------------------------------------------------------------ */ - -extern int eth_init(bd_t *bd); -extern void eth_halt(void); -extern int eth_rx(void); -extern int eth_send(volatile void *packet, int length); #ifdef SHARED_RESOURCES - extern void swap_to(int device_id); +extern void swap_to(int device_id); +#else +# define swap_to(x) #endif -/* - . This is called by register_netdev(). It is responsible for - . checking the portlist for the SMC9000 series chipset. If it finds - . one, then it will initialize the device, find the hardware information, - . and sets up the appropriate device parameters. - . NOTE: Interrupts are *OFF* when this procedure is called. - . - . NB:This shouldn't be static since it is referred to externally. -*/ -int smc_init(void); - -/* - . This is called by unregister_netdev(). It is responsible for - . cleaning up before the driver is finally unregistered and discarded. -*/ -void smc_destructor(void); - -/* - . The kernel calls this function when someone wants to use the device, - . typically 'ifconfig ethX up'. -*/ -static int smc_open(bd_t *bd); - - -/* - . This is called by the kernel in response to 'ifconfig ethX down'. It - . is responsible for cleaning up everything that the open routine - . does, and maybe putting the card into a powerdown state. -*/ -static int smc_close(void); - -/* - . Configures the PHY through the MII Management interface -*/ #ifndef CONFIG_SMC91111_EXT_PHY -static void smc_phy_configure(void); +static void smc_phy_configure(struct eth_device *dev); #endif /* !CONFIG_SMC91111_EXT_PHY */ /* - . This is a separate procedure to handle the receipt of a packet, to - . leave the interrupt code looking slightly cleaner -*/ -static int smc_rcv(void); - -/* See if a MAC address is defined in the current environment. If so use it. If not - . print a warning and set the environment and other globals with the default. - . If an EEPROM is present it really should be consulted. -*/ -int smc_get_ethaddr(bd_t *bd); -int get_rom_mac(uchar *v_rom_mac); - -/* ------------------------------------------------------------ . . Internal routines @@ -233,125 +177,69 @@ int get_rom_mac(uchar *v_rom_mac); * packets being corrupt (shifted) on the wire, etc. Switching to the * inx,outx functions fixed this problem. */ -static inline word SMC_inw(dword offset); -static inline void SMC_outw(word value, dword offset); -static inline byte SMC_inb(dword offset); -static inline void SMC_outb(byte value, dword offset); -static inline void SMC_insw(dword offset, volatile uchar* buf, dword len); -static inline void SMC_outsw(dword offset, uchar* buf, dword len); #define barrier() __asm__ __volatile__("": : :"memory") -static inline word SMC_inw(dword offset) +static inline word SMC_inw(struct eth_device *dev, dword offset) { word v; - v = *((volatile word*)(SMC_BASE_ADDRESS+offset)); + v = *((volatile word*)(dev->iobase + offset)); barrier(); *(volatile u32*)(0xc0000000); return v; } -static inline void SMC_outw(word value, dword offset) +static inline void SMC_outw(struct eth_device *dev, word value, dword offset) { - *((volatile word*)(SMC_BASE_ADDRESS+offset)) = value; + *((volatile word*)(dev->iobase + offset)) = value; barrier(); *(volatile u32*)(0xc0000000); } -static inline byte SMC_inb(dword offset) +static inline byte SMC_inb(struct eth_device *dev, dword offset) { word _w; - _w = SMC_inw(offset & ~((dword)1)); + _w = SMC_inw(dev, offset & ~((dword)1)); return (offset & 1) ? (byte)(_w >> 8) : (byte)(_w); } -static inline void SMC_outb(byte value, dword offset) +static inline void SMC_outb(struct eth_device *dev, byte value, dword offset) { word _w; - _w = SMC_inw(offset & ~((dword)1)); + _w = SMC_inw(dev, offset & ~((dword)1)); if (offset & 1) - *((volatile word*)(SMC_BASE_ADDRESS+(offset & ~((dword)1)))) = (value<<8) | (_w & 0x00ff); + *((volatile word*)(dev->iobase + (offset & ~((dword)1)))) = + (value<<8) | (_w & 0x00ff); else - *((volatile word*)(SMC_BASE_ADDRESS+offset)) = value | (_w & 0xff00); + *((volatile word*)(dev->iobase + offset)) = + value | (_w & 0xff00); } -static inline void SMC_insw(dword offset, volatile uchar* buf, dword len) +static inline void SMC_insw(struct eth_device *dev, dword offset, + volatile uchar* buf, dword len) { volatile word *p = (volatile word *)buf; while (len-- > 0) { - *p++ = SMC_inw(offset); + *p++ = SMC_inw(dev, offset); barrier(); *((volatile u32*)(0xc0000000)); } } -static inline void SMC_outsw(dword offset, uchar* buf, dword len) +static inline void SMC_outsw(struct eth_device *dev, dword offset, + uchar* buf, dword len) { volatile word *p = (volatile word *)buf; while (len-- > 0) { - SMC_outw(*p++, offset); + SMC_outw(dev, *p++, offset); barrier(); *(volatile u32*)(0xc0000000); } } #endif /* CONFIG_SMC_USE_IOFUNCS */ -static char unsigned smc_mac_addr[6] = {0x02, 0x80, 0xad, 0x20, 0x31, 0xb8}; - -/* - * This function must be called before smc_open() if you want to override - * the default mac address. - */ - -void smc_set_mac_addr(const unsigned char *addr) { - int i; - - for (i=0; i < sizeof(smc_mac_addr); i++){ - smc_mac_addr[i] = addr[i]; - } -} - -/* - * smc_get_macaddr is no longer used. If you want to override the default - * mac address, call smc_get_mac_addr as a part of the board initialization. - */ - -#if 0 -void smc_get_macaddr( byte *addr ) { - /* MAC ADDRESS AT FLASHBLOCK 1 / OFFSET 0x10 */ - unsigned char *dnp1110_mac = (unsigned char *) (0xE8000000 + 0x20010); - int i; - - - for (i=0; i<6; i++) { - addr[0] = *(dnp1110_mac+0); - addr[1] = *(dnp1110_mac+1); - addr[2] = *(dnp1110_mac+2); - addr[3] = *(dnp1110_mac+3); - addr[4] = *(dnp1110_mac+4); - addr[5] = *(dnp1110_mac+5); - } -} -#endif /* 0 */ - -/*********************************************** - * Show available memory * - ***********************************************/ -void dump_memory_info(void) -{ - word mem_info; - word old_bank; - - old_bank = SMC_inw(BANK_SELECT)&0xF; - - SMC_SELECT_BANK(0); - mem_info = SMC_inw( MIR_REG ); - PRINTK2("Memory: %4d available\n", (mem_info >> 8)*2048); - - SMC_SELECT_BANK(old_bank); -} /* . A rather simple routine to print out a packet for debugging purposes. */ @@ -361,35 +249,15 @@ static void print_packet( byte *, int ); #define tx_done(dev) 1 - -/* this does a soft reset on the device */ -static void smc_reset( void ); - -/* Enable Interrupts, Receive, and Transmit */ -static void smc_enable( void ); - -/* this puts the device in an inactive state */ -static void smc_shutdown( void ); - -/* Routines to Read and Write the PHY Registers across the - MII Management Interface -*/ - -#ifndef CONFIG_SMC91111_EXT_PHY -static word smc_read_phy_register(byte phyreg); -static void smc_write_phy_register(byte phyreg, word phydata); -#endif /* !CONFIG_SMC91111_EXT_PHY */ - - -static int poll4int (byte mask, int timeout) +static int poll4int (struct eth_device *dev, byte mask, int timeout) { int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ; int is_timeout = 0; - word old_bank = SMC_inw (BSR_REG); + word old_bank = SMC_inw (dev, BSR_REG); PRINTK2 ("Polling...\n"); - SMC_SELECT_BANK (2); - while ((SMC_inw (SMC91111_INT_REG) & mask) == 0) { + SMC_SELECT_BANK (dev, 2); + while ((SMC_inw (dev, SMC91111_INT_REG) & mask) == 0) { if (get_timer (0) >= tmo) { is_timeout = 1; break; @@ -397,7 +265,7 @@ static int poll4int (byte mask, int timeout) } /* restore old bank selection */ - SMC_SELECT_BANK (old_bank); + SMC_SELECT_BANK (dev, old_bank); if (is_timeout) return 1; @@ -406,12 +274,12 @@ static int poll4int (byte mask, int timeout) } /* Only one release command at a time, please */ -static inline void smc_wait_mmu_release_complete (void) +static inline void smc_wait_mmu_release_complete (struct eth_device *dev) { int count = 0; /* assume bank 2 selected */ - while (SMC_inw (MMU_CMD_REG) & MC_BUSY) { + while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { udelay (1); /* Wait until not busy */ if (++count > 200) break; @@ -435,49 +303,50 @@ static inline void smc_wait_mmu_release_complete (void) . 5. clear all interrupts . */ -static void smc_reset (void) +static void smc_reset (struct eth_device *dev) { PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME); /* This resets the registers mostly to defaults, but doesn't affect EEPROM. That seems unnecessary */ - SMC_SELECT_BANK (0); - SMC_outw (RCR_SOFTRST, RCR_REG); + SMC_SELECT_BANK (dev, 0); + SMC_outw (dev, RCR_SOFTRST, RCR_REG); /* Setup the Configuration Register */ /* This is necessary because the CONFIG_REG is not affected */ /* by a soft reset */ - SMC_SELECT_BANK (1); + SMC_SELECT_BANK (dev, 1); #if defined(CONFIG_SMC91111_EXT_PHY) - SMC_outw (CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG); + SMC_outw (dev, CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG); #else - SMC_outw (CONFIG_DEFAULT, CONFIG_REG); + SMC_outw (dev, CONFIG_DEFAULT, CONFIG_REG); #endif /* Release from possible power-down state */ /* Configuration register is not affected by Soft Reset */ - SMC_outw (SMC_inw (CONFIG_REG) | CONFIG_EPH_POWER_EN, CONFIG_REG); + SMC_outw (dev, SMC_inw (dev, CONFIG_REG) | CONFIG_EPH_POWER_EN, + CONFIG_REG); - SMC_SELECT_BANK (0); + SMC_SELECT_BANK (dev, 0); /* this should pause enough for the chip to be happy */ udelay (10); /* Disable transmit and receive functionality */ - SMC_outw (RCR_CLEAR, RCR_REG); - SMC_outw (TCR_CLEAR, TCR_REG); + SMC_outw (dev, RCR_CLEAR, RCR_REG); + SMC_outw (dev, TCR_CLEAR, TCR_REG); /* set the control register */ - SMC_SELECT_BANK (1); - SMC_outw (CTL_DEFAULT, CTL_REG); + SMC_SELECT_BANK (dev, 1); + SMC_outw (dev, CTL_DEFAULT, CTL_REG); /* Reset the MMU */ - SMC_SELECT_BANK (2); - smc_wait_mmu_release_complete (); - SMC_outw (MC_RESET, MMU_CMD_REG); - while (SMC_inw (MMU_CMD_REG) & MC_BUSY) + SMC_SELECT_BANK (dev, 2); + smc_wait_mmu_release_complete (dev); + SMC_outw (dev, MC_RESET, MMU_CMD_REG); + while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) udelay (1); /* Wait until not busy */ /* Note: It doesn't seem that waiting for the MMU busy is needed here, @@ -485,7 +354,7 @@ static void smc_reset (void) of issuing another MMU command right after this */ /* Disable all interrupts */ - SMC_outb (0, IM_REG); + SMC_outb (dev, 0, IM_REG); } /* @@ -496,20 +365,20 @@ static void smc_reset (void) . 2. Enable the receiver . 3. Enable interrupts */ -static void smc_enable() +static void smc_enable(struct eth_device *dev) { PRINTK2("%s: smc_enable\n", SMC_DEV_NAME); - SMC_SELECT_BANK( 0 ); + SMC_SELECT_BANK( dev, 0 ); /* see the header file for options in TCR/RCR DEFAULT*/ - SMC_outw( TCR_DEFAULT, TCR_REG ); - SMC_outw( RCR_DEFAULT, RCR_REG ); + SMC_outw( dev, TCR_DEFAULT, TCR_REG ); + SMC_outw( dev, RCR_DEFAULT, RCR_REG ); /* clear MII_DIS */ /* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */ } /* - . Function: smc_shutdown + . Function: smc_halt . Purpose: closes down the SMC91xxx chip. . Method: . 1. zero the interrupt mask @@ -522,26 +391,25 @@ static void smc_enable() . the manual says that it will wake up in response to any I/O requests . in the register space. Empirical results do not show this working. */ -static void smc_shutdown() +static void smc_halt(struct eth_device *dev) { - PRINTK2(CARDNAME ": smc_shutdown\n"); + PRINTK2("%s: smc_halt\n", SMC_DEV_NAME); /* no more interrupts for me */ - SMC_SELECT_BANK( 2 ); - SMC_outb( 0, IM_REG ); + SMC_SELECT_BANK( dev, 2 ); + SMC_outb( dev, 0, IM_REG ); /* and tell the card to stay away from that nasty outside world */ - SMC_SELECT_BANK( 0 ); - SMC_outb( RCR_CLEAR, RCR_REG ); - SMC_outb( TCR_CLEAR, TCR_REG ); -#ifdef SHARED_RESOURCES + SMC_SELECT_BANK( dev, 0 ); + SMC_outb( dev, RCR_CLEAR, RCR_REG ); + SMC_outb( dev, TCR_CLEAR, TCR_REG ); + swap_to(FLASH); -#endif } /* - . Function: smc_hardware_send_packet(struct net_device * ) + . Function: smc_send(struct net_device * ) . Purpose: . This sends the actual packet to the SMC9xxx chip. . @@ -558,10 +426,10 @@ static void smc_shutdown() . Enable the transmit interrupt, so I know if it failed . Free the kernel data if I actually sent it. */ -static int smc_send_packet (volatile void *packet, int packet_length) +static int smc_send(struct eth_device *dev, volatile void *packet, + int packet_length) { byte packet_no; - unsigned long ioaddr; byte *buf; int length; int numPages; @@ -572,9 +440,9 @@ static int smc_send_packet (volatile void *packet, int packet_length) word saved_ptr; /* save PTR and PNR registers before manipulation */ - SMC_SELECT_BANK (2); - saved_pnr = SMC_inb( PN_REG ); - saved_ptr = SMC_inw( PTR_REG ); + SMC_SELECT_BANK (dev, 2); + saved_pnr = SMC_inb( dev, PN_REG ); + saved_ptr = SMC_inw( dev, PTR_REG ); PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME); @@ -601,8 +469,8 @@ static int smc_send_packet (volatile void *packet, int packet_length) } /* now, try to allocate the memory */ - SMC_SELECT_BANK (2); - SMC_outw (MC_ALLOC | numPages, MMU_CMD_REG); + SMC_SELECT_BANK (dev, 2); + SMC_outw (dev, MC_ALLOC | numPages, MMU_CMD_REG); /* FIXME: the ALLOC_INT bit never gets set * * so the following will always give a * @@ -615,10 +483,10 @@ again: try++; time_out = MEMORY_WAIT_TIME; do { - status = SMC_inb (SMC91111_INT_REG); + status = SMC_inb (dev, SMC91111_INT_REG); if (status & IM_ALLOC_INT) { /* acknowledge the interrupt */ - SMC_outb (IM_ALLOC_INT, SMC91111_INT_REG); + SMC_outb (dev, IM_ALLOC_INT, SMC91111_INT_REG); break; } } while (--time_out); @@ -635,14 +503,10 @@ again: PRINTK2 ("%s: memory allocation, try %d succeeded ...\n", SMC_DEV_NAME, try); - /* I can send the packet now.. */ - - ioaddr = SMC_BASE_ADDRESS; - buf = (byte *) packet; /* If I get here, I _know_ there is a packet slot waiting for me */ - packet_no = SMC_inb (AR_REG); + packet_no = SMC_inb (dev, AR_REG); if (packet_no & AR_FAILED) { /* or isn't there? BAD CHIP! */ printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME); @@ -651,20 +515,20 @@ again: /* we have a packet address, so tell the card to use it */ #ifndef CONFIG_XAENIAX - SMC_outb (packet_no, PN_REG); + SMC_outb (dev, packet_no, PN_REG); #else /* On Xaeniax board, we can't use SMC_outb here because that way * the Allocate MMU command will end up written to the command register * as well, which will lead to a problem. */ - SMC_outl (packet_no << 16, 0); + SMC_outl (dev, packet_no << 16, 0); #endif /* do not write new ptr value if Write data fifo not empty */ while ( saved_ptr & PTR_NOTEMPTY ) printf ("Write data fifo not empty!\n"); /* point to the beginning of the packet */ - SMC_outw (PTR_AUTOINC, PTR_REG); + SMC_outw (dev, PTR_AUTOINC, PTR_REG); PRINTK3 ("%s: Trying to xmit packet of length %x\n", SMC_DEV_NAME, length); @@ -677,11 +541,11 @@ again: /* send the packet length ( +6 for status, length and ctl byte ) and the status word ( set to zeros ) */ #ifdef USE_32_BIT - SMC_outl ((length + 6) << 16, SMC91111_DATA_REG); + SMC_outl (dev, (length + 6) << 16, SMC91111_DATA_REG); #else - SMC_outw (0, SMC91111_DATA_REG); + SMC_outw (dev, 0, SMC91111_DATA_REG); /* send the packet length ( +6 for status words, length, and ctl */ - SMC_outw ((length + 6), SMC91111_DATA_REG); + SMC_outw (dev, (length + 6), SMC91111_DATA_REG); #endif /* send the actual data @@ -692,10 +556,10 @@ again: . almost as much time as is saved? */ #ifdef USE_32_BIT - SMC_outsl (SMC91111_DATA_REG, buf, length >> 2); + SMC_outsl (dev, SMC91111_DATA_REG, buf, length >> 2); #ifndef CONFIG_XAENIAX if (length & 0x2) - SMC_outw (*((word *) (buf + (length & 0xFFFFFFFC))), + SMC_outw (dev, *((word *) (buf + (length & 0xFFFFFFFC))), SMC91111_DATA_REG); #else /* On XANEIAX, we can only use 32-bit writes, so we need to handle @@ -703,48 +567,48 @@ again: */ if ((length & 3) == 3) { u16 * ptr = (u16*) &buf[length-3]; - SMC_outl((*ptr) | ((0x2000 | buf[length-1]) << 16), + SMC_outl(dev, (*ptr) | ((0x2000 | buf[length-1]) << 16), SMC91111_DATA_REG); } else if ((length & 2) == 2) { u16 * ptr = (u16*) &buf[length-2]; - SMC_outl(*ptr, SMC91111_DATA_REG); + SMC_outl(dev, *ptr, SMC91111_DATA_REG); } else if (length & 1) { - SMC_outl((0x2000 | buf[length-1]), SMC91111_DATA_REG); + SMC_outl(dev, (0x2000 | buf[length-1]), SMC91111_DATA_REG); } else { - SMC_outl(0, SMC91111_DATA_REG); + SMC_outl(dev, 0, SMC91111_DATA_REG); } #endif #else - SMC_outsw (SMC91111_DATA_REG, buf, (length) >> 1); + SMC_outsw (dev, SMC91111_DATA_REG, buf, (length) >> 1); #endif /* USE_32_BIT */ #ifndef CONFIG_XAENIAX /* Send the last byte, if there is one. */ if ((length & 1) == 0) { - SMC_outw (0, SMC91111_DATA_REG); + SMC_outw (dev, 0, SMC91111_DATA_REG); } else { - SMC_outw (buf[length - 1] | 0x2000, SMC91111_DATA_REG); + SMC_outw (dev, buf[length - 1] | 0x2000, SMC91111_DATA_REG); } #endif /* and let the chipset deal with it */ - SMC_outw (MC_ENQUEUE, MMU_CMD_REG); + SMC_outw (dev, MC_ENQUEUE, MMU_CMD_REG); /* poll for TX INT */ - /* if (poll4int (IM_TX_INT, SMC_TX_TIMEOUT)) { */ + /* if (poll4int (dev, IM_TX_INT, SMC_TX_TIMEOUT)) { */ /* poll for TX_EMPTY INT - autorelease enabled */ - if (poll4int(IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) { + if (poll4int(dev, IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) { /* sending failed */ PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME); /* release packet */ /* no need to release, MMU does that now */ #ifdef CONFIG_XAENIAX - SMC_outw (MC_FREEPKT, MMU_CMD_REG); + SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG); #endif /* wait for MMU getting ready (low) */ - while (SMC_inw (MMU_CMD_REG) & MC_BUSY) { + while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { udelay (10); } @@ -754,7 +618,7 @@ again: return 0; } else { /* ack. int */ - SMC_outb (IM_TX_EMPTY_INT, SMC91111_INT_REG); + SMC_outb (dev, IM_TX_EMPTY_INT, SMC91111_INT_REG); /* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */ PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME, length); @@ -762,11 +626,11 @@ again: /* release packet */ /* no need to release, MMU does that now */ #ifdef CONFIG_XAENIAX - SMC_outw (MC_FREEPKT, MMU_CMD_REG); + SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG); #endif /* wait for MMU getting ready (low) */ - while (SMC_inw (MMU_CMD_REG) & MC_BUSY) { + while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { udelay (10); } @@ -777,78 +641,62 @@ again: /* restore previously saved registers */ #ifndef CONFIG_XAENIAX - SMC_outb( saved_pnr, PN_REG ); + SMC_outb( dev, saved_pnr, PN_REG ); #else /* On Xaeniax board, we can't use SMC_outb here because that way * the Allocate MMU command will end up written to the command register * as well, which will lead to a problem. */ - SMC_outl(saved_pnr << 16, 0); + SMC_outl(dev, saved_pnr << 16, 0); #endif - SMC_outw( saved_ptr, PTR_REG ); + SMC_outw( dev, saved_ptr, PTR_REG ); return length; } -/*------------------------------------------------------------------------- - | - | smc_destructor( struct net_device * dev ) - | Input parameters: - | dev, pointer to the device structure - | - | Output: - | None. - | - --------------------------------------------------------------------------- -*/ -void smc_destructor() -{ - PRINTK2(CARDNAME ": smc_destructor\n"); -} - - /* * Open and Initialize the board * * Set up everything, reset the card, etc .. * */ -static int smc_open (bd_t * bd) +static int smc_init(struct eth_device *dev, bd_t *bd) { - int i, err; + int i; - PRINTK2 ("%s: smc_open\n", SMC_DEV_NAME); + swap_to(ETHERNET); + + PRINTK2 ("%s: smc_init\n", SMC_DEV_NAME); /* reset the hardware */ - smc_reset (); - smc_enable (); + smc_reset (dev); + smc_enable (dev); /* Configure the PHY */ #ifndef CONFIG_SMC91111_EXT_PHY - smc_phy_configure (); + smc_phy_configure (dev); #endif /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */ -/* SMC_SELECT_BANK(0); */ -/* SMC_outw(0, RPC_REG); */ - SMC_SELECT_BANK (1); +/* SMC_SELECT_BANK(dev, 0); */ +/* SMC_outw(dev, 0, RPC_REG); */ + SMC_SELECT_BANK (dev, 1); - err = smc_get_ethaddr (bd); /* set smc_mac_addr, and sync it with u-boot globals */ - if (err < 0) - return -1; #ifdef USE_32_BIT for (i = 0; i < 6; i += 2) { word address; - address = smc_mac_addr[i + 1] << 8; - address |= smc_mac_addr[i]; - SMC_outw (address, (ADDR0_REG + i)); + address = dev->enetaddr[i + 1] << 8; + address |= dev->enetaddr[i]; + SMC_outw(dev, address, (ADDR0_REG + i)); } #else for (i = 0; i < 6; i++) - SMC_outb (smc_mac_addr[i], (ADDR0_REG + i)); + SMC_outb(dev, dev->enetaddr[i], (ADDR0_REG + i)); #endif + printf(SMC_DEV_NAME ": MAC %pM\n", dev->enetaddr); + return 0; } @@ -864,7 +712,7 @@ static int smc_open (bd_t * bd) . o otherwise, read in the packet -------------------------------------------------------------- */ -static int smc_rcv() +static int smc_rcv(struct eth_device *dev) { int packet_number; word status; @@ -876,12 +724,12 @@ static int smc_rcv() byte saved_pnr; word saved_ptr; - SMC_SELECT_BANK(2); + SMC_SELECT_BANK(dev, 2); /* save PTR and PTR registers */ - saved_pnr = SMC_inb( PN_REG ); - saved_ptr = SMC_inw( PTR_REG ); + saved_pnr = SMC_inb( dev, PN_REG ); + saved_ptr = SMC_inw( dev, PTR_REG ); - packet_number = SMC_inw( RXFIFO_REG ); + packet_number = SMC_inw( dev, RXFIFO_REG ); if ( packet_number & RXFIFO_REMPTY ) { @@ -890,16 +738,16 @@ static int smc_rcv() PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME); /* start reading from the start of the packet */ - SMC_outw( PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG ); + SMC_outw( dev, PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG ); /* First two words are status and packet_length */ #ifdef USE_32_BIT - stat_len = SMC_inl(SMC91111_DATA_REG); + stat_len = SMC_inl(dev, SMC91111_DATA_REG); status = stat_len & 0xffff; packet_length = stat_len >> 16; #else - status = SMC_inw( SMC91111_DATA_REG ); - packet_length = SMC_inw( SMC91111_DATA_REG ); + status = SMC_inw( dev, SMC91111_DATA_REG ); + packet_length = SMC_inw( dev, SMC91111_DATA_REG ); #endif packet_length &= 0x07ff; /* mask off top bits */ @@ -923,20 +771,23 @@ static int smc_rcv() to send the DWORDs or the bytes first, or some mixture. A mixture might improve already slow PIO performance */ - SMC_insl( SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 2 ); + SMC_insl( dev, SMC91111_DATA_REG, NetRxPackets[0], + packet_length >> 2 ); /* read the left over bytes */ if (packet_length & 3) { int i; - byte *tail = (byte *)(NetRxPackets[0] + (packet_length & ~3)); - dword leftover = SMC_inl(SMC91111_DATA_REG); + byte *tail = (byte *)(NetRxPackets[0] + + (packet_length & ~3)); + dword leftover = SMC_inl(dev, SMC91111_DATA_REG); for (i=0; i<(packet_length & 3); i++) *tail++ = (byte) (leftover >> (8*i)) & 0xff; } #else PRINTK3(" Reading %d words and %d byte(s) \n", (packet_length >> 1 ), packet_length & 1 ); - SMC_insw(SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 1); + SMC_insw(dev, SMC91111_DATA_REG , NetRxPackets[0], + packet_length >> 1); #endif /* USE_32_BIT */ @@ -950,26 +801,26 @@ static int smc_rcv() is_error = 1; } - while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY ) + while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY ) udelay(1); /* Wait until not busy */ /* error or good, tell the card to get rid of this packet */ - SMC_outw( MC_RELEASE, MMU_CMD_REG ); + SMC_outw( dev, MC_RELEASE, MMU_CMD_REG ); - while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY ) + while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY ) udelay(1); /* Wait until not busy */ /* restore saved registers */ #ifndef CONFIG_XAENIAX - SMC_outb( saved_pnr, PN_REG ); + SMC_outb( dev, saved_pnr, PN_REG ); #else /* On Xaeniax board, we can't use SMC_outb here because that way * the Allocate MMU command will end up written to the command register * as well, which will lead to a problem. */ - SMC_outl( saved_pnr << 16, 0); + SMC_outl( dev, saved_pnr << 16, 0); #endif - SMC_outw( saved_ptr, PTR_REG ); + SMC_outw( dev, saved_ptr, PTR_REG ); if (!is_error) { /* Pass the packet up to the protocol layers. */ @@ -982,43 +833,24 @@ static int smc_rcv() } -/*---------------------------------------------------- - . smc_close - . - . this makes the board clean up everything that it can - . and not talk to the outside world. Caused by - . an 'ifconfig ethX down' - . - -----------------------------------------------------*/ -static int smc_close() -{ - PRINTK2("%s: smc_close\n", SMC_DEV_NAME); - - /* clear everything */ - smc_shutdown(); - - return 0; -} - - #if 0 /*------------------------------------------------------------ . Modify a bit in the LAN91C111 register set .-------------------------------------------------------------*/ -static word smc_modify_regbit(int bank, int ioaddr, int reg, +static word smc_modify_regbit(struct eth_device *dev, int bank, int ioaddr, int reg, unsigned int bit, int val) { word regval; - SMC_SELECT_BANK( bank ); + SMC_SELECT_BANK( dev, bank ); - regval = SMC_inw( reg ); + regval = SMC_inw( dev, reg ); if (val) regval |= bit; else regval &= ~bit; - SMC_outw( regval, 0 ); + SMC_outw( dev, regval, 0 ); return(regval); } @@ -1026,10 +858,10 @@ static word smc_modify_regbit(int bank, int ioaddr, int reg, /*------------------------------------------------------------ . Retrieve a bit in the LAN91C111 register set .-------------------------------------------------------------*/ -static int smc_get_regbit(int bank, int ioaddr, int reg, unsigned int bit) +static int smc_get_regbit(struct eth_device *dev, int bank, int ioaddr, int reg, unsigned int bit) { - SMC_SELECT_BANK( bank ); - if ( SMC_inw( reg ) & bit) + SMC_SELECT_BANK( dev, bank ); + if ( SMC_inw( dev, reg ) & bit) return(1); else return(0); @@ -1039,20 +871,20 @@ static int smc_get_regbit(int bank, int ioaddr, int reg, unsigned int bit) /*------------------------------------------------------------ . Modify a LAN91C111 register (word access only) .-------------------------------------------------------------*/ -static void smc_modify_reg(int bank, int ioaddr, int reg, word val) +static void smc_modify_reg(struct eth_device *dev, int bank, int ioaddr, int reg, word val) { - SMC_SELECT_BANK( bank ); - SMC_outw( val, reg ); + SMC_SELECT_BANK( dev, bank ); + SMC_outw( dev, val, reg ); } /*------------------------------------------------------------ . Retrieve a LAN91C111 register (word access only) .-------------------------------------------------------------*/ -static int smc_get_reg(int bank, int ioaddr, int reg) +static int smc_get_reg(struct eth_device *dev, int bank, int ioaddr, int reg) { - SMC_SELECT_BANK( bank ); - return(SMC_inw( reg )); + SMC_SELECT_BANK( dev, bank ); + return(SMC_inw( dev, reg )); } #endif /* 0 */ @@ -1105,7 +937,7 @@ static void smc_dump_mii_stream (byte * bits, int size) . Reads a register from the MII Management serial interface .-------------------------------------------------------------*/ #ifndef CONFIG_SMC91111_EXT_PHY -static word smc_read_phy_register (byte phyreg) +static word smc_read_phy_register (struct eth_device *dev, byte phyreg) { int oldBank; int i; @@ -1168,13 +1000,13 @@ static word smc_read_phy_register (byte phyreg) bits[clk_idx++] = 0; /* Save the current bank */ - oldBank = SMC_inw (BANK_SELECT); + oldBank = SMC_inw (dev, BANK_SELECT); /* Select bank 3 */ - SMC_SELECT_BANK (3); + SMC_SELECT_BANK (dev, 3); /* Get the current MII register value */ - mii_reg = SMC_inw (MII_REG); + mii_reg = SMC_inw (dev, MII_REG); /* Turn off all MII Interface bits */ mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO); @@ -1182,23 +1014,23 @@ static word smc_read_phy_register (byte phyreg) /* Clock all 64 cycles */ for (i = 0; i < sizeof bits; ++i) { /* Clock Low - output data */ - SMC_outw (mii_reg | bits[i], MII_REG); + SMC_outw (dev, mii_reg | bits[i], MII_REG); udelay (SMC_PHY_CLOCK_DELAY); /* Clock Hi - input data */ - SMC_outw (mii_reg | bits[i] | MII_MCLK, MII_REG); + SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG); udelay (SMC_PHY_CLOCK_DELAY); - bits[i] |= SMC_inw (MII_REG) & MII_MDI; + bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI; } /* Return to idle state */ /* Set clock to low, data to low, and output tristated */ - SMC_outw (mii_reg, MII_REG); + SMC_outw (dev, mii_reg, MII_REG); udelay (SMC_PHY_CLOCK_DELAY); /* Restore original bank select */ - SMC_SELECT_BANK (oldBank); + SMC_SELECT_BANK (dev, oldBank); /* Recover input data */ phydata = 0; @@ -1222,7 +1054,8 @@ static word smc_read_phy_register (byte phyreg) /*------------------------------------------------------------ . Writes a register to the MII Management serial interface .-------------------------------------------------------------*/ -static void smc_write_phy_register (byte phyreg, word phydata) +static void smc_write_phy_register (struct eth_device *dev, byte phyreg, + word phydata) { int oldBank; int i; @@ -1288,13 +1121,13 @@ static void smc_write_phy_register (byte phyreg, word phydata) bits[clk_idx++] = 0; /* Save the current bank */ - oldBank = SMC_inw (BANK_SELECT); + oldBank = SMC_inw (dev, BANK_SELECT); /* Select bank 3 */ - SMC_SELECT_BANK (3); + SMC_SELECT_BANK (dev, 3); /* Get the current MII register value */ - mii_reg = SMC_inw (MII_REG); + mii_reg = SMC_inw (dev, MII_REG); /* Turn off all MII Interface bits */ mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO); @@ -1302,23 +1135,23 @@ static void smc_write_phy_register (byte phyreg, word phydata) /* Clock all cycles */ for (i = 0; i < sizeof bits; ++i) { /* Clock Low - output data */ - SMC_outw (mii_reg | bits[i], MII_REG); + SMC_outw (dev, mii_reg | bits[i], MII_REG); udelay (SMC_PHY_CLOCK_DELAY); /* Clock Hi - input data */ - SMC_outw (mii_reg | bits[i] | MII_MCLK, MII_REG); + SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG); udelay (SMC_PHY_CLOCK_DELAY); - bits[i] |= SMC_inw (MII_REG) & MII_MDI; + bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI; } /* Return to idle state */ /* Set clock to low, data to low, and output tristated */ - SMC_outw (mii_reg, MII_REG); + SMC_outw (dev, mii_reg, MII_REG); udelay (SMC_PHY_CLOCK_DELAY); /* Restore original bank select */ - SMC_SELECT_BANK (oldBank); + SMC_SELECT_BANK (dev, oldBank); #if (SMC_DEBUG > 2 ) printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n", @@ -1345,7 +1178,7 @@ static void smc_wait_ms(unsigned int ms) . smc_phy_fixed() if the user has requested a certain config. .-------------------------------------------------------------*/ #ifndef CONFIG_SMC91111_EXT_PHY -static void smc_phy_configure () +static void smc_phy_configure (struct eth_device *dev) { int timeout; byte phyaddr; @@ -1361,12 +1194,12 @@ static void smc_phy_configure () phyaddr = SMC_PHY_ADDR; /* Reset the PHY, setting all other bits to zero */ - smc_write_phy_register (PHY_CNTL_REG, PHY_CNTL_RST); + smc_write_phy_register (dev, PHY_CNTL_REG, PHY_CNTL_RST); /* Wait for the reset to complete, or time out */ timeout = 6; /* Wait up to 3 seconds */ while (timeout--) { - if (!(smc_read_phy_register (PHY_CNTL_REG) + if (!(smc_read_phy_register (dev, PHY_CNTL_REG) & PHY_CNTL_RST)) { /* reset complete */ break; @@ -1385,14 +1218,14 @@ static void smc_phy_configure () /* Enable PHY Interrupts (for register 18) */ /* Interrupts listed here are disabled */ - smc_write_phy_register (PHY_MASK_REG, 0xffff); + smc_write_phy_register (dev, PHY_MASK_REG, 0xffff); /* Configure the Receive/Phy Control register */ - SMC_SELECT_BANK (0); - SMC_outw (RPC_DEFAULT, RPC_REG); + SMC_SELECT_BANK (dev, 0); + SMC_outw (dev, RPC_DEFAULT, RPC_REG); /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */ - my_phy_caps = smc_read_phy_register (PHY_STAT_REG); + my_phy_caps = smc_read_phy_register (dev, PHY_STAT_REG); my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */ if (my_phy_caps & PHY_STAT_CAP_T4) @@ -1411,18 +1244,18 @@ static void smc_phy_configure () my_ad_caps |= PHY_AD_10_HDX; /* Update our Auto-Neg Advertisement Register */ - smc_write_phy_register (PHY_AD_REG, my_ad_caps); + smc_write_phy_register (dev, PHY_AD_REG, my_ad_caps); /* Read the register back. Without this, it appears that when */ /* auto-negotiation is restarted, sometimes it isn't ready and */ /* the link does not come up. */ - smc_read_phy_register(PHY_AD_REG); + smc_read_phy_register(dev, PHY_AD_REG); PRINTK2 ("%s: phy caps=%x\n", SMC_DEV_NAME, my_phy_caps); PRINTK2 ("%s: phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps); /* Restart auto-negotiation process in order to advertise my caps */ - smc_write_phy_register (PHY_CNTL_REG, + smc_write_phy_register (dev, PHY_CNTL_REG, PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST); /* Wait for the auto-negotiation to complete. This may take from */ @@ -1431,7 +1264,7 @@ static void smc_phy_configure () timeout = CONFIG_SMC_AUTONEG_TIMEOUT * 2; while (timeout--) { - status = smc_read_phy_register (PHY_STAT_REG); + status = smc_read_phy_register (dev, PHY_STAT_REG); if (status & PHY_STAT_ANEG_ACK) { /* auto-negotiate complete */ break; @@ -1447,7 +1280,7 @@ static void smc_phy_configure () /* Restart auto-negotiation */ printf ("%s: PHY restarting auto-negotiation\n", SMC_DEV_NAME); - smc_write_phy_register (PHY_CNTL_REG, + smc_write_phy_register (dev, PHY_CNTL_REG, PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST | PHY_CNTL_SPEED | @@ -1467,7 +1300,7 @@ static void smc_phy_configure () } /* Re-Configure the Receive/Phy Control register */ - SMC_outw (RPC_DEFAULT, RPC_REG); + SMC_outw (dev, RPC_DEFAULT, RPC_REG); smc_phy_configure_exit: ; @@ -1512,61 +1345,37 @@ static void print_packet( byte * buf, int length ) } #endif -int eth_init(bd_t *bd) { -#ifdef SHARED_RESOURCES - swap_to(ETHERNET); -#endif - return (smc_open(bd)); -} - -void eth_halt() { - smc_close(); -} - -int eth_rx() { - return smc_rcv(); -} - -int eth_send(volatile void *packet, int length) { - return smc_send_packet(packet, length); -} - -int smc_get_ethaddr (bd_t * bd) +int smc91111_initialize(u8 dev_num, int base_addr) { - uchar v_mac[6]; + struct smc91111_priv *priv; + struct eth_device *dev; + int i; - if (!eth_getenv_enetaddr("ethaddr", v_mac)) { - /* get ROM mac value if any */ - if (!get_rom_mac(v_mac)) { - printf("\n*** ERROR: ethaddr is NOT set !!\n"); - return -1; - } - eth_setenv_enetaddr("ethaddr", v_mac); + priv = malloc(sizeof(*priv)); + if (!priv) + return 0; + dev = malloc(sizeof(*dev)); + if (!dev) { + free(priv); + return 0; } - smc_set_mac_addr(v_mac); /* use old function to update smc default */ - PRINTK("Using MAC Address %pM\n", v_mac); - return 0; -} + priv->dev_num = dev_num; + dev->priv = priv; + dev->iobase = base_addr; -int get_rom_mac (uchar *v_rom_mac) -{ -#ifdef HARDCODE_MAC /* used for testing or to supress run time warnings */ - char hw_mac_addr[] = { 0x02, 0x80, 0xad, 0x20, 0x31, 0xb8 }; - - memcpy (v_rom_mac, hw_mac_addr, 6); - return (1); -#else - int i; - int valid_mac = 0; + swap_to(ETHERNET); + SMC_SELECT_BANK(dev, 1); + for (i = 0; i < 6; ++i) + dev->enetaddr[i] = SMC_inb(dev, (ADDR0_REG + i)); + swap_to(FLASH); - SMC_SELECT_BANK (1); - for (i=0; i<6; i++) - { - v_rom_mac[i] = SMC_inb ((ADDR0_REG + i)); - valid_mac |= v_rom_mac[i]; - } + dev->init = smc_init; + dev->halt = smc_halt; + dev->send = smc_send; + dev->recv = smc_rcv; + sprintf(dev->name, "%s-%hu", SMC_DEV_NAME, dev_num); - return (valid_mac ? 1 : 0); -#endif + eth_register(dev); + return 0; } diff --git a/drivers/net/smc91111.h b/drivers/net/smc91111.h index 967addd..bb45241 100644 --- a/drivers/net/smc91111.h +++ b/drivers/net/smc91111.h @@ -58,6 +58,10 @@ typedef unsigned char byte; typedef unsigned short word; typedef unsigned long int dword; +struct smc91111_priv{ + u8 dev_num; +}; + /* . DEBUGGING LEVELS . @@ -77,32 +81,32 @@ typedef unsigned long int dword; #ifdef CONFIG_PXA250 #ifdef CONFIG_XSENGINE -#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1)))) -#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r<<1)))) -#define SMC_inb(p) ({ \ - unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (p<<1)); \ +#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r<<1)))) +#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+(r<<1)))) +#define SMC_inb(a,p) ({ \ + unsigned int __p = (unsigned int)((a)->iobase + (p<<1)); \ unsigned int __v = *(volatile unsigned short *)((__p) & ~2); \ if (__p & 2) __v >>= 8; \ else __v &= 0xff; \ __v; }) #elif defined(CONFIG_XAENIAX) -#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r)))) -#define SMC_inw(z) ({ \ - unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (z)); \ +#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r)))) +#define SMC_inw(a,z) ({ \ + unsigned int __p = (unsigned int)((a)->iobase + (z)); \ unsigned int __v = *(volatile unsigned int *)((__p) & ~3); \ if (__p & 3) __v >>= 16; \ else __v &= 0xffff; \ __v; }) -#define SMC_inb(p) ({ \ - unsigned int ___v = SMC_inw((p) & ~1); \ +#define SMC_inb(a,p) ({ \ + unsigned int ___v = SMC_inw((a),(p) & ~1); \ if (p & 1) ___v >>= 8; \ else ___v &= 0xff; \ ___v; }) #else -#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r)))) -#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r)))) -#define SMC_inb(p) ({ \ - unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (p)); \ +#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r)))) +#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+(r)))) +#define SMC_inb(a,p) ({ \ + unsigned int __p = (unsigned int)((a)->iobase + (p)); \ unsigned int __v = *(volatile unsigned short *)((__p) & ~1); \ if (__p & 1) __v >>= 8; \ else __v &= 0xff; \ @@ -110,69 +114,69 @@ typedef unsigned long int dword; #endif #ifdef CONFIG_XSENGINE -#define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))) = d) -#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r<<1))) = d) +#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r<<1))) = d) +#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r<<1))) = d) #elif defined (CONFIG_XAENIAX) -#define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d) -#define SMC_outw(d,p) ({ \ - dword __dwo = SMC_inl((p) & ~3); \ +#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d) +#define SMC_outw(a,d,p) ({ \ + dword __dwo = SMC_inl((a),(p) & ~3); \ dword __dwn = (word)(d); \ __dwo &= ((p) & 3) ? 0x0000ffff : 0xffff0000; \ __dwo |= ((p) & 3) ? __dwn << 16 : __dwn; \ - SMC_outl(__dwo, (p) & ~3); \ + SMC_outl((a), __dwo, (p) & ~3); \ }) #else -#define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d) -#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d) +#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d) +#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r))) = d) #endif -#define SMC_outb(d,r) ({ word __d = (byte)(d); \ - word __w = SMC_inw((r)&~1); \ +#define SMC_outb(a,d,r) ({ word __d = (byte)(d); \ + word __w = SMC_inw((a),(r)&~1); \ __w &= ((r)&1) ? 0x00FF : 0xFF00; \ __w |= ((r)&1) ? __d<<8 : __d; \ - SMC_outw(__w,(r)&~1); \ + SMC_outw((a),__w,(r)&~1); \ }) -#define SMC_outsl(r,b,l) ({ int __i; \ +#define SMC_outsl(a,r,b,l) ({ int __i; \ dword *__b2; \ __b2 = (dword *) b; \ for (__i = 0; __i < l; __i++) { \ - SMC_outl( *(__b2 + __i), r); \ + SMC_outl((a), *(__b2 + __i), r); \ } \ }) -#define SMC_outsw(r,b,l) ({ int __i; \ +#define SMC_outsw(a,r,b,l) ({ int __i; \ word *__b2; \ __b2 = (word *) b; \ for (__i = 0; __i < l; __i++) { \ - SMC_outw( *(__b2 + __i), r); \ + SMC_outw((a), *(__b2 + __i), r); \ } \ }) -#define SMC_insl(r,b,l) ({ int __i ; \ +#define SMC_insl(a,r,b,l) ({ int __i ; \ dword *__b2; \ __b2 = (dword *) b; \ for (__i = 0; __i < l; __i++) { \ - *(__b2 + __i) = SMC_inl(r); \ - SMC_inl(0); \ + *(__b2 + __i) = SMC_inl((a),(r)); \ + SMC_inl((a),0); \ }; \ }) -#define SMC_insw(r,b,l) ({ int __i ; \ +#define SMC_insw(a,r,b,l) ({ int __i ; \ word *__b2; \ __b2 = (word *) b; \ for (__i = 0; __i < l; __i++) { \ - *(__b2 + __i) = SMC_inw(r); \ - SMC_inw(0); \ + *(__b2 + __i) = SMC_inw((a),(r)); \ + SMC_inw((a),0); \ }; \ }) -#define SMC_insb(r,b,l) ({ int __i ; \ +#define SMC_insb(a,r,b,l) ({ int __i ; \ byte *__b2; \ __b2 = (byte *) b; \ for (__i = 0; __i < l; __i++) { \ - *(__b2 + __i) = SMC_inb(r); \ - SMC_inb(0); \ + *(__b2 + __i) = SMC_inb((a),(r)); \ + SMC_inb((a),0); \ }; \ }) @@ -187,61 +191,61 @@ typedef unsigned long int dword; ((0x00FF0000UL & _x) >> 8) | \ (_x >> 24)); }) -#define SMC_inl(r) (SMC_LEON_SWAP32((*(volatile dword *)(SMC_BASE_ADDRESS+((r)<<0))))) -#define SMC_inl_nosw(r) ((*(volatile dword *)(SMC_BASE_ADDRESS+((r)<<0)))) -#define SMC_inw(r) (SMC_LEON_SWAP16((*(volatile word *)(SMC_BASE_ADDRESS+((r)<<0))))) -#define SMC_inw_nosw(r) ((*(volatile word *)(SMC_BASE_ADDRESS+((r)<<0)))) -#define SMC_inb(p) ({ \ - word ___v = SMC_inw((p) & ~1); \ +#define SMC_inl(a,r) (SMC_LEON_SWAP32((*(volatile dword *)((a)->iobase+((r)<<0))))) +#define SMC_inl_nosw(a,r) ((*(volatile dword *)((a)->iobase+((r)<<0)))) +#define SMC_inw(a,r) (SMC_LEON_SWAP16((*(volatile word *)((a)->iobase+((r)<<0))))) +#define SMC_inw_nosw(a,r) ((*(volatile word *)((a)->iobase+((r)<<0)))) +#define SMC_inb(a,p) ({ \ + word ___v = SMC_inw((a),(p) & ~1); \ if ((p) & 1) ___v >>= 8; \ else ___v &= 0xff; \ ___v; }) -#define SMC_outl(d,r) (*(volatile dword *)(SMC_BASE_ADDRESS+((r)<<0))=SMC_LEON_SWAP32(d)) -#define SMC_outl_nosw(d,r) (*(volatile dword *)(SMC_BASE_ADDRESS+((r)<<0))=(d)) -#define SMC_outw(d,r) (*(volatile word *)(SMC_BASE_ADDRESS+((r)<<0))=SMC_LEON_SWAP16(d)) -#define SMC_outw_nosw(d,r) (*(volatile word *)(SMC_BASE_ADDRESS+((r)<<0))=(d)) -#define SMC_outb(d,r) do{ word __d = (byte)(d); \ - word __w = SMC_inw((r)&~1); \ +#define SMC_outl(a,d,r) (*(volatile dword *)((a)->iobase+((r)<<0))=SMC_LEON_SWAP32(d)) +#define SMC_outl_nosw(a,d,r) (*(volatile dword *)((a)->iobase+((r)<<0))=(d)) +#define SMC_outw(a,d,r) (*(volatile word *)((a)->iobase+((r)<<0))=SMC_LEON_SWAP16(d)) +#define SMC_outw_nosw(a,d,r) (*(volatile word *)((a)->iobase+((r)<<0))=(d)) +#define SMC_outb(a,d,r) do{ word __d = (byte)(d); \ + word __w = SMC_inw((a),(r)&~1); \ __w &= ((r)&1) ? 0x00FF : 0xFF00; \ __w |= ((r)&1) ? __d<<8 : __d; \ - SMC_outw(__w,(r)&~1); \ + SMC_outw((a),__w,(r)&~1); \ }while(0) -#define SMC_outsl(r,b,l) do{ int __i; \ +#define SMC_outsl(a,r,b,l) do{ int __i; \ dword *__b2; \ __b2 = (dword *) b; \ for (__i = 0; __i < l; __i++) { \ - SMC_outl_nosw( *(__b2 + __i), r); \ + SMC_outl_nosw((a), *(__b2 + __i), r); \ } \ }while(0) -#define SMC_outsw(r,b,l) do{ int __i; \ +#define SMC_outsw(a,r,b,l) do{ int __i; \ word *__b2; \ __b2 = (word *) b; \ for (__i = 0; __i < l; __i++) { \ - SMC_outw_nosw( *(__b2 + __i), r); \ + SMC_outw_nosw((a), *(__b2 + __i), r); \ } \ }while(0) -#define SMC_insl(r,b,l) do{ int __i ; \ +#define SMC_insl(a,r,b,l) do{ int __i ; \ dword *__b2; \ __b2 = (dword *) b; \ for (__i = 0; __i < l; __i++) { \ - *(__b2 + __i) = SMC_inl_nosw(r); \ + *(__b2 + __i) = SMC_inl_nosw((a),(r)); \ }; \ }while(0) -#define SMC_insw(r,b,l) do{ int __i ; \ +#define SMC_insw(a,r,b,l) do{ int __i ; \ word *__b2; \ __b2 = (word *) b; \ for (__i = 0; __i < l; __i++) { \ - *(__b2 + __i) = SMC_inw_nosw(r); \ + *(__b2 + __i) = SMC_inw_nosw((a),(r)); \ }; \ }while(0) -#define SMC_insb(r,b,l) do{ int __i ; \ +#define SMC_insb(a,r,b,l) do{ int __i ; \ byte *__b2; \ __b2 = (byte *) b; \ for (__i = 0; __i < l; __i++) { \ - *(__b2 + __i) = SMC_inb(r); \ + *(__b2 + __i) = SMC_inb((a),(r)); \ }; \ }while(0) @@ -253,48 +257,48 @@ typedef unsigned long int dword; */ #ifdef CONFIG_ADNPESC1 -#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1)))) +#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1)))) #elif CONFIG_BLACKFIN -#define SMC_inw(r) ({ word __v = (*((volatile word *)(SMC_BASE_ADDRESS+(r)))); SSYNC(); __v;}) +#define SMC_inw(a,r) ({ word __v = (*((volatile word *)((a)->iobase+(r)))); SSYNC(); __v;}) #else -#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r)))) +#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+(r)))) #endif -#define SMC_inb(r) (((r)&1) ? SMC_inw((r)&~1)>>8 : SMC_inw(r)&0xFF) +#define SMC_inb(a,r) (((r)&1) ? SMC_inw((a),(r)&~1)>>8 : SMC_inw((a),(r)&0xFF)) #ifdef CONFIG_ADNPESC1 -#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1))) = d) +#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+((r)<<1))) = d) #elif CONFIG_BLACKFIN -#define SMC_outw(d,r) {(*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d); SSYNC();} +#define SMC_outw(a,d,r) {(*((volatile word *)((a)->iobase+(r))) = d); SSYNC();} #else -#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d) +#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r))) = d) #endif -#define SMC_outb(d,r) ({ word __d = (byte)(d); \ - word __w = SMC_inw((r)&~1); \ +#define SMC_outb(a,d,r) ({ word __d = (byte)(d); \ + word __w = SMC_inw((a),(r)&~1); \ __w &= ((r)&1) ? 0x00FF : 0xFF00; \ __w |= ((r)&1) ? __d<<8 : __d; \ - SMC_outw(__w,(r)&~1); \ + SMC_outw((a),__w,(r)&~1); \ }) #if 0 -#define SMC_outsw(r,b,l) outsw(SMC_BASE_ADDRESS+(r), (b), (l)) +#define SMC_outsw(a,r,b,l) outsw((a)->iobase+(r), (b), (l)) #else -#define SMC_outsw(r,b,l) ({ int __i; \ +#define SMC_outsw(a,r,b,l) ({ int __i; \ word *__b2; \ __b2 = (word *) b; \ for (__i = 0; __i < l; __i++) { \ - SMC_outw( *(__b2 + __i), r); \ + SMC_outw((a), *(__b2 + __i), r); \ } \ }) #endif #if 0 -#define SMC_insw(r,b,l) insw(SMC_BASE_ADDRESS+(r), (b), (l)) +#define SMC_insw(a,r,b,l) insw((a)->iobase+(r), (b), (l)) #else -#define SMC_insw(r,b,l) ({ int __i ; \ +#define SMC_insw(a,r,b,l) ({ int __i ; \ word *__b2; \ __b2 = (word *) b; \ for (__i = 0; __i < l; __i++) { \ - *(__b2 + __i) = SMC_inw(r); \ - SMC_inw(0); \ + *(__b2 + __i) = SMC_inw((a),(r)); \ + SMC_inw((a),0); \ }; \ }) #endif @@ -304,30 +308,30 @@ typedef unsigned long int dword; #if defined(CONFIG_SMC_USE_32_BIT) #ifdef CONFIG_XSENGINE -#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1)))) +#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r<<1)))) #else -#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r)))) +#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r)))) #endif -#define SMC_insl(r,b,l) ({ int __i ; \ +#define SMC_insl(a,r,b,l) ({ int __i ; \ dword *__b2; \ __b2 = (dword *) b; \ for (__i = 0; __i < l; __i++) { \ - *(__b2 + __i) = SMC_inl(r); \ - SMC_inl(0); \ + *(__b2 + __i) = SMC_inl((a),(r)); \ + SMC_inl((a),0); \ }; \ }) #ifdef CONFIG_XSENGINE -#define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))) = d) +#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r<<1))) = d) #else -#define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d) +#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d) #endif -#define SMC_outsl(r,b,l) ({ int __i; \ +#define SMC_outsl(a,r,b,l) ({ int __i; \ dword *__b2; \ __b2 = (dword *) b; \ for (__i = 0; __i < l; __i++) { \ - SMC_outl( *(__b2 + __i), r); \ + SMC_outl((a), *(__b2 + __i), r); \ } \ }) @@ -752,25 +756,25 @@ enum { /* select a register bank, 0 to 3 */ -#define SMC_SELECT_BANK(x) { SMC_outw( x, BANK_SELECT ); } +#define SMC_SELECT_BANK(a,x) { SMC_outw((a), (x), BANK_SELECT ); } /* this enables an interrupt in the interrupt mask register */ -#define SMC_ENABLE_INT(x) {\ +#define SMC_ENABLE_INT(a,x) {\ unsigned char mask;\ - SMC_SELECT_BANK(2);\ - mask = SMC_inb( IM_REG );\ + SMC_SELECT_BANK((a),2);\ + mask = SMC_inb((a), IM_REG );\ mask |= (x);\ - SMC_outb( mask, IM_REG ); \ + SMC_outb( (a), mask, IM_REG ); \ } /* this disables an interrupt from the interrupt mask register */ -#define SMC_DISABLE_INT(x) {\ +#define SMC_DISABLE_INT(a,x) {\ unsigned char mask;\ SMC_SELECT_BANK(2);\ - mask = SMC_inb( IM_REG );\ + mask = SMC_inb( (a), IM_REG );\ mask &= ~(x);\ - SMC_outb( mask, IM_REG ); \ + SMC_outb( (a), mask, IM_REG ); \ } /*---------------------------------------------------------------------- -- cgit v1.1 From aba8237257dd15b0e76cc517f0e741c0908ee0b9 Mon Sep 17 00:00:00 2001 From: Prafulla Wadaskar Date: Wed, 9 Sep 2009 15:59:19 +0530 Subject: net: kirkwood_egiga.c: fixed build warning if link up detection code is disabled through config option, it gives build warning. This patch fixes the same Signed-off-by: Prafulla Wadaskar Signed-off-by: Ben Warren --- drivers/net/kirkwood_egiga.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/kirkwood_egiga.c b/drivers/net/kirkwood_egiga.c index 479035d..07a86cd 100644 --- a/drivers/net/kirkwood_egiga.c +++ b/drivers/net/kirkwood_egiga.c @@ -400,8 +400,10 @@ static int kwgbe_init(struct eth_device *dev) { struct kwgbe_device *dkwgbe = to_dkwgbe(dev); struct kwgbe_registers *regs = dkwgbe->regs; +#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \ + && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN) int i; - +#endif /* setup RX rings */ kwgbe_init_rx_desc_ring(dkwgbe); -- cgit v1.1 From ddc922ff2c20ae0b7f9ce2df1ac28143e2f325bd Mon Sep 17 00:00:00 2001 From: Niklaus Giger Date: Sun, 4 Oct 2009 20:04:20 +0200 Subject: ppc_4xx: Apply new HW register names Modify all existing *.c files to use the new register names as seen in the AMCC manuals. Signed-off-by: Niklaus Giger Signed-off-by: Stefan Roese --- drivers/net/4xx_enet.c | 100 ++++++++++++++++++++++++------------------------- 1 file changed, 50 insertions(+), 50 deletions(-) (limited to 'drivers') diff --git a/drivers/net/4xx_enet.c b/drivers/net/4xx_enet.c index f2c9be0..2fac641 100644 --- a/drivers/net/4xx_enet.c +++ b/drivers/net/4xx_enet.c @@ -44,7 +44,7 @@ * RX descriptor address up to the next cache line boundary. * 16-Jan-00 Added support for booting with IP of 0x0 MKW * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the - * EMAC_RXM register. JWB + * EMAC0_RXM register. JWB * 12-Mar-01 anne-sophie.harnois@nextream.fr * - Variables are compatible with those already defined in * include/net.h @@ -58,7 +58,7 @@ * 08-May-01 stefan.roese@esd-electronics.com * - MAL error handling added (eth_init called again) * 13-Nov-01 stefan.roese@esd-electronics.com - * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex + * - Set IST bit in EMAC0_MR1 reg upon 100MBit or full duplex * 04-Jan-02 stefan.roese@esd-electronics.com * - Wait for PHY auto negotiation to complete added * 06-Feb-02 stefan.roese@esd-electronics.com @@ -359,7 +359,7 @@ static void ppc_4xx_eth_halt (struct eth_device *dev) EMAC_4XX_HW_PST hw_p = dev->priv; u32 val = 10000; - out_be32((void *)EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */ + out_be32((void *)EMAC0_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */ /* 1st reset MAL channel */ /* Note: writing a 0 to a channel has no effect */ @@ -382,7 +382,7 @@ static void ppc_4xx_eth_halt (struct eth_device *dev) emac_loopback_enable(hw_p); /* EMAC RESET */ - out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); + out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_SRST); /* remove clocks for EMAC internal loopback */ emac_loopback_disable(hw_p); @@ -485,7 +485,7 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) /* Ensure we setup mdio for this devnum and ONLY this devnum */ zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum); - out_be32((void *)ZMII_FER, zmiifer); + out_be32((void *)ZMII0_FER, zmiifer); out_be32((void *)RGMII_FER, rmiifer); return ((int)pfc1); @@ -504,21 +504,21 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) switch (pfc1) { case SDR0_PFC1_SELECT_CONFIG_2: /* 1 x GMII port */ - out_be32((void *)ZMII_FER, 0x00); + out_be32((void *)ZMII0_FER, 0x00); out_be32((void *)RGMII_FER, 0x00000037); bis->bi_phymode[0] = BI_PHYMODE_GMII; bis->bi_phymode[1] = BI_PHYMODE_NONE; break; case SDR0_PFC1_SELECT_CONFIG_4: /* 2 x RGMII ports */ - out_be32((void *)ZMII_FER, 0x00); + out_be32((void *)ZMII0_FER, 0x00); out_be32((void *)RGMII_FER, 0x00000055); bis->bi_phymode[0] = BI_PHYMODE_RGMII; bis->bi_phymode[1] = BI_PHYMODE_RGMII; break; case SDR0_PFC1_SELECT_CONFIG_6: /* 2 x SMII ports */ - out_be32((void *)ZMII_FER, + out_be32((void *)ZMII0_FER, ((ZMII_FER_SMII) << ZMII_FER_V(0)) | ((ZMII_FER_SMII) << ZMII_FER_V(1))); out_be32((void *)RGMII_FER, 0x00000000); @@ -527,7 +527,7 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) break; case SDR0_PFC1_SELECT_CONFIG_1_2: /* only 1 x MII supported */ - out_be32((void *)ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0)); + out_be32((void *)ZMII0_FER, (ZMII_FER_MII) << ZMII_FER_V(0)); out_be32((void *)RGMII_FER, 0x00000000); bis->bi_phymode[0] = BI_PHYMODE_MII; bis->bi_phymode[1] = BI_PHYMODE_NONE; @@ -537,9 +537,9 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) } /* Ensure we setup mdio for this devnum and ONLY this devnum */ - zmiifer = in_be32((void *)ZMII_FER); + zmiifer = in_be32((void *)ZMII0_FER); zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum); - out_be32((void *)ZMII_FER, zmiifer); + out_be32((void *)ZMII0_FER, zmiifer); return ((int)0x0); } @@ -953,18 +953,18 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) /* NOTE: Therefore, disable all other EMACS, since we handle */ /* NOTE: only one emac at a time */ reg = 0; - out_be32((void *)ZMII_FER, 0); + out_be32((void *)ZMII0_FER, 0); udelay (100); #if defined(CONFIG_440GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) - out_be32((void *)ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); + out_be32((void *)ZMII0_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); #elif defined(CONFIG_440GX) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis); #endif - out_be32((void *)ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum)); + out_be32((void *)ZMII0_SSR, ZMII0_SSR_SP << ZMII0_SSR_V(devnum)); #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ #if defined(CONFIG_405EX) ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis); @@ -976,13 +976,13 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) emac_loopback_enable(hw_p); /* EMAC RESET */ - out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); + out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_SRST); /* remove clocks for EMAC internal loopback */ emac_loopback_disable(hw_p); failsafe = 1000; - while ((in_be32((void *)EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) { + while ((in_be32((void *)EMAC0_MR0 + hw_p->hw_addr) & (EMAC_MR0_SRST)) && failsafe) { udelay (1000); failsafe--; } @@ -1000,15 +1000,15 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) opbfreq = sysinfo.freqOPB / 1000000; if (opbfreq <= 50); else if (opbfreq <= 66) - mode_reg |= EMAC_M1_OBCI_66; + mode_reg |= EMAC_MR1_OBCI_66; else if (opbfreq <= 83) - mode_reg |= EMAC_M1_OBCI_83; + mode_reg |= EMAC_MR1_OBCI_83; else if (opbfreq <= 100) - mode_reg |= EMAC_M1_OBCI_100; + mode_reg |= EMAC_MR1_OBCI_100; else - mode_reg |= EMAC_M1_OBCI_GT100; + mode_reg |= EMAC_MR1_OBCI_GT100; - out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg); + out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg); #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */ #if defined(CONFIG_GPCS_PHY_ADDR) || defined(CONFIG_GPCS_PHY1_ADDR) || \ @@ -1041,9 +1041,9 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #endif } - mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr); - mode_reg |= EMAC_M1_MF_1000GPCS | EMAC_M1_IPPA_SET(reg); - out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg); + mode_reg = in_be32((void *)EMAC0_MR1 + hw_p->hw_addr); + mode_reg |= EMAC_MR1_MF_1000GPCS | EMAC_MR1_IPPA_SET(reg); + out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg); /* Configure GPCS interface to recommended setting for SGMII */ miiphy_reset(dev->name, reg); @@ -1250,11 +1250,11 @@ get_speed: #endif /* Set ZMII/RGMII speed according to the phy link speed */ - reg = in_be32((void *)ZMII_SSR); + reg = in_be32((void *)ZMII0_SSR); if ( (speed == 100) || (speed == 1000) ) - out_be32((void *)ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum))); + out_be32((void *)ZMII0_SSR, reg | (ZMII0_SSR_SP << ZMII0_SSR_V (devnum))); else - out_be32((void *)ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum)))); + out_be32((void *)ZMII0_SSR, reg & (~(ZMII0_SSR_SP << ZMII0_SSR_V (devnum)))); if ((devnum == 2) || (devnum == 3)) { if (speed == 1000) @@ -1381,7 +1381,7 @@ get_speed: reg = reg << 8; reg |= dev->enetaddr[1]; - out_be32((void *)EMAC_IAH + hw_p->hw_addr, reg); + out_be32((void *)EMAC0_IAH + hw_p->hw_addr, reg); reg = 0x00000000; reg |= dev->enetaddr[2]; /* set low address */ @@ -1392,7 +1392,7 @@ get_speed: reg = reg << 8; reg |= dev->enetaddr[5]; - out_be32((void *)EMAC_IAL + hw_p->hw_addr, reg); + out_be32((void *)EMAC0_IAL + hw_p->hw_addr, reg); switch (devnum) { case 1: @@ -1480,9 +1480,9 @@ get_speed: mtdcr (MAL0_RXCASR, (MAL_TXRX_CASR >> hw_p->devnum)); /* set transmit enable & receive enable */ - out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE); + out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_TXE | EMAC_MR0_RXE); - mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr); + mode_reg = in_be32((void *)EMAC0_MR1 + hw_p->hw_addr); /* set rx-/tx-fifo size */ mode_reg = (mode_reg & ~EMAC_MR1_FIFO_MASK) | EMAC_MR1_FIFO_SIZE; @@ -1497,47 +1497,47 @@ get_speed: pfc1 |= SDR0_PFC1_EM_1000; mtsdr (SDR0_PFC1, pfc1); #endif - mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST; + mode_reg = mode_reg | EMAC_MR1_MF_1000MBPS | EMAC_MR1_IST; } else if (speed == _100BASET) - mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST; + mode_reg = mode_reg | EMAC_MR1_MF_100MBPS | EMAC_MR1_IST; else mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */ if (duplex == FULL) - mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST; + mode_reg = mode_reg | 0x80000000 | EMAC_MR1_IST; - out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg); + out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg); /* Enable broadcast and indvidual address */ /* TBS: enabling runts as some misbehaved nics will send runts */ - out_be32((void *)EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE); + out_be32((void *)EMAC0_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE); /* we probably need to set the tx mode1 reg? maybe at tx time */ /* set transmit request threshold register */ - out_be32((void *)EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */ + out_be32((void *)EMAC0_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */ /* set receive low/high water mark register */ #if defined(CONFIG_440) /* 440s has a 64 byte burst length */ - out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000); + out_be32((void *)EMAC0_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000); #else /* 405s have a 16 byte burst length */ - out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000); + out_be32((void *)EMAC0_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000); #endif /* defined(CONFIG_440) */ - out_be32((void *)EMAC_TXM1 + hw_p->hw_addr, 0xf8640000); + out_be32((void *)EMAC0_TMR1 + hw_p->hw_addr, 0xf8640000); /* Set fifo limit entry in tx mode 0 */ - out_be32((void *)EMAC_TXM0 + hw_p->hw_addr, 0x00000003); + out_be32((void *)EMAC0_TMR0 + hw_p->hw_addr, 0x00000003); /* Frame gap set */ - out_be32((void *)EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008); + out_be32((void *)EMAC0_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008); /* Set EMAC IER */ hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE; if (speed == _100BASET) hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE; - out_be32((void *)EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */ - out_be32((void *)EMAC_IER + hw_p->hw_addr, hw_p->emac_ier); + out_be32((void *)EMAC0_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */ + out_be32((void *)EMAC0_IER + hw_p->hw_addr, hw_p->emac_ier); if (hw_p->first_init == 0) { /* @@ -1596,8 +1596,8 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, sync(); - out_be32((void *)EMAC_TXM0 + hw_p->hw_addr, - in_be32((void *)EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0); + out_be32((void *)EMAC0_TMR0 + hw_p->hw_addr, + in_be32((void *)EMAC0_TMR0 + hw_p->hw_addr) | EMAC_TMR0_GNP0); #ifdef INFO_4XX_ENET hw_p->stats.pkts_tx++; #endif @@ -1607,9 +1607,9 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, *-----------------------------------------------------------------------*/ time_start = get_timer (0); while (1) { - temp_txm0 = in_be32((void *)EMAC_TXM0 + hw_p->hw_addr); + temp_txm0 = in_be32((void *)EMAC0_TMR0 + hw_p->hw_addr); /* loop until either TINT turns on or 3 seconds elapse */ - if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) { + if ((temp_txm0 & EMAC_TMR0_GNP0) != 0) { /* transmit is done, so now check for errors * If there is an error, an interrupt should * happen when we return @@ -1678,7 +1678,7 @@ int enetInt (struct eth_device *dev) /* look for EMAC errors */ if ((uic_emac & UIC_ETHx) || (uic_emac_b & UIC_ETHxB)) { - emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr); + emac_isr = in_be32((void *)EMAC0_ISR + hw_p->hw_addr); emac_err(dev, emac_isr); /* clear EMAC error interrupt status bits */ @@ -1761,7 +1761,7 @@ static void emac_err (struct eth_device *dev, unsigned long isr) EMAC_4XX_HW_PST hw_p = dev->priv; printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr); - out_be32((void *)EMAC_ISR + hw_p->hw_addr, isr); + out_be32((void *)EMAC0_ISR + hw_p->hw_addr, isr); } /*-----------------------------------------------------------------------------+ -- cgit v1.1 From 4ba31ab33ac824635fcb49ac609070a9ebcab7f0 Mon Sep 17 00:00:00 2001 From: Luigi 'Comio' Mantellini Date: Sat, 10 Oct 2009 12:42:20 +0200 Subject: Rewrite the miiphybb (Bit-banged MII bus driver) in order to support an arbitrary number of mii buses. This feature is useful when your board uses different mii buses for different phys and all (or a part) of these buses are implemented via bit-banging mode. The driver requires that the following macros should be defined into the board configuration file: CONFIG_BITBANGMII - Enable the miiphybb driver CONFIG_BITBANGMII_MULTI - Enable the multi bus support If the CONFIG_BITBANGMII_MULTI is not defined, the board's config file needs to define at least the following macros: MII_INIT - Generic code to enable the MII bus (optional) MDIO_DECLARE - Declaration needed to access to the MDIO pin (optional) MDIO_ACTIVE - Activate the MDIO pin as out pin MDIO_TRISTATE - Activate the MDIO pin as input/tristate pin MDIO_READ - Read the MDIO pin MDIO(v) - Write v on the MDIO pin MDC_DECLARE - Declaration needed to access to the MDC pin (optional) MDC(v) - Write v on the MDC pin The previous macros make the driver compatible with the previous version (that didn't support the multi-bus). When the CONFIG_BITBANGMII_MULTI is also defined, the board code needs to fill the bb_miiphy_buses[] array with a record for each required bus and declare the bb_miiphy_buses_num variable with the number of mii buses. The record (struct bb_miiphy_bus) has the following fields/callbacks (see miiphy.h for details): char name[] - The symbolic name that must be equal to the MII bus registered name int (*init)() - Initialization function called at startup time (just before the Ethernet initialization) int (*mdio_active)() - Activate the MDIO pin as output int (*mdio_tristate)() - Activate the MDIO pin as input/tristate pin int (*set_mdio)() - Write the MDIO pin int (*get_mdio)() - Read the MDIO pin int (*set_mdc)() - Write the MDC pin int (*delay)() - Delay function void *priv - Private data used by board specific code The board code will look like: struct bb_miiphy_bus bb_miiphy_buses[] = { { .name = miibus#1, .init = b1_init, .mdio_active = b1_mdio_active, ... }, { .name = miibus#2, .init = b2_init, .mdio_active = b2_mdio_active, ... }, ... int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / sizeof(bb_miiphy_buses[0]); Signed-off-by: Luigi 'Comio' Mantellini Signed-off-by: Ben Warren --- drivers/net/phy/miiphybb.c | 346 +++++++++++++++++++++++++++++++-------------- 1 file changed, 242 insertions(+), 104 deletions(-) (limited to 'drivers') diff --git a/drivers/net/phy/miiphybb.c b/drivers/net/phy/miiphybb.c index b77c917..44c45fa 100644 --- a/drivers/net/phy/miiphybb.c +++ b/drivers/net/phy/miiphybb.c @@ -1,4 +1,7 @@ /* + * (C) Copyright 2009 Industrie Dial Face S.p.A. + * Luigi 'Comio' Mantellini + * * (C) Copyright 2001 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com. * @@ -29,18 +32,144 @@ #include #include #include +#include + +#define BB_MII_RELOCATE(v,off) (v += (v?off:0)) + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_BITBANGMII_MULTI + +/* + * If CONFIG_BITBANGMII_MULTI is not defined we use a + * compatibility layer with the previous miiphybb implementation + * based on macros usage. + * + */ +static int bb_mii_init_wrap(struct bb_miiphy_bus *bus) +{ +#ifdef MII_INIT + MII_INIT; +#endif + return 0; +} + +static int bb_mdio_active_wrap(struct bb_miiphy_bus *bus) +{ +#ifdef MDIO_DECLARE + MDIO_DECLARE; +#endif + MDIO_ACTIVE; + return 0; +} + +static int bb_mdio_tristate_wrap(struct bb_miiphy_bus *bus) +{ +#ifdef MDIO_DECLARE + MDIO_DECLARE; +#endif + MDIO_TRISTATE; + return 0; +} + +static int bb_set_mdio_wrap(struct bb_miiphy_bus *bus, int v) +{ +#ifdef MDIO_DECLARE + MDIO_DECLARE; +#endif + MDIO(v); + return 0; +} + +static int bb_get_mdio_wrap(struct bb_miiphy_bus *bus, int *v) +{ +#ifdef MDIO_DECLARE + MDIO_DECLARE; +#endif + *v = MDIO_READ; + return 0; +} + +static int bb_set_mdc_wrap(struct bb_miiphy_bus *bus, int v) +{ +#ifdef MDC_DECLARE + MDC_DECLARE; +#endif + MDC(v); + return 0; +} + +static int bb_delay_wrap(struct bb_miiphy_bus *bus) +{ + MIIDELAY; + return 0; +} + +struct bb_miiphy_bus bb_miiphy_buses[] = { + { + .name = BB_MII_DEVNAME, + .init = bb_mii_init_wrap, + .mdio_active = bb_mdio_active_wrap, + .mdio_tristate = bb_mdio_tristate_wrap, + .set_mdio = bb_set_mdio_wrap, + .get_mdio = bb_get_mdio_wrap, + .set_mdc = bb_set_mdc_wrap, + .delay = bb_delay_wrap, + } +}; + +int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / + sizeof(bb_miiphy_buses[0]); +#endif + +void bb_miiphy_init(void) +{ + int i; + + for (i = 0; i < bb_miiphy_buses_num; i++) { +#if !defined(CONFIG_RELOC_FIXUP_WORKS) + /* Relocate the hook pointers*/ + BB_MII_RELOCATE(bb_miiphy_buses[i].init, gd->reloc_off); + BB_MII_RELOCATE(bb_miiphy_buses[i].mdio_active, gd->reloc_off); + BB_MII_RELOCATE(bb_miiphy_buses[i].mdio_tristate, gd->reloc_off); + BB_MII_RELOCATE(bb_miiphy_buses[i].set_mdio, gd->reloc_off); + BB_MII_RELOCATE(bb_miiphy_buses[i].get_mdio, gd->reloc_off); + BB_MII_RELOCATE(bb_miiphy_buses[i].set_mdc, gd->reloc_off); + BB_MII_RELOCATE(bb_miiphy_buses[i].delay, gd->reloc_off); +#endif + if (bb_miiphy_buses[i].init != NULL) { + bb_miiphy_buses[i].init(&bb_miiphy_buses[i]); + } + } +} + +static inline struct bb_miiphy_bus *bb_miiphy_getbus(char *devname) +{ +#ifdef CONFIG_BITBANGMII_MULTI + int i; + + /* Search the correct bus */ + for (i = 0; i < bb_miiphy_buses_num; i++) { + if (!strcmp(bb_miiphy_buses[i].name, devname)) { + return &bb_miiphy_buses[i]; + } + } + return NULL; +#else + /* We have just one bitbanging bus */ + return &bb_miiphy_buses[0]; +#endif +} /***************************************************************************** * * Utility to send the preamble, address, and register (common to read * and write). */ -static void miiphy_pre (char read, unsigned char addr, unsigned char reg) +static void miiphy_pre(struct bb_miiphy_bus *bus, char read, + unsigned char addr, unsigned char reg) { - int j; /* counter */ -#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM)) - volatile ioport_t *iop = ioport_addr ((immap_t *) CONFIG_SYS_IMMR, MDIO_PORT); -#endif + int j; /* * Send a 32 bit preamble ('1's) with an extra '1' bit for good measure. @@ -50,67 +179,66 @@ static void miiphy_pre (char read, unsigned char addr, unsigned char reg) * but it is safer and will be much more robust. */ - MDIO_ACTIVE; - MDIO (1); + bus->mdio_active(bus); + bus->set_mdio(bus, 1); for (j = 0; j < 32; j++) { - MDC (0); - MIIDELAY; - MDC (1); - MIIDELAY; + bus->set_mdc(bus, 0); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); } /* send the start bit (01) and the read opcode (10) or write (10) */ - MDC (0); - MDIO (0); - MIIDELAY; - MDC (1); - MIIDELAY; - MDC (0); - MDIO (1); - MIIDELAY; - MDC (1); - MIIDELAY; - MDC (0); - MDIO (read); - MIIDELAY; - MDC (1); - MIIDELAY; - MDC (0); - MDIO (!read); - MIIDELAY; - MDC (1); - MIIDELAY; + bus->set_mdc(bus, 0); + bus->set_mdio(bus, 0); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); + bus->set_mdc(bus, 0); + bus->set_mdio(bus, 1); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); + bus->set_mdc(bus, 0); + bus->set_mdio(bus, read); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); + bus->set_mdc(bus, 0); + bus->set_mdio(bus, !read); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); /* send the PHY address */ for (j = 0; j < 5; j++) { - MDC (0); + bus->set_mdc(bus, 0); if ((addr & 0x10) == 0) { - MDIO (0); + bus->set_mdio(bus, 0); } else { - MDIO (1); + bus->set_mdio(bus, 1); } - MIIDELAY; - MDC (1); - MIIDELAY; + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); addr <<= 1; } /* send the register address */ for (j = 0; j < 5; j++) { - MDC (0); + bus->set_mdc(bus, 0); if ((reg & 0x10) == 0) { - MDIO (0); + bus->set_mdio(bus, 0); } else { - MDIO (1); + bus->set_mdio(bus, 1); } - MIIDELAY; - MDC (1); - MIIDELAY; + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); reg <<= 1; } } - /***************************************************************************** * * Read a MII PHY register. @@ -118,63 +246,69 @@ static void miiphy_pre (char read, unsigned char addr, unsigned char reg) * Returns: * 0 on success */ -int bb_miiphy_read (char *devname, unsigned char addr, - unsigned char reg, unsigned short *value) +int bb_miiphy_read(char *devname, unsigned char addr, + unsigned char reg, unsigned short *value) { - short rdreg; /* register working value */ - int j; /* counter */ -#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM)) - volatile ioport_t *iop = ioport_addr ((immap_t *) CONFIG_SYS_IMMR, MDIO_PORT); -#endif + short rdreg; /* register working value */ + int v; + int j; /* counter */ + struct bb_miiphy_bus *bus; + + bus = bb_miiphy_getbus(devname); + if (bus == NULL) { + return -1; + } if (value == NULL) { puts("NULL value pointer\n"); - return (-1); + return -1; } - miiphy_pre (1, addr, reg); + miiphy_pre (bus, 1, addr, reg); /* tri-state our MDIO I/O pin so we can read */ - MDC (0); - MDIO_TRISTATE; - MIIDELAY; - MDC (1); - MIIDELAY; + bus->set_mdc(bus, 0); + bus->mdio_tristate(bus); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); /* check the turnaround bit: the PHY should be driving it to zero */ - if (MDIO_READ != 0) { + bus->get_mdio(bus, &v); + if (v != 0) { /* puts ("PHY didn't drive TA low\n"); */ for (j = 0; j < 32; j++) { - MDC (0); - MIIDELAY; - MDC (1); - MIIDELAY; + bus->set_mdc(bus, 0); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); } /* There is no PHY, set value to 0xFFFF and return */ *value = 0xFFFF; - return (-1); + return -1; } - MDC (0); - MIIDELAY; + bus->set_mdc(bus, 0); + bus->delay(bus); /* read 16 bits of register data, MSB first */ rdreg = 0; for (j = 0; j < 16; j++) { - MDC (1); - MIIDELAY; + bus->set_mdc(bus, 1); + bus->delay(bus); rdreg <<= 1; - rdreg |= MDIO_READ; - MDC (0); - MIIDELAY; + bus->get_mdio(bus, &v); + rdreg |= (v & 0x1); + bus->set_mdc(bus, 0); + bus->delay(bus); } - MDC (1); - MIIDELAY; - MDC (0); - MIIDELAY; - MDC (1); - MIIDELAY; + bus->set_mdc(bus, 1); + bus->delay(bus); + bus->set_mdc(bus, 0); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); *value = rdreg; @@ -194,49 +328,53 @@ int bb_miiphy_read (char *devname, unsigned char addr, * 0 on success */ int bb_miiphy_write (char *devname, unsigned char addr, - unsigned char reg, unsigned short value) + unsigned char reg, unsigned short value) { + struct bb_miiphy_bus *bus; int j; /* counter */ -#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM)) - volatile ioport_t *iop = ioport_addr ((immap_t *) CONFIG_SYS_IMMR, MDIO_PORT); -#endif - miiphy_pre (0, addr, reg); + bus = bb_miiphy_getbus(devname); + if (bus == NULL) { + /* Bus not found! */ + return -1; + } + + miiphy_pre (bus, 0, addr, reg); /* send the turnaround (10) */ - MDC (0); - MDIO (1); - MIIDELAY; - MDC (1); - MIIDELAY; - MDC (0); - MDIO (0); - MIIDELAY; - MDC (1); - MIIDELAY; + bus->set_mdc(bus, 0); + bus->set_mdio(bus, 1); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); + bus->set_mdc(bus, 0); + bus->set_mdio(bus, 0); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); /* write 16 bits of register data, MSB first */ for (j = 0; j < 16; j++) { - MDC (0); + bus->set_mdc(bus, 0); if ((value & 0x00008000) == 0) { - MDIO (0); + bus->set_mdio(bus, 0); } else { - MDIO (1); + bus->set_mdio(bus, 1); } - MIIDELAY; - MDC (1); - MIIDELAY; + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); value <<= 1; } /* * Tri-state the MDIO line. */ - MDIO_TRISTATE; - MDC (0); - MIIDELAY; - MDC (1); - MIIDELAY; + bus->mdio_tristate(bus); + bus->set_mdc(bus, 0); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); return 0; -} +} \ No newline at end of file -- cgit v1.1 From 285870f75378aca41c5063e4358ad93bf3014fd8 Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Thu, 9 Oct 2008 01:27:18 -0500 Subject: Leave x86emu op code tables in default section Forcing the tables into got2 caused extra relocation when using -mrelocatable. This patch requires any board defining CONFIG_BIOSEMU to use -mrelocatable. Signed-off-by: Ed Swarthout Acked-by: Jin Zhengxiong --- drivers/bios_emulator/x86emu/ops.c | 17 +++++++---------- drivers/bios_emulator/x86emu/ops2.c | 5 +---- 2 files changed, 8 insertions(+), 14 deletions(-) (limited to 'drivers') diff --git a/drivers/bios_emulator/x86emu/ops.c b/drivers/bios_emulator/x86emu/ops.c index f884e9b..c836a20 100644 --- a/drivers/bios_emulator/x86emu/ops.c +++ b/drivers/bios_emulator/x86emu/ops.c @@ -70,9 +70,6 @@ * calls is especially important; otherwise mistakes in coding an * "add" would represent a nightmare in maintenance. * -* Jason ported this file to u-boot. place all the function pointer in -* the got2 sector. Removed some opcode. -* ****************************************************************************/ #include @@ -88,7 +85,7 @@ static char *x86emu_GenOpName[8] = { #endif /* used by several opcodes */ -static u8 (*genop_byte_operation[])(u8 d, u8 s) __attribute__ ((section(GOT2_TYPE))) = +static u8 (*genop_byte_operation[])(u8 d, u8 s) = { add_byte, /* 00 */ or_byte, /* 01 */ @@ -100,7 +97,7 @@ static u8 (*genop_byte_operation[])(u8 d, u8 s) __attribute__ ((section(GOT2_TYP cmp_byte, /* 07 */ }; -static u16 (*genop_word_operation[])(u16 d, u16 s) __attribute__ ((section(GOT2_TYPE))) = +static u16 (*genop_word_operation[])(u16 d, u16 s) = { add_word, /*00 */ or_word, /*01 */ @@ -112,7 +109,7 @@ static u16 (*genop_word_operation[])(u16 d, u16 s) __attribute__ ((section(GOT2_ cmp_word, /*07 */ }; -static u32 (*genop_long_operation[])(u32 d, u32 s) __attribute__ ((section(GOT2_TYPE))) = +static u32 (*genop_long_operation[])(u32 d, u32 s) = { add_long, /*00 */ or_long, /*01 */ @@ -125,7 +122,7 @@ static u32 (*genop_long_operation[])(u32 d, u32 s) __attribute__ ((section(GOT2_ }; /* used by opcodes 80, c0, d0, and d2. */ -static u8(*opcD0_byte_operation[])(u8 d, u8 s) __attribute__ ((section(GOT2_TYPE))) = +static u8(*opcD0_byte_operation[])(u8 d, u8 s) = { rol_byte, ror_byte, @@ -138,7 +135,7 @@ static u8(*opcD0_byte_operation[])(u8 d, u8 s) __attribute__ ((section(GOT2_TYPE }; /* used by opcodes c1, d1, and d3. */ -static u16(*opcD1_word_operation[])(u16 s, u8 d) __attribute__ ((section(GOT2_TYPE))) = +static u16(*opcD1_word_operation[])(u16 s, u8 d) = { rol_word, ror_word, @@ -151,7 +148,7 @@ static u16(*opcD1_word_operation[])(u16 s, u8 d) __attribute__ ((section(GOT2_TY }; /* used by opcodes c1, d1, and d3. */ -static u32 (*opcD1_long_operation[])(u32 s, u8 d) __attribute__ ((section(GOT2_TYPE))) = +static u32 (*opcD1_long_operation[])(u32 s, u8 d) = { rol_long, ror_long, @@ -5144,7 +5141,7 @@ void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1)) /*************************************************************************** * Single byte operation code table: **************************************************************************/ -void (*x86emu_optab[256])(u8) __attribute__ ((section(GOT2_TYPE))) = +void (*x86emu_optab[256])(u8) = { /* 0x00 */ x86emuOp_genop_byte_RM_R, /* 0x01 */ x86emuOp_genop_word_RM_R, diff --git a/drivers/bios_emulator/x86emu/ops2.c b/drivers/bios_emulator/x86emu/ops2.c index ee7258e..937bf4c 100644 --- a/drivers/bios_emulator/x86emu/ops2.c +++ b/drivers/bios_emulator/x86emu/ops2.c @@ -39,9 +39,6 @@ * and emulation of all the x86 extended two-byte processor * instructions. * -* Jason port this file to u-boot. Put the function pointer into -* got2 sector. -* ****************************************************************************/ #include @@ -1495,7 +1492,7 @@ void x86emuOp2_movsx_word_R_RM(u8 X86EMU_UNUSED(op2)) /*************************************************************************** * Double byte operation code table: **************************************************************************/ -void (*x86emu_optab2[256])(u8) __attribute__((section(GOT2_TYPE))) = +void (*x86emu_optab2[256])(u8) = { /* 0x00 */ x86emuOp2_illegal_op, /* Group F (ring 0 PM) */ /* 0x01 */ x86emuOp2_illegal_op, /* Group G (ring 0 PM) */ -- cgit v1.1 From 9de0212bd7c4c82a7e8c2a2c8714f8c7abc57d08 Mon Sep 17 00:00:00 2001 From: Dirk Behme Date: Mon, 28 Sep 2009 08:17:50 -0400 Subject: OMAP3 MMC: Fix warning dereferencing type-punned pointer Fix warning Dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Dirk Behme CC: Steve Sakoman Acked-by: Tom Rix --- drivers/mmc/omap3_mmc.c | 48 +++++++++++++++++++++--------------------------- 1 file changed, 21 insertions(+), 27 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/omap3_mmc.c b/drivers/mmc/omap3_mmc.c index 9e09434..513dd25 100644 --- a/drivers/mmc/omap3_mmc.c +++ b/drivers/mmc/omap3_mmc.c @@ -235,8 +235,8 @@ unsigned char mmc_detect_card(mmc_card_data *mmc_card_cur) unsigned char err; unsigned int argument = 0; unsigned int ocr_value, ocr_recvd, ret_cmd41, hcs_val; - unsigned int resp[4]; unsigned short retry_cnt = 2000; + mmc_resp_t mmc_resp; /* Set to Initialization Clock */ err = mmc_clock_config(CLK_400KHZ, 0); @@ -247,18 +247,18 @@ unsigned char mmc_detect_card(mmc_card_data *mmc_card_cur) argument = 0x00000000; ocr_value = (0x1FF << 15); - err = mmc_send_cmd(MMC_CMD0, argument, resp); + err = mmc_send_cmd(MMC_CMD0, argument, mmc_resp.resp); if (err != 1) return err; argument = SD_CMD8_CHECK_PATTERN | SD_CMD8_2_7_3_6_V_RANGE; - err = mmc_send_cmd(MMC_SDCMD8, argument, resp); + err = mmc_send_cmd(MMC_SDCMD8, argument, mmc_resp.resp); hcs_val = (err == 1) ? MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR : MMC_OCR_REG_HOST_CAPACITY_SUPPORT_BYTE; argument = 0x0000 << 16; - err = mmc_send_cmd(MMC_CMD55, argument, resp); + err = mmc_send_cmd(MMC_CMD55, argument, mmc_resp.resp); if (err == 1) { mmc_card_cur->card_type = SD_CARD; ocr_value |= hcs_val; @@ -272,24 +272,24 @@ unsigned char mmc_detect_card(mmc_card_data *mmc_card_cur) } argument = ocr_value; - err = mmc_send_cmd(ret_cmd41, argument, resp); + err = mmc_send_cmd(ret_cmd41, argument, mmc_resp.resp); if (err != 1) return err; - ocr_recvd = ((mmc_resp_r3 *) resp)->ocr; + ocr_recvd = mmc_resp.r3.ocr; while (!(ocr_recvd & (0x1 << 31)) && (retry_cnt > 0)) { retry_cnt--; if (mmc_card_cur->card_type == SD_CARD) { argument = 0x0000 << 16; - err = mmc_send_cmd(MMC_CMD55, argument, resp); + err = mmc_send_cmd(MMC_CMD55, argument, mmc_resp.resp); } argument = ocr_value; - err = mmc_send_cmd(ret_cmd41, argument, resp); + err = mmc_send_cmd(ret_cmd41, argument, mmc_resp.resp); if (err != 1) return err; - ocr_recvd = ((mmc_resp_r3 *) resp)->ocr; + ocr_recvd = mmc_resp.r3.ocr; } if (!(ocr_recvd & (0x1 << 31))) @@ -318,22 +318,22 @@ unsigned char mmc_detect_card(mmc_card_data *mmc_card_cur) if (!(ocr_recvd & ocr_value)) return 0; - err = mmc_send_cmd(MMC_CMD2, argument, resp); + err = mmc_send_cmd(MMC_CMD2, argument, mmc_resp.resp); if (err != 1) return err; if (mmc_card_cur->card_type == MMC_CARD) { argument = mmc_card_cur->RCA << 16; - err = mmc_send_cmd(MMC_CMD3, argument, resp); + err = mmc_send_cmd(MMC_CMD3, argument, mmc_resp.resp); if (err != 1) return err; } else { argument = 0x00000000; - err = mmc_send_cmd(MMC_SDCMD3, argument, resp); + err = mmc_send_cmd(MMC_SDCMD3, argument, mmc_resp.resp); if (err != 1) return err; - mmc_card_cur->RCA = ((mmc_resp_r6 *) resp)->newpublishedrca; + mmc_card_cur->RCA = mmc_resp.r6.newpublishedrca; } writel(readl(&mmc_base->con) & ~OD, &mmc_base->con); @@ -437,10 +437,9 @@ unsigned char configure_mmc(mmc_card_data *mmc_card_cur) { unsigned char ret_val; unsigned int argument; - unsigned int resp[4]; unsigned int trans_clk, trans_fact, trans_unit, retries = 2; - mmc_csd_reg_t Card_CSD; unsigned char trans_speed; + mmc_resp_t mmc_resp; ret_val = mmc_init_setup(); @@ -453,21 +452,16 @@ unsigned char configure_mmc(mmc_card_data *mmc_card_cur) } while ((retries > 0) && (ret_val != 1)); argument = mmc_card_cur->RCA << 16; - ret_val = mmc_send_cmd(MMC_CMD9, argument, resp); + ret_val = mmc_send_cmd(MMC_CMD9, argument, mmc_resp.resp); if (ret_val != 1) return ret_val; - ((unsigned int *) &Card_CSD)[3] = resp[3]; - ((unsigned int *) &Card_CSD)[2] = resp[2]; - ((unsigned int *) &Card_CSD)[1] = resp[1]; - ((unsigned int *) &Card_CSD)[0] = resp[0]; - if (mmc_card_cur->card_type == MMC_CARD) - mmc_card_cur->version = Card_CSD.spec_vers; + mmc_card_cur->version = mmc_resp.Card_CSD.spec_vers; - trans_speed = Card_CSD.tran_speed; + trans_speed = mmc_resp.Card_CSD.tran_speed; - ret_val = mmc_send_cmd(MMC_CMD4, MMC_DSR_DEFAULT << 16, resp); + ret_val = mmc_send_cmd(MMC_CMD4, MMC_DSR_DEFAULT << 16, mmc_resp.resp); if (ret_val != 1) return ret_val; @@ -491,18 +485,18 @@ unsigned char configure_mmc(mmc_card_data *mmc_card_cur) return ret_val; argument = mmc_card_cur->RCA << 16; - ret_val = mmc_send_cmd(MMC_CMD7_SELECT, argument, resp); + ret_val = mmc_send_cmd(MMC_CMD7_SELECT, argument, mmc_resp.resp); if (ret_val != 1) return ret_val; /* Configure the block length to 512 bytes */ argument = MMCSD_SECTOR_SIZE; - ret_val = mmc_send_cmd(MMC_CMD16, argument, resp); + ret_val = mmc_send_cmd(MMC_CMD16, argument, mmc_resp.resp); if (ret_val != 1) return ret_val; /* get the card size in sectors */ - ret_val = mmc_read_cardsize(mmc_card_cur, &Card_CSD); + ret_val = mmc_read_cardsize(mmc_card_cur, &mmc_resp.Card_CSD); if (ret_val != 1) return ret_val; -- cgit v1.1 From 2a6cc97b91997ae485312ac91ffbcea6a89b663a Mon Sep 17 00:00:00 2001 From: Olof Johansson Date: Tue, 29 Sep 2009 10:21:29 -0400 Subject: SMC911X: Add chip auto detection Refactor the smc911x driver to allow for detecting when the chip is missing. I.e. the detect_chip() function is called earlier and will abort gracefully when the Chip ID read returns all 1's. Signed-off-by: Olof Johansson Acked-by: Dirk Behme Acked-by: Ben Warren --- drivers/net/smc911x.c | 14 ++++++++------ drivers/net/smc911x.h | 7 +++++-- 2 files changed, 13 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index 18a729c..b106ec9 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -146,10 +146,9 @@ static void smc911x_enable(struct eth_device *dev) static int smc911x_init(struct eth_device *dev, bd_t * bd) { - printf(DRIVERNAME ": initializing\n"); + struct chip_id *id = dev->priv; - if (smc911x_detect_chip(dev)) - goto err_out; + printf(DRIVERNAME ": detected %s controller\n", id->name); smc911x_reset(dev); @@ -162,9 +161,6 @@ static int smc911x_init(struct eth_device *dev, bd_t * bd) smc911x_enable(dev); return 0; - -err_out: - return -1; } static int smc911x_send(struct eth_device *dev, @@ -268,6 +264,12 @@ int smc911x_initialize(u8 dev_num, int base_addr) dev->recv = smc911x_rx; sprintf(dev->name, "%s-%hu", DRIVERNAME, dev_num); + /* Try to detect chip. Will fail if not present. */ + if (smc911x_detect_chip(dev)) { + free(dev); + return 0; + } + eth_register(dev); return 0; } diff --git a/drivers/net/smc911x.h b/drivers/net/smc911x.h index 053e330..d5bca63 100644 --- a/drivers/net/smc911x.h +++ b/drivers/net/smc911x.h @@ -441,7 +441,10 @@ static int smc911x_detect_chip(struct eth_device *dev) unsigned long val, i; val = smc911x_reg_read(dev, BYTE_TEST); - if (val != 0x87654321) { + if (val == 0xffffffff) { + /* Special case -- no chip present */ + return -1; + } else if (val != 0x87654321) { printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val); return -1; } @@ -455,7 +458,7 @@ static int smc911x_detect_chip(struct eth_device *dev) return -1; } - printf(DRIVERNAME ": detected %s controller\n", chip_ids[i].name); + dev->priv = (void *)&chip_ids[i]; return 0; } -- cgit v1.1 From 4678d674f0cacc983dca7f6b9933cd8291c9797c Mon Sep 17 00:00:00 2001 From: Minkyu Kang Date: Thu, 1 Oct 2009 17:20:08 +0900 Subject: s5pc1xx: support onenand driver This patch includes the onenand driver for s5pc100 Signed-off-by: Minkyu Kang Signed-off-by: Kyungmin Park --- drivers/mtd/onenand/Makefile | 1 + drivers/mtd/onenand/samsung.c | 636 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 637 insertions(+) create mode 100644 drivers/mtd/onenand/samsung.c (limited to 'drivers') diff --git a/drivers/mtd/onenand/Makefile b/drivers/mtd/onenand/Makefile index 1d35a57..2571df0 100644 --- a/drivers/mtd/onenand/Makefile +++ b/drivers/mtd/onenand/Makefile @@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libonenand.a COBJS-$(CONFIG_CMD_ONENAND) := onenand_uboot.o onenand_base.o onenand_bbt.o +COBJS-$(CONFIG_SAMSUNG_ONENAND) += samsung.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/mtd/onenand/samsung.c b/drivers/mtd/onenand/samsung.c new file mode 100644 index 0000000..f2be687 --- /dev/null +++ b/drivers/mtd/onenand/samsung.c @@ -0,0 +1,636 @@ +/* + * S3C64XX/S5PC100 OneNAND driver at U-Boot + * + * Copyright (C) 2008-2009 Samsung Electronics + * Kyungmin Park + * + * Implementation: + * Emulate the pseudo BufferRAM + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#ifdef ONENAND_DEBUG +#define DPRINTK(format, args...) \ +do { \ + printf("%s[%d]: " format "\n", __func__, __LINE__, ##args); \ +} while (0) +#else +#define DPRINTK(...) do { } while (0) +#endif + +#define ONENAND_ERASE_STATUS 0x00 +#define ONENAND_MULTI_ERASE_SET 0x01 +#define ONENAND_ERASE_START 0x03 +#define ONENAND_UNLOCK_START 0x08 +#define ONENAND_UNLOCK_END 0x09 +#define ONENAND_LOCK_START 0x0A +#define ONENAND_LOCK_END 0x0B +#define ONENAND_LOCK_TIGHT_START 0x0C +#define ONENAND_LOCK_TIGHT_END 0x0D +#define ONENAND_UNLOCK_ALL 0x0E +#define ONENAND_OTP_ACCESS 0x12 +#define ONENAND_SPARE_ACCESS_ONLY 0x13 +#define ONENAND_MAIN_ACCESS_ONLY 0x14 +#define ONENAND_ERASE_VERIFY 0x15 +#define ONENAND_MAIN_SPARE_ACCESS 0x16 +#define ONENAND_PIPELINE_READ 0x4000 + +#if defined(CONFIG_S3C64XX) +#define MAP_00 (0x0 << 24) +#define MAP_01 (0x1 << 24) +#define MAP_10 (0x2 << 24) +#define MAP_11 (0x3 << 24) +#elif defined(CONFIG_S5PC1XX) +#define MAP_00 (0x0 << 26) +#define MAP_01 (0x1 << 26) +#define MAP_10 (0x2 << 26) +#define MAP_11 (0x3 << 26) +#endif + +/* read/write of XIP buffer */ +#define CMD_MAP_00(mem_addr) (MAP_00 | ((mem_addr) << 1)) +/* read/write to the memory device */ +#define CMD_MAP_01(mem_addr) (MAP_01 | (mem_addr)) +/* control special functions of the memory device */ +#define CMD_MAP_10(mem_addr) (MAP_10 | (mem_addr)) +/* direct interface(direct access) with the memory device */ +#define CMD_MAP_11(mem_addr) (MAP_11 | ((mem_addr) << 2)) + +struct s3c_onenand { + struct mtd_info *mtd; + void __iomem *base; + void __iomem *ahb_addr; + int bootram_command; + void __iomem *page_buf; + void __iomem *oob_buf; + unsigned int (*mem_addr)(int fba, int fpa, int fsa); + struct samsung_onenand *reg; +}; + +static struct s3c_onenand *onenand; + +static int s3c_read_cmd(unsigned int cmd) +{ + return readl(onenand->ahb_addr + cmd); +} + +static void s3c_write_cmd(int value, unsigned int cmd) +{ + writel(value, onenand->ahb_addr + cmd); +} + +/* + * MEM_ADDR + * + * fba: flash block address + * fpa: flash page address + * fsa: flash sector address + * + * return the buffer address on the memory device + * It will be combined with CMD_MAP_XX + */ +#if defined(CONFIG_S3C64XX) +static unsigned int s3c_mem_addr(int fba, int fpa, int fsa) +{ + return (fba << 12) | (fpa << 6) | (fsa << 4); +} +#elif defined(CONFIG_S5PC1XX) +static unsigned int s3c_mem_addr(int fba, int fpa, int fsa) +{ + return (fba << 13) | (fpa << 7) | (fsa << 5); +} +#endif + +static void s3c_onenand_reset(void) +{ + unsigned long timeout = 0x10000; + int stat; + + writel(ONENAND_MEM_RESET_COLD, &onenand->reg->mem_reset); + while (timeout--) { + stat = readl(&onenand->reg->int_err_stat); + if (stat & RST_CMP) + break; + } + stat = readl(&onenand->reg->int_err_stat); + writel(stat, &onenand->reg->int_err_ack); + + /* Clear interrupt */ + writel(0x0, &onenand->reg->int_err_ack); + /* Clear the ECC status */ + writel(0x0, &onenand->reg->ecc_err_stat); +} + +static unsigned short s3c_onenand_readw(void __iomem *addr) +{ + struct onenand_chip *this = onenand->mtd->priv; + int reg = addr - this->base; + int word_addr = reg >> 1; + int value; + + /* It's used for probing time */ + switch (reg) { + case ONENAND_REG_MANUFACTURER_ID: + return readl(&onenand->reg->manufact_id); + case ONENAND_REG_DEVICE_ID: + return readl(&onenand->reg->device_id); + case ONENAND_REG_VERSION_ID: + return readl(&onenand->reg->flash_ver_id); + case ONENAND_REG_DATA_BUFFER_SIZE: + return readl(&onenand->reg->data_buf_size); + case ONENAND_REG_TECHNOLOGY: + return readl(&onenand->reg->tech); + case ONENAND_REG_SYS_CFG1: + return readl(&onenand->reg->mem_cfg); + + /* Used at unlock all status */ + case ONENAND_REG_CTRL_STATUS: + return 0; + + case ONENAND_REG_WP_STATUS: + return ONENAND_WP_US; + + default: + break; + } + + /* BootRAM access control */ + if (reg < ONENAND_DATARAM && onenand->bootram_command) { + if (word_addr == 0) + return readl(&onenand->reg->manufact_id); + if (word_addr == 1) + return readl(&onenand->reg->device_id); + if (word_addr == 2) + return readl(&onenand->reg->flash_ver_id); + } + + value = s3c_read_cmd(CMD_MAP_11(word_addr)) & 0xffff; + printk(KERN_INFO "s3c_onenand_readw: Illegal access" + " at reg 0x%x, value 0x%x\n", word_addr, value); + return value; +} + +static void s3c_onenand_writew(unsigned short value, void __iomem *addr) +{ + struct onenand_chip *this = onenand->mtd->priv; + int reg = addr - this->base; + int word_addr = reg >> 1; + + /* It's used for probing time */ + switch (reg) { + case ONENAND_REG_SYS_CFG1: + writel(value, &onenand->reg->mem_cfg); + return; + + case ONENAND_REG_START_ADDRESS1: + case ONENAND_REG_START_ADDRESS2: + return; + + /* Lock/lock-tight/unlock/unlock_all */ + case ONENAND_REG_START_BLOCK_ADDRESS: + return; + + default: + break; + } + + /* BootRAM access control */ + if (reg < ONENAND_DATARAM) { + if (value == ONENAND_CMD_READID) { + onenand->bootram_command = 1; + return; + } + if (value == ONENAND_CMD_RESET) { + writel(ONENAND_MEM_RESET_COLD, + &onenand->reg->mem_reset); + onenand->bootram_command = 0; + return; + } + } + + printk(KERN_INFO "s3c_onenand_writew: Illegal access" + " at reg 0x%x, value 0x%x\n", word_addr, value); + + s3c_write_cmd(value, CMD_MAP_11(word_addr)); +} + +static int s3c_onenand_wait(struct mtd_info *mtd, int state) +{ + unsigned int flags = INT_ACT; + unsigned int stat, ecc; + unsigned long timeout = 0x100000; + + switch (state) { + case FL_READING: + flags |= BLK_RW_CMP | LOAD_CMP; + break; + case FL_WRITING: + flags |= BLK_RW_CMP | PGM_CMP; + break; + case FL_ERASING: + flags |= BLK_RW_CMP | ERS_CMP; + break; + case FL_LOCKING: + flags |= BLK_RW_CMP; + break; + default: + break; + } + + while (timeout--) { + stat = readl(&onenand->reg->int_err_stat); + if (stat & flags) + break; + } + + /* To get correct interrupt status in timeout case */ + stat = readl(&onenand->reg->int_err_stat); + writel(stat, &onenand->reg->int_err_ack); + + /* + * In the Spec. it checks the controller status first + * However if you get the correct information in case of + * power off recovery (POR) test, it should read ECC status first + */ + if (stat & LOAD_CMP) { + ecc = readl(&onenand->reg->ecc_err_stat); + if (ecc & ONENAND_ECC_4BIT_UNCORRECTABLE) { + printk(KERN_INFO "%s: ECC error = 0x%04x\n", + __func__, ecc); + mtd->ecc_stats.failed++; + return -EBADMSG; + } + } + + if (stat & (LOCKED_BLK | ERS_FAIL | PGM_FAIL | LD_FAIL_ECC_ERR)) { + printk(KERN_INFO "%s: controller error = 0x%04x\n", + __func__, stat); + if (stat & LOCKED_BLK) + printk(KERN_INFO "%s: it's locked error = 0x%04x\n", + __func__, stat); + + return -EIO; + } + + return 0; +} + +static int s3c_onenand_command(struct mtd_info *mtd, int cmd, + loff_t addr, size_t len) +{ + struct onenand_chip *this = mtd->priv; + unsigned int *m, *s; + int fba, fpa, fsa = 0; + unsigned int mem_addr; + int i, mcount, scount; + int index; + + fba = (int) (addr >> this->erase_shift); + fpa = (int) (addr >> this->page_shift); + fpa &= this->page_mask; + + mem_addr = onenand->mem_addr(fba, fpa, fsa); + + switch (cmd) { + case ONENAND_CMD_READ: + case ONENAND_CMD_READOOB: + case ONENAND_CMD_BUFFERRAM: + ONENAND_SET_NEXT_BUFFERRAM(this); + default: + break; + } + + index = ONENAND_CURRENT_BUFFERRAM(this); + + /* + * Emulate Two BufferRAMs and access with 4 bytes pointer + */ + m = (unsigned int *) onenand->page_buf; + s = (unsigned int *) onenand->oob_buf; + + if (index) { + m += (this->writesize >> 2); + s += (mtd->oobsize >> 2); + } + + mcount = mtd->writesize >> 2; + scount = mtd->oobsize >> 2; + + switch (cmd) { + case ONENAND_CMD_READ: + /* Main */ + for (i = 0; i < mcount; i++) + *m++ = s3c_read_cmd(CMD_MAP_01(mem_addr)); + return 0; + + case ONENAND_CMD_READOOB: + writel(TSRF, &onenand->reg->trans_spare); + /* Main */ + for (i = 0; i < mcount; i++) + *m++ = s3c_read_cmd(CMD_MAP_01(mem_addr)); + + /* Spare */ + for (i = 0; i < scount; i++) + *s++ = s3c_read_cmd(CMD_MAP_01(mem_addr)); + + writel(0, &onenand->reg->trans_spare); + return 0; + + case ONENAND_CMD_PROG: + /* Main */ + for (i = 0; i < mcount; i++) + s3c_write_cmd(*m++, CMD_MAP_01(mem_addr)); + return 0; + + case ONENAND_CMD_PROGOOB: + writel(TSRF, &onenand->reg->trans_spare); + + /* Main - dummy write */ + for (i = 0; i < mcount; i++) + s3c_write_cmd(0xffffffff, CMD_MAP_01(mem_addr)); + + /* Spare */ + for (i = 0; i < scount; i++) + s3c_write_cmd(*s++, CMD_MAP_01(mem_addr)); + + writel(0, &onenand->reg->trans_spare); + return 0; + + case ONENAND_CMD_UNLOCK_ALL: + s3c_write_cmd(ONENAND_UNLOCK_ALL, CMD_MAP_10(mem_addr)); + return 0; + + case ONENAND_CMD_ERASE: + s3c_write_cmd(ONENAND_ERASE_START, CMD_MAP_10(mem_addr)); + return 0; + + case ONENAND_CMD_MULTIBLOCK_ERASE: + s3c_write_cmd(ONENAND_MULTI_ERASE_SET, CMD_MAP_10(mem_addr)); + return 0; + + case ONENAND_CMD_ERASE_VERIFY: + s3c_write_cmd(ONENAND_ERASE_VERIFY, CMD_MAP_10(mem_addr)); + return 0; + + default: + break; + } + + return 0; +} + +static unsigned char *s3c_get_bufferram(struct mtd_info *mtd, int area) +{ + struct onenand_chip *this = mtd->priv; + int index = ONENAND_CURRENT_BUFFERRAM(this); + unsigned char *p; + + if (area == ONENAND_DATARAM) { + p = (unsigned char *) onenand->page_buf; + if (index == 1) + p += this->writesize; + } else { + p = (unsigned char *) onenand->oob_buf; + if (index == 1) + p += mtd->oobsize; + } + + return p; +} + +static int onenand_read_bufferram(struct mtd_info *mtd, loff_t addr, int area, + unsigned char *buffer, int offset, + size_t count) +{ + unsigned char *p; + + p = s3c_get_bufferram(mtd, area); + memcpy(buffer, p + offset, count); + return 0; +} + +static int onenand_write_bufferram(struct mtd_info *mtd, loff_t addr, int area, + const unsigned char *buffer, int offset, + size_t count) +{ + unsigned char *p; + + p = s3c_get_bufferram(mtd, area); + memcpy(p + offset, buffer, count); + return 0; +} + +static int s3c_onenand_bbt_wait(struct mtd_info *mtd, int state) +{ + struct samsung_onenand *reg = (struct samsung_onenand *)onenand->base; + unsigned int flags = INT_ACT | LOAD_CMP; + unsigned int stat; + unsigned long timeout = 0x10000; + + while (timeout--) { + stat = readl(®->int_err_stat); + if (stat & flags) + break; + } + /* To get correct interrupt status in timeout case */ + stat = readl(&onenand->reg->int_err_stat); + writel(stat, &onenand->reg->int_err_ack); + + if (stat & LD_FAIL_ECC_ERR) { + s3c_onenand_reset(); + return ONENAND_BBT_READ_ERROR; + } + + if (stat & LOAD_CMP) { + int ecc = readl(&onenand->reg->ecc_err_stat); + if (ecc & ONENAND_ECC_4BIT_UNCORRECTABLE) { + s3c_onenand_reset(); + return ONENAND_BBT_READ_ERROR; + } + } + + return 0; +} + +static void s3c_onenand_check_lock_status(struct mtd_info *mtd) +{ + struct onenand_chip *this = mtd->priv; + unsigned int block, end; + int tmp; + + end = this->chipsize >> this->erase_shift; + + for (block = 0; block < end; block++) { + tmp = s3c_read_cmd(CMD_MAP_01(onenand->mem_addr(block, 0, 0))); + + if (readl(&onenand->reg->int_err_stat) & LOCKED_BLK) { + printf("block %d is write-protected!\n", block); + writel(LOCKED_BLK, &onenand->reg->int_err_ack); + } + } +} + +static void s3c_onenand_do_lock_cmd(struct mtd_info *mtd, loff_t ofs, + size_t len, int cmd) +{ + struct onenand_chip *this = mtd->priv; + int start, end, start_mem_addr, end_mem_addr; + + start = ofs >> this->erase_shift; + start_mem_addr = onenand->mem_addr(start, 0, 0); + end = start + (len >> this->erase_shift) - 1; + end_mem_addr = onenand->mem_addr(end, 0, 0); + + if (cmd == ONENAND_CMD_LOCK) { + s3c_write_cmd(ONENAND_LOCK_START, CMD_MAP_10(start_mem_addr)); + s3c_write_cmd(ONENAND_LOCK_END, CMD_MAP_10(end_mem_addr)); + } else { + s3c_write_cmd(ONENAND_UNLOCK_START, CMD_MAP_10(start_mem_addr)); + s3c_write_cmd(ONENAND_UNLOCK_END, CMD_MAP_10(end_mem_addr)); + } + + this->wait(mtd, FL_LOCKING); +} + +static void s3c_onenand_unlock_all(struct mtd_info *mtd) +{ + struct onenand_chip *this = mtd->priv; + loff_t ofs = 0; + size_t len = this->chipsize; + + /* FIXME workaround */ + this->subpagesize = mtd->writesize; + mtd->subpage_sft = 0; + + if (this->options & ONENAND_HAS_UNLOCK_ALL) { + /* Write unlock command */ + this->command(mtd, ONENAND_CMD_UNLOCK_ALL, 0, 0); + + /* No need to check return value */ + this->wait(mtd, FL_LOCKING); + + /* Workaround for all block unlock in DDP */ + if (!ONENAND_IS_DDP(this)) { + s3c_onenand_check_lock_status(mtd); + return; + } + + /* All blocks on another chip */ + ofs = this->chipsize >> 1; + len = this->chipsize >> 1; + } + + s3c_onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_UNLOCK); + s3c_onenand_check_lock_status(mtd); +} + +#ifdef CONFIG_S3C64XX +static void s3c_set_width_regs(struct onenand_chip *this) +{ + int dev_id, density; + int fba, fpa, fsa; + int dbs_dfs; + + dev_id = DEVICE_ID0_REG; + + density = (dev_id >> ONENAND_DEVICE_DENSITY_SHIFT) & 0xf; + dbs_dfs = !!(dev_id & ONENAND_DEVICE_IS_DDP); + + fba = density + 7; + if (dbs_dfs) + fba--; /* Decrease the fba */ + fpa = 6; + if (density >= ONENAND_DEVICE_DENSITY_512Mb) + fsa = 2; + else + fsa = 1; + + DPRINTK("FBA %lu, FPA %lu, FSA %lu, DDP %lu", + FBA_WIDTH0_REG, FPA_WIDTH0_REG, FSA_WIDTH0_REG, + DDP_DEVICE_REG); + + DPRINTK("mem_cfg0 0x%lx, sync mode %lu, " + "dev_page_size %lu, BURST LEN %lu", + MEM_CFG0_REG, SYNC_MODE_REG, + DEV_PAGE_SIZE_REG, BURST_LEN0_REG); + + DEV_PAGE_SIZE_REG = 0x1; + + FBA_WIDTH0_REG = fba; + FPA_WIDTH0_REG = fpa; + FSA_WIDTH0_REG = fsa; + DBS_DFS_WIDTH0_REG = dbs_dfs; +} +#endif + +void s3c_onenand_init(struct mtd_info *mtd) +{ + struct onenand_chip *this = mtd->priv; + u32 size = (4 << 10); /* 4 KiB */ + + onenand = malloc(sizeof(struct s3c_onenand)); + if (!onenand) + return; + + onenand->page_buf = malloc(size * sizeof(char)); + if (!onenand->page_buf) + return; + memset(onenand->page_buf, 0xff, size); + + onenand->oob_buf = malloc(128 * sizeof(char)); + if (!onenand->oob_buf) + return; + memset(onenand->oob_buf, 0xff, 128); + + onenand->mtd = mtd; + +#if defined(CONFIG_S3C64XX) + onenand->base = (void *)0x70100000; + onenand->ahb_addr = (void *)0x20000000; +#elif defined(CONFIG_S5PC1XX) + onenand->base = (void *)0xE7100000; + onenand->ahb_addr = (void *)0xB0000000; +#endif + onenand->mem_addr = s3c_mem_addr; + onenand->reg = (struct samsung_onenand *)onenand->base; + + this->read_word = s3c_onenand_readw; + this->write_word = s3c_onenand_writew; + + this->wait = s3c_onenand_wait; + this->bbt_wait = s3c_onenand_bbt_wait; + this->unlock_all = s3c_onenand_unlock_all; + this->command = s3c_onenand_command; + + this->read_bufferram = onenand_read_bufferram; + this->write_bufferram = onenand_write_bufferram; + + this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK; +} -- cgit v1.1 From dd2c9e6a3b67c8ff56694e515e6e3c7baddd8f52 Mon Sep 17 00:00:00 2001 From: Minkyu Kang Date: Thu, 1 Oct 2009 17:20:28 +0900 Subject: s5pc1xx: support serial driver This patch includes the serial driver for s5pc1xx. s5pc1xx uart driver needs own register setting and clock configuration. So, need to special driver. Signed-off-by: Minkyu Kang --- drivers/serial/Makefile | 1 + drivers/serial/serial_s5pc1xx.c | 195 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 196 insertions(+) create mode 100644 drivers/serial/serial_s5pc1xx.c (limited to 'drivers') diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 64882a2..3c77a7c 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -33,6 +33,7 @@ COBJS-$(CONFIG_NS9750_UART) += ns9750_serial.o COBJS-$(CONFIG_SYS_NS16550) += ns16550.o COBJS-$(CONFIG_DRIVER_S3C4510_UART) += s3c4510b_uart.o COBJS-$(CONFIG_S3C64XX) += s3c64xx.o +COBJS-$(CONFIG_S5PC1XX) += serial_s5pc1xx.o COBJS-$(CONFIG_SYS_NS16550_SERIAL) += serial.o COBJS-$(CONFIG_CLPS7111_SERIAL) += serial_clps7111.o COBJS-$(CONFIG_IMX_SERIAL) += serial_imx.o diff --git a/drivers/serial/serial_s5pc1xx.c b/drivers/serial/serial_s5pc1xx.c new file mode 100644 index 0000000..64c1dcc --- /dev/null +++ b/drivers/serial/serial_s5pc1xx.c @@ -0,0 +1,195 @@ +/* + * (C) Copyright 2009 SAMSUNG Electronics + * Minkyu Kang + * Heungjun Kim + * + * based on drivers/serial/s3c64xx.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include + +static inline struct s5pc1xx_uart *s5pc1xx_get_base_uart(int dev_index) +{ + u32 offset = dev_index * sizeof(struct s5pc1xx_uart); + + if (cpu_is_s5pc100()) + return (struct s5pc1xx_uart *)(S5PC100_UART_BASE + offset); + else + return (struct s5pc1xx_uart *)(S5PC110_UART_BASE + offset); +} + +/* + * The coefficient, used to calculate the baudrate on S5PC1XX UARTs is + * calculated as + * C = UBRDIV * 16 + number_of_set_bits_in_UDIVSLOT + * however, section 31.6.11 of the datasheet doesn't recomment using 1 for 1, + * 3 for 2, ... (2^n - 1) for n, instead, they suggest using these constants: + */ +static const int udivslot[] = { + 0, + 0x0080, + 0x0808, + 0x0888, + 0x2222, + 0x4924, + 0x4a52, + 0x54aa, + 0x5555, + 0xd555, + 0xd5d5, + 0xddd5, + 0xdddd, + 0xdfdd, + 0xdfdf, + 0xffdf, +}; + +void serial_setbrg_dev(const int dev_index) +{ + DECLARE_GLOBAL_DATA_PTR; + struct s5pc1xx_uart *const uart = s5pc1xx_get_base_uart(dev_index); + u32 pclk = get_pclk(); + u32 baudrate = gd->baudrate; + u32 val; + + val = pclk / baudrate; + + writel(val / 16 - 1, &uart->ubrdiv); + writel(udivslot[val % 16], &uart->udivslot); +} + +/* + * Initialise the serial port with the given baudrate. The settings + * are always 8 data bits, no parity, 1 stop bit, no start bits. + */ +int serial_init_dev(const int dev_index) +{ + struct s5pc1xx_uart *const uart = s5pc1xx_get_base_uart(dev_index); + + /* reset and enable FIFOs, set triggers to the maximum */ + writel(0, &uart->ufcon); + writel(0, &uart->umcon); + /* 8N1 */ + writel(0x3, &uart->ulcon); + /* No interrupts, no DMA, pure polling */ + writel(0x245, &uart->ucon); + + serial_setbrg_dev(dev_index); + + return 0; +} + +static int serial_err_check(const int dev_index) +{ + struct s5pc1xx_uart *const uart = s5pc1xx_get_base_uart(dev_index); + + if (readl(&uart->uerstat) & 0xf) + return 1; + + return 0; +} + +/* + * Read a single byte from the serial port. Returns 1 on success, 0 + * otherwise. When the function is succesfull, the character read is + * written into its argument c. + */ +int serial_getc_dev(const int dev_index) +{ + struct s5pc1xx_uart *const uart = s5pc1xx_get_base_uart(dev_index); + + /* wait for character to arrive */ + while (!(readl(&uart->utrstat) & 0x1)) { + if (serial_err_check(dev_index)) + return 0; + } + + return (int)(readl(&uart->urxh) & 0xff); +} + +/* + * Output a single byte to the serial port. + */ +void serial_putc_dev(const char c, const int dev_index) +{ + struct s5pc1xx_uart *const uart = s5pc1xx_get_base_uart(dev_index); + + /* wait for room in the tx FIFO */ + while (!(readl(&uart->utrstat) & 0x2)) { + if (serial_err_check(dev_index)) + return; + } + + writel(c, &uart->utxh); + + /* If \n, also do \r */ + if (c == '\n') + serial_putc('\r'); +} + +/* + * Test whether a character is in the RX buffer + */ +int serial_tstc_dev(const int dev_index) +{ + struct s5pc1xx_uart *const uart = s5pc1xx_get_base_uart(dev_index); + + return (int)(readl(&uart->utrstat) & 0x1); +} + +void serial_puts_dev(const char *s, const int dev_index) +{ + while (*s) + serial_putc_dev(*s++, dev_index); +} + +/* Multi serial device functions */ +#define DECLARE_S5P_SERIAL_FUNCTIONS(port) \ +int s5p_serial##port##_init(void) { return serial_init_dev(port); } \ +void s5p_serial##port##_setbrg(void) { serial_setbrg_dev(port); } \ +int s5p_serial##port##_getc(void) { return serial_getc_dev(port); } \ +int s5p_serial##port##_tstc(void) { return serial_tstc_dev(port); } \ +void s5p_serial##port##_putc(const char c) { serial_putc_dev(c, port); } \ +void s5p_serial##port##_puts(const char *s) { serial_puts_dev(s, port); } + +#define INIT_S5P_SERIAL_STRUCTURE(port, name, bus) { \ + name, \ + bus, \ + s5p_serial##port##_init, \ + s5p_serial##port##_setbrg, \ + s5p_serial##port##_getc, \ + s5p_serial##port##_tstc, \ + s5p_serial##port##_putc, \ + s5p_serial##port##_puts, } + +DECLARE_S5P_SERIAL_FUNCTIONS(0); +struct serial_device s5pc1xx_serial0_device = + INIT_S5P_SERIAL_STRUCTURE(0, "s5pser0", "S5PUART0"); +DECLARE_S5P_SERIAL_FUNCTIONS(1); +struct serial_device s5pc1xx_serial1_device = + INIT_S5P_SERIAL_STRUCTURE(1, "s5pser1", "S5PUART1"); +DECLARE_S5P_SERIAL_FUNCTIONS(2); +struct serial_device s5pc1xx_serial2_device = + INIT_S5P_SERIAL_STRUCTURE(2, "s5pser2", "S5PUART2"); +DECLARE_S5P_SERIAL_FUNCTIONS(3); +struct serial_device s5pc1xx_serial3_device = + INIT_S5P_SERIAL_STRUCTURE(3, "s5pser3", "S5PUART3"); -- cgit v1.1 From eb0ae7f549b7142826a8bcdd2dc945fac9c36349 Mon Sep 17 00:00:00 2001 From: "kevin.morfitt@fearnside-systems.co.uk" Date: Sat, 10 Oct 2009 13:33:11 +0900 Subject: Clean-up of s3c24x0 drivers excluding nand driver This patch re-formats the arm920t s3c24x0 driver files, excluding the nand driver, in preparation for changes to add support for the Embest SBC2440-II Board. The changes are as follows: - re-indent the code using Lindent - make sure register layouts are defined using a C struct - replace the upper-case typedef'ed C struct names with lower case non-typedef'ed ones - make sure registers are accessed using the proper accessor functions - run checkpatch.pl and fix any error reports It assumes the following patch has been applied first: - [U-Boot][PATCH-ARM] CONFIG_SYS_HZ fix for ARM902T S3C24X0 Boards, 05/09/2009 - patches 1/4 and 2/4 of this series Tested on an Embest SBC2440-II Board with local u-boot patches as I don't have any s3c2400 or s3c2410 boards but need this patch applying before I can submit patches for the SBC2440-II Board. Also, temporarily modified sbc2410x, smdk2400, smdk2410 and trab configs to use the mtd nand driver (which isn't used by any board at the moment), ran MAKEALL for all ARM9 targets and no new warnings or errors were found. Signed-off-by: Kevin Morfitt Signed-off-by: Minkyu Kang --- drivers/i2c/s3c24x0_i2c.c | 273 ++++++++++++++++++++-------------------- drivers/rtc/s3c24x0_rtc.c | 130 +++++++++---------- drivers/serial/serial_s3c24x0.c | 160 +++++++++++++---------- 3 files changed, 296 insertions(+), 267 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c index f0c1aa3..55c6a12 100644 --- a/drivers/i2c/s3c24x0_i2c.c +++ b/drivers/i2c/s3c24x0_i2c.c @@ -32,6 +32,8 @@ #elif defined(CONFIG_S3C2410) #include #endif + +#include #include #ifdef CONFIG_HARD_I2C @@ -42,142 +44,139 @@ #define I2C_OK 0 #define I2C_NOK 1 #define I2C_NACK 2 -#define I2C_NOK_LA 3 /* Lost arbitration */ -#define I2C_NOK_TOUT 4 /* time out */ - -#define I2CSTAT_BSY 0x20 /* Busy bit */ -#define I2CSTAT_NACK 0x01 /* Nack bit */ -#define I2CCON_IRPND 0x10 /* Interrupt pending bit */ -#define I2C_MODE_MT 0xC0 /* Master Transmit Mode */ -#define I2C_MODE_MR 0x80 /* Master Receive Mode */ -#define I2C_START_STOP 0x20 /* START / STOP */ -#define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */ +#define I2C_NOK_LA 3 /* Lost arbitration */ +#define I2C_NOK_TOUT 4 /* time out */ -#define I2C_TIMEOUT 1 /* 1 second */ +#define I2CSTAT_BSY 0x20 /* Busy bit */ +#define I2CSTAT_NACK 0x01 /* Nack bit */ +#define I2CCON_IRPND 0x10 /* Interrupt pending bit */ +#define I2C_MODE_MT 0xC0 /* Master Transmit Mode */ +#define I2C_MODE_MR 0x80 /* Master Receive Mode */ +#define I2C_START_STOP 0x20 /* START / STOP */ +#define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */ +#define I2C_TIMEOUT 1 /* 1 second */ static int GetI2CSDA(void) { - S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); #ifdef CONFIG_S3C2410 - return (gpio->GPEDAT & 0x8000) >> 15; + return (readl(&gpio->GPEDAT) & 0x8000) >> 15; #endif #ifdef CONFIG_S3C2400 - return (gpio->PGDAT & 0x0020) >> 5; + return (readl(&gpio->PGDAT) & 0x0020) >> 5; #endif } #if 0 static void SetI2CSDA(int x) { - rGPEDAT = (rGPEDAT & ~0x8000) | (x&1) << 15; + rGPEDAT = (rGPEDAT & ~0x8000) | (x & 1) << 15; } #endif static void SetI2CSCL(int x) { - S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); #ifdef CONFIG_S3C2410 - gpio->GPEDAT = (gpio->GPEDAT & ~0x4000) | (x&1) << 14; + writel((readl(&gpio->GPEDAT) & ~0x4000) | (x & 1) << 14, &gpio->GPEDAT); #endif #ifdef CONFIG_S3C2400 - gpio->PGDAT = (gpio->PGDAT & ~0x0040) | (x&1) << 6; + writel((readl(&gpio->PGDAT) & ~0x0040) | (x & 1) << 6, &gpio->PGDAT); #endif } - -static int WaitForXfer (void) +static int WaitForXfer(void) { - S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C (); - int i, status; + struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c(); + int i; i = I2C_TIMEOUT * 10000; - status = i2c->IICCON; - while ((i > 0) && !(status & I2CCON_IRPND)) { - udelay (100); - status = i2c->IICCON; + while (!(readl(&i2c->IICCON) & I2CCON_IRPND) && (i > 0)) { + udelay(100); i--; } - return (status & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT; + return (readl(&i2c->IICCON) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT; } -static int IsACK (void) +static int IsACK(void) { - S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C (); + struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c(); - return (!(i2c->IICSTAT & I2CSTAT_NACK)); + return !(readl(&i2c->IICSTAT) & I2CSTAT_NACK); } -static void ReadWriteByte (void) +static void ReadWriteByte(void) { - S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C (); + struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c(); - i2c->IICCON &= ~I2CCON_IRPND; + writel(readl(&i2c->IICCON) & ~I2CCON_IRPND, &i2c->IICCON); } -void i2c_init (int speed, int slaveadd) +void i2c_init(int speed, int slaveadd) { - S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C (); - S3C24X0_GPIO *const gpio = S3C24X0_GetBase_GPIO (); + struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c(); + struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); ulong freq, pres = 16, div; - int i, status; + int i; /* wait for some time to give previous transfer a chance to finish */ i = I2C_TIMEOUT * 1000; - status = i2c->IICSTAT; - while ((i > 0) && (status & I2CSTAT_BSY)) { - udelay (1000); - status = i2c->IICSTAT; + while ((readl(&i2c->IICSTAT) && I2CSTAT_BSY) && (i > 0)) { + udelay(1000); i--; } - if ((status & I2CSTAT_BSY) || GetI2CSDA () == 0) { + if ((readl(&i2c->IICSTAT) & I2CSTAT_BSY) || GetI2CSDA() == 0) { #ifdef CONFIG_S3C2410 - ulong old_gpecon = gpio->GPECON; + ulong old_gpecon = readl(&gpio->GPECON); #endif #ifdef CONFIG_S3C2400 - ulong old_gpecon = gpio->PGCON; + ulong old_gpecon = readl(&gpio->PGCON); #endif - /* bus still busy probably by (most) previously interrupted transfer */ + /* bus still busy probably by (most) previously interrupted + transfer */ #ifdef CONFIG_S3C2410 /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */ - gpio->GPECON = (gpio->GPECON & ~0xF0000000) | 0x10000000; + writel((readl(&gpio->GPECON) & ~0xF0000000) | 0x10000000, + &gpio->GPECON); #endif #ifdef CONFIG_S3C2400 /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */ - gpio->PGCON = (gpio->PGCON & ~0x00003c00) | 0x00001000; + writel((readl(&gpio->PGCON) & ~0x00003c00) | 0x00001000, + &gpio->PGCON); #endif /* toggle I2CSCL until bus idle */ - SetI2CSCL (0); - udelay (1000); + SetI2CSCL(0); + udelay(1000); i = 10; - while ((i > 0) && (GetI2CSDA () != 1)) { - SetI2CSCL (1); - udelay (1000); - SetI2CSCL (0); - udelay (1000); + while ((i > 0) && (GetI2CSDA() != 1)) { + SetI2CSCL(1); + udelay(1000); + SetI2CSCL(0); + udelay(1000); i--; } - SetI2CSCL (1); - udelay (1000); + SetI2CSCL(1); + udelay(1000); /* restore pin functions */ #ifdef CONFIG_S3C2410 - gpio->GPECON = old_gpecon; + writel(old_gpecon, &gpio->GPECON); #endif #ifdef CONFIG_S3C2400 - gpio->PGCON = old_gpecon; + writel(old_gpecon, &gpio->PGCON); #endif } /* calculate prescaler and divisor values */ - freq = get_PCLK (); + freq = get_PCLK(); if ((freq / pres / (16 + 1)) > speed) /* set prescaler to 512 */ pres = 512; @@ -188,13 +187,13 @@ void i2c_init (int speed, int slaveadd) /* set prescaler, divisor according to freq, also set * ACKGEN, IRQ */ - i2c->IICCON = (div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0); + writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->IICCON); /* init to SLAVE REVEIVE and set slaveaddr */ - i2c->IICSTAT = 0; - i2c->IICADD = slaveadd; + writel(0, &i2c->IICSTAT); + writel(slaveadd, &i2c->IICADD); /* program Master Transmit (and implicit STOP) */ - i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA; + writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->IICSTAT); } @@ -206,107 +205,109 @@ void i2c_init (int speed, int slaveadd) * 0 we skip the address write cycle. */ static -int i2c_transfer (unsigned char cmd_type, - unsigned char chip, - unsigned char addr[], - unsigned char addr_len, - unsigned char data[], unsigned short data_len) +int i2c_transfer(unsigned char cmd_type, + unsigned char chip, + unsigned char addr[], + unsigned char addr_len, + unsigned char data[], unsigned short data_len) { - S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C (); - int i, status, result; + struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c(); + int i, result; if (data == 0 || data_len == 0) { /*Don't support data transfer of no length or to address 0 */ - printf ("i2c_transfer: bad call\n"); + printf("i2c_transfer: bad call\n"); return I2C_NOK; } /* Check I2C bus idle */ i = I2C_TIMEOUT * 1000; - status = i2c->IICSTAT; - while ((i > 0) && (status & I2CSTAT_BSY)) { - udelay (1000); - status = i2c->IICSTAT; + while ((readl(&i2c->IICSTAT) & I2CSTAT_BSY) && (i > 0)) { + udelay(1000); i--; } - if (status & I2CSTAT_BSY) + if (readl(&i2c->IICSTAT) & I2CSTAT_BSY) return I2C_NOK_TOUT; - i2c->IICCON |= 0x80; + writel(readl(&i2c->IICCON) | 0x80, &i2c->IICCON); result = I2C_OK; switch (cmd_type) { case I2C_WRITE: if (addr && addr_len) { - i2c->IICDS = chip; + writel(chip, &i2c->IICDS); /* send START */ - i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP; + writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP, + &i2c->IICSTAT); i = 0; while ((i < addr_len) && (result == I2C_OK)) { - result = WaitForXfer (); - i2c->IICDS = addr[i]; - ReadWriteByte (); + result = WaitForXfer(); + writel(addr[i], &i2c->IICDS); + ReadWriteByte(); i++; } i = 0; while ((i < data_len) && (result == I2C_OK)) { - result = WaitForXfer (); - i2c->IICDS = data[i]; - ReadWriteByte (); + result = WaitForXfer(); + writel(data[i], &i2c->IICDS); + ReadWriteByte(); i++; } } else { - i2c->IICDS = chip; + writel(chip, &i2c->IICDS); /* send START */ - i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP; + writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP, + &i2c->IICSTAT); i = 0; while ((i < data_len) && (result = I2C_OK)) { - result = WaitForXfer (); - i2c->IICDS = data[i]; - ReadWriteByte (); + result = WaitForXfer(); + writel(data[i], &i2c->IICDS); + ReadWriteByte(); i++; } } if (result == I2C_OK) - result = WaitForXfer (); + result = WaitForXfer(); /* send STOP */ - i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA; - ReadWriteByte (); + writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT); + ReadWriteByte(); break; case I2C_READ: if (addr && addr_len) { - i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA; - i2c->IICDS = chip; + writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->IICSTAT); + writel(chip, &i2c->IICDS); /* send START */ - i2c->IICSTAT |= I2C_START_STOP; - result = WaitForXfer (); - if (IsACK ()) { + writel(readl(&i2c->IICSTAT) | I2C_START_STOP, + &i2c->IICSTAT); + result = WaitForXfer(); + if (IsACK()) { i = 0; while ((i < addr_len) && (result == I2C_OK)) { - i2c->IICDS = addr[i]; - ReadWriteByte (); - result = WaitForXfer (); + writel(addr[i], &i2c->IICDS); + ReadWriteByte(); + result = WaitForXfer(); i++; } - i2c->IICDS = chip; + writel(chip, &i2c->IICDS); /* resend START */ - i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA | - I2C_START_STOP; - ReadWriteByte (); - result = WaitForXfer (); + writel(I2C_MODE_MR | I2C_TXRX_ENA | + I2C_START_STOP, &i2c->IICSTAT); + ReadWriteByte(); + result = WaitForXfer(); i = 0; while ((i < data_len) && (result == I2C_OK)) { /* disable ACK for final READ */ if (i == data_len - 1) - i2c->IICCON &= ~0x80; - ReadWriteByte (); - result = WaitForXfer (); - data[i] = i2c->IICDS; + writel(readl(&i2c->IICCON) + & ~0x80, &i2c->IICCON); + ReadWriteByte(); + result = WaitForXfer(); + data[i] = readl(&i2c->IICDS); i++; } } else { @@ -314,21 +315,23 @@ int i2c_transfer (unsigned char cmd_type, } } else { - i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA; - i2c->IICDS = chip; + writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT); + writel(chip, &i2c->IICDS); /* send START */ - i2c->IICSTAT |= I2C_START_STOP; - result = WaitForXfer (); + writel(readl(&i2c->IICSTAT) | I2C_START_STOP, + &i2c->IICSTAT); + result = WaitForXfer(); - if (IsACK ()) { + if (IsACK()) { i = 0; while ((i < data_len) && (result == I2C_OK)) { /* disable ACK for final READ */ if (i == data_len - 1) - i2c->IICCON &= ~0x80; - ReadWriteByte (); - result = WaitForXfer (); - data[i] = i2c->IICDS; + writel(readl(&i2c->IICCON) & + ~0x80, &i2c->IICCON); + ReadWriteByte(); + result = WaitForXfer(); + data[i] = readl(&i2c->IICDS); i++; } } else { @@ -337,12 +340,12 @@ int i2c_transfer (unsigned char cmd_type, } /* send STOP */ - i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA; - ReadWriteByte (); + writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT); + ReadWriteByte(); break; default: - printf ("i2c_transfer: bad call\n"); + printf("i2c_transfer: bad call\n"); result = I2C_NOK; break; } @@ -350,7 +353,7 @@ int i2c_transfer (unsigned char cmd_type, return (result); } -int i2c_probe (uchar chip) +int i2c_probe(uchar chip) { uchar buf[1]; @@ -361,16 +364,16 @@ int i2c_probe (uchar chip) * address was ed (i.e. there was a chip at that address which * drove the data line low). */ - return (i2c_transfer (I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK); + return i2c_transfer(I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK; } -int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len) +int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) { uchar xaddr[4]; int ret; if (alen > 4) { - printf ("I2C read: addr len %d not supported\n", alen); + printf("I2C read: addr len %d not supported\n", alen); return 1; } @@ -394,23 +397,24 @@ int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len) * hidden in the chip address. */ if (alen > 0) - chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); + chip |= ((addr >> (alen * 8)) & + CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); #endif if ((ret = - i2c_transfer (I2C_READ, chip << 1, &xaddr[4 - alen], alen, - buffer, len)) != 0) { - printf ("I2c read: failed %d\n", ret); + i2c_transfer(I2C_READ, chip << 1, &xaddr[4 - alen], alen, + buffer, len)) != 0) { + printf("I2c read: failed %d\n", ret); return 1; } return 0; } -int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len) +int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) { uchar xaddr[4]; if (alen > 4) { - printf ("I2C write: addr len %d not supported\n", alen); + printf("I2C write: addr len %d not supported\n", alen); return 1; } @@ -433,10 +437,11 @@ int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len) * hidden in the chip address. */ if (alen > 0) - chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); + chip |= ((addr >> (alen * 8)) & + CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); #endif return (i2c_transfer (I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer, len) != 0); } -#endif /* CONFIG_HARD_I2C */ +#endif /* CONFIG_HARD_I2C */ diff --git a/drivers/rtc/s3c24x0_rtc.c b/drivers/rtc/s3c24x0_rtc.c index e10db9a..1ce34e3 100644 --- a/drivers/rtc/s3c24x0_rtc.c +++ b/drivers/rtc/s3c24x0_rtc.c @@ -37,6 +37,7 @@ #endif #include +#include /*#define DEBUG*/ @@ -48,112 +49,113 @@ typedef enum { static inline void SetRTC_Access(RTC_ACCESS a) { - S3C24X0_RTC * const rtc = S3C24X0_GetBase_RTC(); + struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc(); + switch (a) { - case RTC_ENABLE: - rtc->RTCCON |= 0x01; break; + case RTC_ENABLE: + writeb(readb(&rtc->RTCCON) | 0x01, &rtc->RTCCON); + break; - case RTC_DISABLE: - rtc->RTCCON &= ~0x01; break; + case RTC_DISABLE: + writeb(readb(&rtc->RTCCON) & ~0x01, &rtc->RTCCON); + break; } } /* ------------------------------------------------------------------------- */ -int rtc_get (struct rtc_time *tmp) +int rtc_get(struct rtc_time *tmp) { - S3C24X0_RTC * const rtc = S3C24X0_GetBase_RTC(); + struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc(); uchar sec, min, hour, mday, wday, mon, year; - uchar a_sec,a_min, a_hour, a_date, a_mon, a_year, a_armed; + uchar a_sec, a_min, a_hour, a_date, a_mon, a_year, a_armed; /* enable access to RTC registers */ SetRTC_Access(RTC_ENABLE); /* read RTC registers */ do { - sec = rtc->BCDSEC; - min = rtc->BCDMIN; - hour = rtc->BCDHOUR; - mday = rtc->BCDDATE; - wday = rtc->BCDDAY; - mon = rtc->BCDMON; - year = rtc->BCDYEAR; - } while (sec != rtc->BCDSEC); + sec = readb(&rtc->BCDSEC); + min = readb(&rtc->BCDMIN); + hour = readb(&rtc->BCDHOUR); + mday = readb(&rtc->BCDDATE); + wday = readb(&rtc->BCDDAY); + mon = readb(&rtc->BCDMON); + year = readb(&rtc->BCDYEAR); + } while (sec != readb(&rtc->BCDSEC)); /* read ALARM registers */ - a_sec = rtc->ALMSEC; - a_min = rtc->ALMMIN; - a_hour = rtc->ALMHOUR; - a_date = rtc->ALMDATE; - a_mon = rtc->ALMMON; - a_year = rtc->ALMYEAR; - a_armed = rtc->RTCALM; + a_sec = readb(&rtc->ALMSEC); + a_min = readb(&rtc->ALMMIN); + a_hour = readb(&rtc->ALMHOUR); + a_date = readb(&rtc->ALMDATE); + a_mon = readb(&rtc->ALMMON); + a_year = readb(&rtc->ALMYEAR); + a_armed = readb(&rtc->RTCALM); /* disable access to RTC registers */ SetRTC_Access(RTC_DISABLE); #ifdef RTC_DEBUG - printf ( "Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x " - "hr: %02x min: %02x sec: %02x\n", - year, mon, mday, wday, - hour, min, sec); - printf ( "Alarms: %02x: year: %02x month: %02x date: %02x hour: %02x min: %02x sec: %02x\n", - a_armed, - a_year, a_mon, a_date, - a_hour, a_min, a_sec); + printf("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x " + "hr: %02x min: %02x sec: %02x\n", + year, mon, mday, wday, hour, min, sec); + printf("Alarms: %02x: year: %02x month: %02x date: %02x hour: " + "%02x min: %02x sec: %02x\n", + a_armed, a_year, a_mon, a_date, a_hour, a_min, a_sec); #endif - tmp->tm_sec = bcd2bin(sec & 0x7F); - tmp->tm_min = bcd2bin(min & 0x7F); + tmp->tm_sec = bcd2bin(sec & 0x7F); + tmp->tm_min = bcd2bin(min & 0x7F); tmp->tm_hour = bcd2bin(hour & 0x3F); tmp->tm_mday = bcd2bin(mday & 0x3F); tmp->tm_mon = bcd2bin(mon & 0x1F); tmp->tm_year = bcd2bin(year); tmp->tm_wday = bcd2bin(wday & 0x07); - if(tmp->tm_year<70) - tmp->tm_year+=2000; + if (tmp->tm_year < 70) + tmp->tm_year += 2000; else - tmp->tm_year+=1900; - tmp->tm_yday = 0; - tmp->tm_isdst= 0; + tmp->tm_year += 1900; + tmp->tm_yday = 0; + tmp->tm_isdst = 0; #ifdef RTC_DEBUG - printf ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + printf("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); #endif return 0; } -int rtc_set (struct rtc_time *tmp) +int rtc_set(struct rtc_time *tmp) { - S3C24X0_RTC * const rtc = S3C24X0_GetBase_RTC(); + struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc(); uchar sec, min, hour, mday, wday, mon, year; #ifdef RTC_DEBUG - printf ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + printf("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); #endif - year = bin2bcd(tmp->tm_year % 100); - mon = bin2bcd(tmp->tm_mon); - wday = bin2bcd(tmp->tm_wday); - mday = bin2bcd(tmp->tm_mday); - hour = bin2bcd(tmp->tm_hour); - min = bin2bcd(tmp->tm_min); - sec = bin2bcd(tmp->tm_sec); + year = bin2bcd(tmp->tm_year % 100); + mon = bin2bcd(tmp->tm_mon); + wday = bin2bcd(tmp->tm_wday); + mday = bin2bcd(tmp->tm_mday); + hour = bin2bcd(tmp->tm_hour); + min = bin2bcd(tmp->tm_min); + sec = bin2bcd(tmp->tm_sec); /* enable access to RTC registers */ SetRTC_Access(RTC_ENABLE); /* write RTC registers */ - rtc->BCDSEC = sec; - rtc->BCDMIN = min; - rtc->BCDHOUR = hour; - rtc->BCDDATE = mday; - rtc->BCDDAY = wday; - rtc->BCDMON = mon; - rtc->BCDYEAR = year; + writeb(sec, &rtc->BCDSEC); + writeb(min, &rtc->BCDMIN); + writeb(hour, &rtc->BCDHOUR); + writeb(mday, &rtc->BCDDATE); + writeb(wday, &rtc->BCDDAY); + writeb(mon, &rtc->BCDMON); + writeb(year, &rtc->BCDYEAR); /* disable access to RTC registers */ SetRTC_Access(RTC_DISABLE); @@ -161,12 +163,12 @@ int rtc_set (struct rtc_time *tmp) return 0; } -void rtc_reset (void) +void rtc_reset(void) { - S3C24X0_RTC * const rtc = S3C24X0_GetBase_RTC(); + struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc(); - rtc->RTCCON = (rtc->RTCCON & ~0x06) | 0x08; - rtc->RTCCON &= ~(0x08|0x01); + writeb((readb(&rtc->RTCCON) & ~0x06) | 0x08, &rtc->RTCCON); + writeb(readb(&rtc->RTCCON) & ~(0x08 | 0x01), &rtc->RTCCON); } #endif diff --git a/drivers/serial/serial_s3c24x0.c b/drivers/serial/serial_s3c24x0.c index 6d69c43..c2c72e4 100644 --- a/drivers/serial/serial_s3c24x0.c +++ b/drivers/serial/serial_s3c24x0.c @@ -38,7 +38,7 @@ DECLARE_GLOBAL_DATA_PTR; #elif defined(CONFIG_SERIAL3) # if defined(CONFIG_TRAB) -# #error "TRAB supports only CONFIG_SERIAL1" +# error "TRAB supports only CONFIG_SERIAL1" # endif #define UART_NR S3C24X0_UART2 @@ -46,51 +46,71 @@ DECLARE_GLOBAL_DATA_PTR; #error "Bad: you didn't configure serial ..." #endif +#include + #if defined(CONFIG_SERIAL_MULTI) #include /* Multi serial device functions */ #define DECLARE_S3C_SERIAL_FUNCTIONS(port) \ - int s3serial##port##_init (void) {\ - return serial_init_dev(port);}\ - void s3serial##port##_setbrg (void) {\ - serial_setbrg_dev(port);}\ - int s3serial##port##_getc (void) {\ - return serial_getc_dev(port);}\ - int s3serial##port##_tstc (void) {\ - return serial_tstc_dev(port);}\ - void s3serial##port##_putc (const char c) {\ - serial_putc_dev(port, c);}\ - void s3serial##port##_puts (const char *s) {\ - serial_puts_dev(port, s);} - -#define INIT_S3C_SERIAL_STRUCTURE(port,name,bus) {\ - name,\ - bus,\ - s3serial##port##_init,\ - s3serial##port##_setbrg,\ - s3serial##port##_getc,\ - s3serial##port##_tstc,\ - s3serial##port##_putc,\ - s3serial##port##_puts, } + int s3serial##port##_init(void) \ + { \ + return serial_init_dev(port); \ + } \ + void s3serial##port##_setbrg(void) \ + { \ + serial_setbrg_dev(port); \ + } \ + int s3serial##port##_getc(void) \ + { \ + return serial_getc_dev(port); \ + } \ + int s3serial##port##_tstc(void) \ + { \ + return serial_tstc_dev(port); \ + } \ + void s3serial##port##_putc(const char c) \ + { \ + serial_putc_dev(port, c); \ + } \ + void s3serial##port##_puts(const char *s) \ + { \ + serial_puts_dev(port, s); \ + } + +#define INIT_S3C_SERIAL_STRUCTURE(port, name, bus) { \ + name, \ + bus, \ + s3serial##port##_init, \ + s3serial##port##_setbrg, \ + s3serial##port##_getc, \ + s3serial##port##_tstc, \ + s3serial##port##_putc, \ + s3serial##port##_puts, \ +} #endif /* CONFIG_SERIAL_MULTI */ +#ifdef CONFIG_HWFLOW +static int hwflow; +#endif + void _serial_setbrg(const int dev_index) { - S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index); + struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index); unsigned int reg = 0; int i; /* value is calculated so : (int)(PCLK/16./baudrate) -1 */ reg = get_PCLK() / (16 * gd->baudrate) - 1; - uart->UBRDIV = reg; - for (i = 0; i < 100; i++); + writel(reg, &uart->UBRDIV); + for (i = 0; i < 100; i++) + /* Delay */ ; } + #if defined(CONFIG_SERIAL_MULTI) -static inline void -serial_setbrg_dev(unsigned int dev_index) +static inline void serial_setbrg_dev(unsigned int dev_index) { _serial_setbrg(dev_index); } @@ -107,29 +127,33 @@ void serial_setbrg(void) */ static int serial_init_dev(const int dev_index) { - S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index); + struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index); + +#ifdef CONFIG_HWFLOW + hwflow = 0; /* turned off by default */ +#endif /* FIFO enable, Tx/Rx FIFO clear */ - uart->UFCON = 0x07; - uart->UMCON = 0x0; + writel(0x07, &uart->UFCON); + writel(0x0, &uart->UMCON); /* Normal,No parity,1 stop,8 bit */ - uart->ULCON = 0x3; + writel(0x3, &uart->ULCON); /* * tx=level,rx=edge,disable timeout int.,enable rx error int., * normal,interrupt or polling */ - uart->UCON = 0x245; + writel(0x245, &uart->UCON); #ifdef CONFIG_HWFLOW - uart->UMCON = 0x1; /* RTS up */ + writel(0x1, &uart->UMCON); /* RTS up */ #endif /* FIXME: This is sooooooooooooooooooo ugly */ #if defined(CONFIG_ARCH_GTA02_v1) || defined(CONFIG_ARCH_GTA02_v2) /* we need auto hw flow control on the gsm and gps port */ if (dev_index == 0 || dev_index == 1) - uart->UMCON = 0x10; + writel(0x10, &uart->UMCON); #endif _serial_setbrg(dev_index); @@ -140,7 +164,7 @@ static int serial_init_dev(const int dev_index) /* Initialise the serial port. The settings are always 8 data bits, no parity, * 1 stop bit, no start bits. */ -int serial_init (void) +int serial_init(void) { return serial_init_dev(UART_NR); } @@ -151,40 +175,40 @@ int serial_init (void) * otherwise. When the function is succesfull, the character read is * written into its argument c. */ -int _serial_getc (const int dev_index) +int _serial_getc(const int dev_index) { - S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index); + struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index); - /* wait for character to arrive */ - while (!(uart->UTRSTAT & 0x1)); + while (!(readl(&uart->UTRSTAT) & 0x1)) + /* wait for character to arrive */ ; - return uart->URXH & 0xff; + return readb(&uart->URXH) & 0xff; } + #if defined(CONFIG_SERIAL_MULTI) static inline int serial_getc_dev(unsigned int dev_index) { return _serial_getc(dev_index); } #else -int serial_getc (void) +int serial_getc(void) { return _serial_getc(UART_NR); } #endif #ifdef CONFIG_HWFLOW -static int hwflow = 0; /* turned off by default */ int hwflow_onoff(int on) { - switch(on) { + switch (on) { case 0: default: - break; /* return current */ + break; /* return current */ case 1: - hwflow = 1; /* turn on */ + hwflow = 1; /* turn on */ break; case -1: - hwflow = 0; /* turn off */ + hwflow = 0; /* turn off */ break; } return hwflow; @@ -208,29 +232,29 @@ void enable_putc(void) /* * Output a single byte to the serial port. */ -void _serial_putc (const char c, const int dev_index) +void _serial_putc(const char c, const int dev_index) { - S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index); + struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index); #ifdef CONFIG_MODEM_SUPPORT if (be_quiet) return; #endif - /* wait for room in the tx FIFO */ - while (!(uart->UTRSTAT & 0x2)); + while (!(readl(&uart->UTRSTAT) & 0x2)) + /* wait for room in the tx FIFO */ ; #ifdef CONFIG_HWFLOW - /* Wait for CTS up */ - while(hwflow && !(uart->UMSTAT & 0x1)) - ; + while (hwflow && !(readl(&uart->UMSTAT) & 0x1)) + /* Wait for CTS up */ ; #endif - uart->UTXH = c; + writeb(c, &uart->UTXH); /* If \n, also do \r */ if (c == '\n') - serial_putc ('\r'); + serial_putc('\r'); } + #if defined(CONFIG_SERIAL_MULTI) static inline void serial_putc_dev(unsigned int dev_index, const char c) { @@ -249,13 +273,13 @@ void serial_putc(const char c) */ int _serial_tstc(const int dev_index) { - S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index); + struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index); - return uart->UTRSTAT & 0x1; + return readl(&uart->UTRSTAT) & 0x1; } + #if defined(CONFIG_SERIAL_MULTI) -static inline int -serial_tstc_dev(unsigned int dev_index) +static inline int serial_tstc_dev(unsigned int dev_index) { return _serial_tstc(dev_index); } @@ -269,18 +293,17 @@ int serial_tstc(void) void _serial_puts(const char *s, const int dev_index) { while (*s) { - _serial_putc (*s++, dev_index); + _serial_putc(*s++, dev_index); } } + #if defined(CONFIG_SERIAL_MULTI) -static inline void -serial_puts_dev(int dev_index, const char *s) +static inline void serial_puts_dev(int dev_index, const char *s) { _serial_puts(s, dev_index); } #else -void -serial_puts (const char *s) +void serial_puts(const char *s) { _serial_puts(s, UART_NR); } @@ -289,12 +312,11 @@ serial_puts (const char *s) #if defined(CONFIG_SERIAL_MULTI) DECLARE_S3C_SERIAL_FUNCTIONS(0); struct serial_device s3c24xx_serial0_device = - INIT_S3C_SERIAL_STRUCTURE(0, "s3ser0", "S3UART1"); +INIT_S3C_SERIAL_STRUCTURE(0, "s3ser0", "S3UART1"); DECLARE_S3C_SERIAL_FUNCTIONS(1); struct serial_device s3c24xx_serial1_device = - INIT_S3C_SERIAL_STRUCTURE(1, "s3ser1", "S3UART2"); +INIT_S3C_SERIAL_STRUCTURE(1, "s3ser1", "S3UART2"); DECLARE_S3C_SERIAL_FUNCTIONS(2); struct serial_device s3c24xx_serial2_device = - INIT_S3C_SERIAL_STRUCTURE(2, "s3ser2", "S3UART3"); - +INIT_S3C_SERIAL_STRUCTURE(2, "s3ser2", "S3UART3"); #endif /* CONFIG_SERIAL_MULTI */ -- cgit v1.1 From 3d1988ab47cc0e265272967e07d747ec600a44c9 Mon Sep 17 00:00:00 2001 From: "kevin.morfitt@fearnside-systems.co.uk" Date: Sat, 10 Oct 2009 13:34:09 +0900 Subject: Clean-up of s3c24x0 nand driver This patch re-formats the arm920t s3c24x0 nand driver in preparation for changes to add support for the Embest SBC2440-II Board. The changes are as follows: - re-indent the code using Lindent - make sure register layouts are defined using a C struct - replace the upper-case typedef'ed C struct names with lower case non-typedef'ed ones - make sure registers are accessed using the proper accessor functions - run checkpatch.pl and fix any error reports It assumes the following patch has been applied first: - [U-Boot][PATCH-ARM] CONFIG_SYS_HZ fix for ARM902T S3C24X0 Boards, 05/09/2009 - patches 1/4, 2/4 and 3/4 of this series Tested on an Embest SBC2440-II Board with local u-boot patches as I don't have any s3c2400 or s3c2410 boards but need this patch applying before I can submit patches for the SBC2440-II Board. Also, temporarily modified sbc2410x, smdk2400, smdk2410 and trab configs to use the mtd nand driver (which isn't used by any board at the moment), ran MAKEALL for all ARM9 targets and no new warnings or errors were found. Signed-off-by: Kevin Morfitt Signed-off-by: Minkyu Kang --- drivers/mtd/nand/s3c2410_nand.c | 62 +++++++++++++++++------------------------ 1 file changed, 25 insertions(+), 37 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/s3c2410_nand.c b/drivers/mtd/nand/s3c2410_nand.c index d27a625..f2f3e72 100644 --- a/drivers/mtd/nand/s3c2410_nand.c +++ b/drivers/mtd/nand/s3c2410_nand.c @@ -20,29 +20,10 @@ #include -#if 0 -#define DEBUGN printf -#else -#define DEBUGN(x, args ...) {} -#endif - #include #include #include -#define __REGb(x) (*(volatile unsigned char *)(x)) -#define __REGi(x) (*(volatile unsigned int *)(x)) - -#define NF_BASE 0x4e000000 -#define NFCONF __REGi(NF_BASE + 0x0) -#define NFCMD __REGb(NF_BASE + 0x4) -#define NFADDR __REGb(NF_BASE + 0x8) -#define NFDATA __REGb(NF_BASE + 0xc) -#define NFSTAT __REGb(NF_BASE + 0x10) -#define NFECC0 __REGb(NF_BASE + 0x14) -#define NFECC1 __REGb(NF_BASE + 0x15) -#define NFECC2 __REGb(NF_BASE + 0x16) - #define S3C2410_NFCONF_EN (1<<15) #define S3C2410_NFCONF_512BYTE (1<<14) #define S3C2410_NFCONF_4STEP (1<<13) @@ -58,11 +39,12 @@ static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) { struct nand_chip *chip = mtd->priv; + struct s3c2410_nand *nand = s3c2410_get_base_nand(); - DEBUGN("hwcontrol(): 0x%02x 0x%02x\n", cmd, ctrl); + debugX(1, "hwcontrol(): 0x%02x 0x%02x\n", cmd, ctrl); if (ctrl & NAND_CTRL_CHANGE) { - ulong IO_ADDR_W = NF_BASE; + ulong IO_ADDR_W = (ulong)nand; if (!(ctrl & NAND_CLE)) IO_ADDR_W |= S3C2410_ADDR_NCLE; @@ -72,9 +54,11 @@ static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) chip->IO_ADDR_W = (void *)IO_ADDR_W; if (ctrl & NAND_NCE) - NFCONF &= ~S3C2410_NFCONF_nFCE; + writel(readl(&nand->NFCONF) & ~S3C2410_NFCONF_nFCE, + &nand->NFCONF); else - NFCONF |= S3C2410_NFCONF_nFCE; + writel(readl(&nand->NFCONF) | S3C2410_NFCONF_nFCE, + &nand->NFCONF); } if (cmd != NAND_CMD_NONE) @@ -83,15 +67,17 @@ static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) static int s3c2410_dev_ready(struct mtd_info *mtd) { - DEBUGN("dev_ready\n"); - return (NFSTAT & 0x01); + struct s3c2410_nand *nand = s3c2410_get_base_nand(); + debugX(1, "dev_ready\n"); + return readl(&nand->NFSTAT) & 0x01; } #ifdef CONFIG_S3C2410_NAND_HWECC void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode) { - DEBUGN("s3c2410_nand_enable_hwecc(%p, %d)\n", mtd, mode); - NFCONF |= S3C2410_NFCONF_INITECC; + struct s3c2410_nand *nand = s3c2410_get_base_nand(); + debugX(1, "s3c2410_nand_enable_hwecc(%p, %d)\n", mtd, mode); + writel(readl(&nand->NFCONF) | S3C2410_NFCONF_INITECC, &nand->NFCONF); } static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, @@ -100,8 +86,8 @@ static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, ecc_code[0] = NFECC0; ecc_code[1] = NFECC1; ecc_code[2] = NFECC2; - DEBUGN("s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n", - mtd , ecc_code[0], ecc_code[1], ecc_code[2]); + debugX(1, "s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n", + mtd , ecc_code[0], ecc_code[1], ecc_code[2]); return 0; } @@ -123,24 +109,26 @@ int board_nand_init(struct nand_chip *nand) { u_int32_t cfg; u_int8_t tacls, twrph0, twrph1; - S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); + struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); + struct s3c2410_nand *nand_reg = s3c2410_get_base_nand(); - DEBUGN("board_nand_init()\n"); + debugX(1, "board_nand_init()\n"); - clk_power->CLKCON |= (1 << 4); + writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON); /* initialize hardware */ - twrph0 = 3; twrph1 = 0; tacls = 0; + twrph0 = 3; + twrph1 = 0; + tacls = 0; cfg = S3C2410_NFCONF_EN; cfg |= S3C2410_NFCONF_TACLS(tacls - 1); cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1); cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1); - - NFCONF = cfg; + writel(cfg, &nand_reg->NFCONF); /* initialize nand_chip data structure */ - nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)0x4e00000c; + nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)&nand_reg->NFDATA; /* read_buf and write_buf are default */ /* read_byte and write_byte are default */ @@ -165,7 +153,7 @@ int board_nand_init(struct nand_chip *nand) nand->options = 0; #endif - DEBUGN("end of nand_init\n"); + debugX(1, "end of nand_init\n"); return 0; } -- cgit v1.1 From f3807374787e4394efb767e2e8527887f57e51b8 Mon Sep 17 00:00:00 2001 From: Minkyu Kang Date: Thu, 15 Oct 2009 11:19:15 +0900 Subject: s5pc1xx: SMDKC100: fix compile warnings fix the following compile warnings warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Minkyu Kang --- drivers/serial/serial_s5pc1xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/serial/serial_s5pc1xx.c b/drivers/serial/serial_s5pc1xx.c index 64c1dcc..68c06a9 100644 --- a/drivers/serial/serial_s5pc1xx.c +++ b/drivers/serial/serial_s5pc1xx.c @@ -74,7 +74,7 @@ void serial_setbrg_dev(const int dev_index) val = pclk / baudrate; writel(val / 16 - 1, &uart->ubrdiv); - writel(udivslot[val % 16], &uart->udivslot); + writew(udivslot[val % 16], &uart->udivslot); } /* -- cgit v1.1 From 4bc3d2afb380e78fdbb9c501d9a8da6d59eb178e Mon Sep 17 00:00:00 2001 From: Steve Sakoman Date: Tue, 20 Oct 2009 18:21:18 +0200 Subject: ARM: OMAP3: Refactors the SM911x driver Move the test up in the function to not hang on systems without ethernet. Signed-off-by: Steve Sakoman Acked-by: Ben Warren --- drivers/net/smc911x.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index b106ec9..df73478 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -249,6 +249,12 @@ int smc911x_initialize(u8 dev_num, int base_addr) dev->iobase = base_addr; + /* Try to detect chip. Will fail if not present. */ + if (smc911x_detect_chip(dev)) { + free(dev); + return 0; + } + addrh = smc911x_get_mac_csr(dev, ADDRH); addrl = smc911x_get_mac_csr(dev, ADDRL); dev->enetaddr[0] = addrl; @@ -264,12 +270,6 @@ int smc911x_initialize(u8 dev_num, int base_addr) dev->recv = smc911x_rx; sprintf(dev->name, "%s-%hu", DRIVERNAME, dev_num); - /* Try to detect chip. Will fail if not present. */ - if (smc911x_detect_chip(dev)) { - free(dev); - return 0; - } - eth_register(dev); return 0; } -- cgit v1.1