From db5b7f566e513dc1b7f364102010558e5ae7e14f Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 25 Aug 2014 13:34:16 -0300 Subject: net: fec_mxc: Adjust RX DMA alignment for mx6solox mx6solox has a requirement for 64 bytes alignment for RX DMA transfer. Other SoCs work with the standard 32 bytes alignment. Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers, which addresses the needs from mx6solox and also works for the other SoCs. Signed-off-by: Fabio Estevam Acked-by: Marek Vasut --- drivers/net/fec_mxc.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'drivers/net') diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 4cefda4..d310016 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -28,6 +28,14 @@ DECLARE_GLOBAL_DATA_PTR; */ #define FEC_XFER_TIMEOUT 5000 +/* + * The standard 32-byte DMA alignment does not work on mx6solox, which requires + * 64-byte alignment in the DMA RX FEC buffer. + * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also + * satisfies the alignment on other SoCs (32-bytes) + */ +#define FEC_DMA_RX_MINALIGN 64 + #ifndef CONFIG_MII #error "CONFIG_MII has to be defined!" #endif @@ -881,9 +889,9 @@ static int fec_alloc_descs(struct fec_priv *fec) /* Allocate RX buffers. */ /* Maximum RX buffer size. */ - size = roundup(FEC_MAX_PKT_SIZE, ARCH_DMA_MINALIGN); + size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN); for (i = 0; i < FEC_RBD_NUM; i++) { - data = memalign(ARCH_DMA_MINALIGN, size); + data = memalign(FEC_DMA_RX_MINALIGN, size); if (!data) { printf("%s: error allocating rxbuf %d\n", __func__, i); goto err_ring; -- cgit v1.1 From f599288d55e5816c2cf468880e3120ed0b34080e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 25 Aug 2014 13:34:17 -0300 Subject: net: fec_mxc: Poll FEC_TBD_READY after polling TDAR When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets always cleared prior then the READY bit is cleared in the last BD, which causes FEC packets reception to always fail. As explained by Ye Li: "The TDAR bit is cleared when the descriptors are all out from TX ring, but on mx6solox we noticed that the READY bit is still not cleared right after TDAR. These are two distinct signals, and in IC simulation, we found that TDAR always gets cleared prior than the READY bit of last BD becomes cleared. In mx6solox, we use a later version of FEC IP. It looks like that this intrinsic behaviour of TDAR bit has changed in this newer FEC version." Fix this by polling the READY bit of BD after the TDAR polling, which covers the mx6solox case and does not harm the other SoCs. No performance drop has been noticed with this patch applied when testing TFTP transfers on several boards of different i.mx SoCs. Signed-off-by: Fabio Estevam Acked-by: Marek Vasut --- drivers/net/fec_mxc.c | 30 +++++++++++++++++++++++++++--- 1 file changed, 27 insertions(+), 3 deletions(-) (limited to 'drivers/net') diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index d310016..549d648 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -719,13 +719,37 @@ static int fec_send(struct eth_device *dev, void *packet, int length) break; } - if (!timeout) + if (!timeout) { ret = -EINVAL; + goto out; + } - invalidate_dcache_range(addr, addr + size); - if (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) + /* + * The TDAR bit is cleared when the descriptors are all out from TX + * but on mx6solox we noticed that the READY bit is still not cleared + * right after TDAR. + * These are two distinct signals, and in IC simulation, we found that + * TDAR always gets cleared prior than the READY bit of last BD becomes + * cleared. + * In mx6solox, we use a later version of FEC IP. It looks like that + * this intrinsic behaviour of TDAR bit has changed in this newer FEC + * version. + * + * Fix this by polling the READY bit of BD after the TDAR polling, + * which covers the mx6solox case and does not harm the other SoCs. + */ + timeout = FEC_XFER_TIMEOUT; + while (--timeout) { + invalidate_dcache_range(addr, addr + size); + if (!(readw(&fec->tbd_base[fec->tbd_index].status) & + FEC_TBD_READY)) + break; + } + + if (!timeout) ret = -EINVAL; +out: debug("fec_send: status 0x%x index %d ret %i\n", readw(&fec->tbd_base[fec->tbd_index].status), fec->tbd_index, ret); -- cgit v1.1