From f6d1f6e4a58edae4776937647381a43fea5e83a5 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 23 Jul 2013 15:32:36 +0200 Subject: net, phy, cpsw: fix gigabit register access accessing a lan9303 switch with the cpsw driver results in wrong speed detection, as the switch sets the BMSR_ERCAP in BMSR register, and follow read of the MII_STAT1000 register fails, as the switch does not support it. Current code did not check, if a phy_read() fails ... fix this. Signed-off-by: Heiko Schocher Cc: Joe Hershberger Acked-by: Mugunthan V N Signed-off-by: Tom Rini --- drivers/net/phy/phy.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers/net/phy/phy.c') diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 6fe793d..62925bb 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -277,7 +277,7 @@ int genphy_parse_link(struct phy_device *phydev) /* We're using autonegotiation */ if (mii_reg & BMSR_ANEGCAPABLE) { u32 lpa = 0; - u32 gblpa = 0; + int gblpa = 0; u32 estatus = 0; /* Check for gigabit capability */ @@ -286,6 +286,10 @@ int genphy_parse_link(struct phy_device *phydev) * both PHYs in the link */ gblpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_STAT1000); + if (gblpa < 0) { + debug("Could not read MII_STAT1000. Ignoring gigabit capability\n"); + gblpa = 0; + } gblpa &= phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000) << 2; } -- cgit v1.1