From 5344cc1a82fcc2817d4671696b3939b0dfa4323e Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 23 Jan 2015 00:24:19 +0900 Subject: powerpc: ppc4xx: remove PPChameleonEVB, CATcenter boards These boards are still non-generic boards. It is a good thing that we can drop board-specific hack code from drivers/mtd/nand/nand_base.c Signed-off-by: Masahiro Yamada Acked-by: Stefan Roese Cc: Andrea "llandre" Marson --- drivers/mtd/nand/nand_base.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 63bdf65..6db6566 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -1065,11 +1065,6 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) } } #endif -#ifdef PPCHAMELON_NAND_TIMER_HACK - time_start = get_timer(0); - while (get_timer(time_start) < 10) - ; -#endif /* PPCHAMELON_NAND_TIMER_HACK */ led_trigger_event(nand_led_trigger, LED_OFF); status = (int)chip->read_byte(mtd); -- cgit v1.1 From b0265d56fe24a757638a2a0ca76ec1400f43d348 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 5 Jan 2015 20:05:36 -0700 Subject: dm: tegra: nand: Remove use of fdtdec GPIO support These functions are going away, so use the new uclass support instead. Signed-off-by: Simon Glass --- drivers/mtd/nand/tegra_nand.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/tegra_nand.c b/drivers/mtd/nand/tegra_nand.c index 163cf29..b660f3b 100644 --- a/drivers/mtd/nand/tegra_nand.c +++ b/drivers/mtd/nand/tegra_nand.c @@ -79,7 +79,7 @@ enum { struct fdt_nand { struct nand_ctlr *reg; int enabled; /* 1 to enable, 0 to disable */ - struct fdt_gpio_state wp_gpio; /* write-protect GPIO */ + struct gpio_desc wp_gpio; /* write-protect GPIO */ s32 width; /* bit width, normally 8 */ u32 timing[FDT_NAND_TIMING_COUNT]; }; @@ -945,8 +945,8 @@ static int fdt_decode_nand(const void *blob, int node, struct fdt_nand *config) config->reg = (struct nand_ctlr *)fdtdec_get_addr(blob, node, "reg"); config->enabled = fdtdec_get_is_enabled(blob, node); config->width = fdtdec_get_int(blob, node, "nvidia,nand-width", 8); - err = fdtdec_decode_gpio(blob, node, "nvidia,wp-gpios", - &config->wp_gpio); + err = gpio_request_by_name_nodev(blob, node, "nvidia,wp-gpios", 0, + &config->wp_gpio, GPIOD_IS_OUT); if (err) return err; err = fdtdec_get_int_array(blob, node, "nvidia,timing", @@ -1009,8 +1009,7 @@ int tegra_nand_init(struct nand_chip *nand, int devnum) /* Adjust timing for NAND device */ setup_timing(config->timing, info->reg); - fdtdec_setup_gpio(&config->wp_gpio); - gpio_direction_output(config->wp_gpio.gpio, 1); + dm_gpio_set_value(&config->wp_gpio, 1); our_mtd = &nand_info[devnum]; our_mtd->priv = nand; -- cgit v1.1 From 0e48dc5e416f031c8eb05143f2dfab3111ec3b29 Mon Sep 17 00:00:00 2001 From: "Wu, Josh" Date: Fri, 16 Jan 2015 11:54:46 +0800 Subject: mtd: atmel_nand: according to pmecc version to perform 0xff page correction MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As the PMECC hardware has different version. In SAMA5D4 chip, the PMECC ip can generate 0xff pmecc ECC value for all 0xff sector. According to this, add PMECC version check, if it's SAMA5D4 then we always let PMECC hardware to correct it. Signed-off-by: Josh Wu Acked-by: Bo Shen Acked-by: Andreas Bießmann --- drivers/mtd/nand/atmel_nand.c | 9 +++++++++ drivers/mtd/nand/atmel_nand_ecc.h | 20 ++++++++++++++++++++ 2 files changed, 29 insertions(+) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index 620b6e8..b16e3aa 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -44,6 +44,7 @@ struct atmel_nand_host { u8 pmecc_corr_cap; u16 pmecc_sector_size; u32 pmecc_index_table_offset; + u32 pmecc_version; int pmecc_bytes_per_sector; int pmecc_sector_number; @@ -486,6 +487,10 @@ static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf, int i, err_nbr, eccbytes; uint8_t *buf_pos; + /* SAMA5D4 PMECC IP can correct errors for all 0xff page */ + if (host->pmecc_version >= PMECC_VERSION_SAMA5D4) + goto normal_check; + eccbytes = nand_chip->ecc.bytes; for (i = 0; i < eccbytes; i++) if (ecc[i] != 0xff) @@ -961,6 +966,10 @@ static int atmel_pmecc_nand_init_params(struct nand_chip *nand, nand->ecc.write_page = atmel_nand_pmecc_write_page; nand->ecc.strength = cap; + /* Check the PMECC ip version */ + host->pmecc_version = pmecc_readl(host->pmerrloc, version); + dev_dbg(host->dev, "PMECC IP version is: %x\n", host->pmecc_version); + atmel_pmecc_core_init(mtd); return 0; diff --git a/drivers/mtd/nand/atmel_nand_ecc.h b/drivers/mtd/nand/atmel_nand_ecc.h index eac860d..b2d2682 100644 --- a/drivers/mtd/nand/atmel_nand_ecc.h +++ b/drivers/mtd/nand/atmel_nand_ecc.h @@ -123,6 +123,20 @@ struct pmecc_errloc_regs { u32 sigma[25]; /* 0x28-0x88 Error Location Sigma Registers */ u32 el[24]; /* 0x8C-0xE8 Error Location Registers */ u32 reserved1[5]; /* 0xEC-0xFC Reserved */ + + /* + * 0x100-0x1F8: + * Reserved for AT91SAM9X5, AT91SAM9N12. + * HSMC registers for SAMA5D3, SAMA5D4. + */ + u32 reserved2[63]; + + /* + * 0x1FC: + * PMECC version for AT91SAM9X5, AT91SAM9N12. + * HSMC version for SAMA5D3, SAMA5D4. Can refer as PMECC version. + */ + u32 version; }; /* For Error Location Configuration Register */ @@ -137,6 +151,12 @@ struct pmecc_errloc_regs { #define PMERRLOC_ERR_NUM_MASK (0x1f << 8) #define PMERRLOC_CALC_DONE (1 << 0) +/* PMECC IP version */ +#define PMECC_VERSION_SAMA5D4 0x113 +#define PMECC_VERSION_SAMA5D3 0x112 +#define PMECC_VERSION_AT91SAM9N12 0x102 +#define PMECC_VERSION_AT91SAM9X5 0x101 + /* Galois field dimension */ #define PMECC_GF_DIMENSION_13 13 #define PMECC_GF_DIMENSION_14 14 -- cgit v1.1