From aad4659a2fde4b69e8124d6fe8b57bf28d3c747d Mon Sep 17 00:00:00 2001 From: Abbas Raza Date: Mon, 25 Mar 2013 09:13:34 +0000 Subject: mmc: i.MX6: fsl_esdhc: Define maximum bus width supported by a board Maximum bus width supported by some i.MX6 boards is not 8bit like others. In case where both host controller and card support 8bit transfers, they agree to communicate on 8bit interface while some boards support only 4bit interface. Due to this reason the mmc 8bit default mode fails on these boards. To rectify this, define maximum bus width supported by these boards (4bit). If max_bus_width is not defined, it is 0 by default and 8bit width support will be enabled in host capabilities otherwise host capabilities are modified accordingly. It is tested with a MMCplus card. Signed-off-by: Abbas Raza cc: stefano Babic cc: Andy Fleming Acked-by: Dirk Behme Acked-by: Andrew Gabbasov --- drivers/mmc/fsl_esdhc.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers/mmc/fsl_esdhc.c') diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 54b5363..35f879e 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -580,6 +580,13 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC; + if (cfg->max_bus_width > 0) { + if (cfg->max_bus_width < 8) + mmc->host_caps &= ~MMC_MODE_8BIT; + if (cfg->max_bus_width < 4) + mmc->host_caps &= ~MMC_MODE_4BIT; + } + if (caps & ESDHC_HOSTCAPBLT_HSS) mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; -- cgit v1.1 From 54899fc8fe7b33cbe1a7179e39d24e75ababcdc6 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Wed, 3 Apr 2013 12:31:56 +0000 Subject: fsl_esdhc: flush cache after IO completion The cache should invalidate the read buffer for the SD card interface after the transfer complete, not command-complete. Tested-by: Andrew Gabbasov Signed-off-by: Eric Nelson --- drivers/mmc/fsl_esdhc.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'drivers/mmc/fsl_esdhc.c') diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 35f879e..737b812 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -327,9 +327,6 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE))) ; - if (data && (data->flags & MMC_DATA_READ)) - check_and_invalidate_dcache_range(cmd, data); - irqstat = esdhc_read32(®s->irqstat); esdhc_write32(®s->irqstat, irqstat); @@ -403,6 +400,8 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) } while (!(irqstat & IRQSTAT_TC) && (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)); #endif + if (data->flags & MMC_DATA_READ) + check_and_invalidate_dcache_range(cmd, data); } esdhc_write32(®s->irqstat, -1); -- cgit v1.1 From 9b74dc56fba2b9db39420f81c990284f36d5801f Mon Sep 17 00:00:00 2001 From: Andrew Gabbasov Date: Sun, 7 Apr 2013 23:06:08 +0000 Subject: fsl_esdhc: Fix DMA transfer completion waiting loop Rework the waiting for transfer completion loop condition to continue waiting until both Transfer Complete and DMA End interrupts occur. Checking of DLA bit in Present State register looks not needed in addition to interrupts status checking, so it can be removed from the condition. Also, DMA Error condition is added to the list of data errors, checked in the loop. Signed-off-by: Andrew Gabbasov --- drivers/mmc/fsl_esdhc.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/mmc/fsl_esdhc.c') diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 737b812..e945c0a 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -397,8 +397,7 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) if (irqstat & DATA_ERR) return COMM_ERR; - } while (!(irqstat & IRQSTAT_TC) && - (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)); + } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE); #endif if (data->flags & MMC_DATA_READ) check_and_invalidate_dcache_range(cmd, data); -- cgit v1.1