From f1df9364459425abba75488a148ddd98fabf40d7 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 26 Mar 2015 15:36:56 +0100 Subject: arm: mvebu: Add Armada 38x DDR3 training code from Marvell bin_hdr This patch adds the DDR3 setup and training code taken from the Marvell U-Boot repository. This code used to be included as a binary (bin_hdr) into the Armada A38x boot image. Not linked with the main U-Boot. With this code addition and the serdes/PHY setup code, the Armada A38x support in mainline U-Boot is finally self-contained. So the complete image for booting can be built from mainline U-Boot. Without any additional external inclusion. Note: This code has undergone many hours (days!) of coding-style cleanup and refactoring. It still is not checkpatch clean though, I'm afraid. As the factoring of the code has so many levels of indentation that many lines are longer than 80 chars. Signed-off-by: Stefan Roese --- drivers/ddr/marvell/a38x/ddr3_a38x_topology.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 drivers/ddr/marvell/a38x/ddr3_a38x_topology.h (limited to 'drivers/ddr/marvell/a38x/ddr3_a38x_topology.h') diff --git a/drivers/ddr/marvell/a38x/ddr3_a38x_topology.h b/drivers/ddr/marvell/a38x/ddr3_a38x_topology.h new file mode 100644 index 0000000..f27bbff --- /dev/null +++ b/drivers/ddr/marvell/a38x/ddr3_a38x_topology.h @@ -0,0 +1,22 @@ +/* + * Copyright (C) Marvell International Ltd. and its affiliates + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _DDR3_A38X_TOPOLOGY_H +#define _DDR3_A38X_TOPOLOGY_H + +#include "ddr_topology_def.h" + +/* Bus mask variants */ +#define BUS_MASK_32BIT 0xf +#define BUS_MASK_32BIT_ECC 0x1f +#define BUS_MASK_16BIT 0x3 +#define BUS_MASK_16BIT_ECC 0x13 +#define BUS_MASK_16BIT_ECC_PUP3 0xb + +#define DYNAMIC_CS_SIZE_CONFIG +#define DISABLE_L2_FILTERING_DURING_DDR_TRAINING + +#endif /* _DDR3_A38X_TOPOLOGY_H */ -- cgit v1.1