From c65408720670819a9a7174a6b0ed59968cd8ffb7 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 21 Jul 2015 05:29:05 +0200 Subject: ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 3 Zap the useless addr variable. Signed-off-by: Marek Vasut --- drivers/ddr/altera/sequencer.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'drivers/ddr/altera/sequencer.c') diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c index cc5db16..986f088 100644 --- a/drivers/ddr/altera/sequencer.c +++ b/drivers/ddr/altera/sequencer.c @@ -2977,7 +2977,6 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group, int i; u32 sticky_bit_chk; u32 min_index; - u32 addr; int left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS]; int right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS]; int mid; @@ -2996,8 +2995,8 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group, dm_margin = 0; - addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET; - start_dqs = readl(addr + + start_dqs = readl((SDR_PHYGRP_SCCGRP_ADDRESS | + SCC_MGR_IO_OUT1_DELAY_OFFSET) + (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2)); /* Per-bit deskew. */ -- cgit v1.1