From 3c1d218a1d3048fb576677c47eab43049d0b7778 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 4 Apr 2016 11:41:26 -0700 Subject: armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun CC: Prabhakar Kushwaha Reviewed-by: Prabhakar Kushwaha --- drivers/crypto/fsl/jr.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/crypto/fsl') diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index 3fc418a..8bc517d 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -545,12 +545,12 @@ int sec_init(void) /* * Modifying CAAM Read/Write Attributes - * For LS2080A and LS2085A + * For LS2080A * For AXI Write - Cacheable, Write Back, Write allocate * For AXI Read - Cacheable, Read allocate - * Only For LS2080a and LS2085a, to solve CAAM coherency issues + * Only For LS2080a, to solve CAAM coherency issues */ -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#ifdef CONFIG_LS2080A mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0xb << MCFGR_AWCACHE_SHIFT); mcr = (mcr & ~MCFGR_ARCACHE_MASK) | (0x6 << MCFGR_ARCACHE_SHIFT); #else -- cgit v1.1