From ccca7dfd0273af41e5b4bdec7f8731b177a20fde Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Tue, 23 Apr 2013 10:17:40 +0000 Subject: Add fuse API and commands MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This can be useful for fuse-like hardware, OTP SoC options, etc. Signed-off-by: Benoît Thébaudeau --- doc/README.fuse | 67 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 doc/README.fuse (limited to 'doc') diff --git a/doc/README.fuse b/doc/README.fuse new file mode 100644 index 0000000..1bc91c4 --- /dev/null +++ b/doc/README.fuse @@ -0,0 +1,67 @@ +Fuse API functions and commands + +The fuse API allows to control a fusebox and how it is used by the upper +hardware layers. + +A fuse corresponds to a single non-volatile memory bit that can be programmed +(i.e. blown, set to 1) only once. The programming operation is irreversible. A +fuse that has not been programmed reads 0. + +Fuses can be used by SoCs to store various permanent configuration and data, +e.g. boot configuration, security configuration, MAC addresses, etc. + +A fuse word is the smallest group of fuses that can be read at once from the +fusebox control IP registers. This is limited to 32 bits with the current API. + +A fuse bank is the smallest group of fuse words having a common ID, as defined +by each SoC. + +Upon startup, the fusebox control IP reads the fuse values and stores them to a +volatile shadow cache. + +See the README files of the drivers implementing this API in order to know the +SoC- and implementation-specific details. + +Functions / commands: + + int fuse_read(u32 bank, u32 word, u32 *val); + fuse read [] + Read fuse words from the shadow cache. + + int fuse_sense(u32 bank, u32 word, u32 *val); + fuse sense [] + Sense - i.e. read directly from the fusebox, skipping the shadow cache - + fuse words. This operation does not update the shadow cache. + + This is useful to know the true value of fuses if an override has been + performed (see below). + + int fuse_prog(u32 bank, u32 word, u32 val); + fuse prog [-y] [...] + Program fuse words. This operation directly affects the fusebox and is + irreversible. The shadow cache is updated accordingly or not, depending on + each IP. + + Only the bits to be programmed should be set in the input value (i.e. for + fuse bits that have already been programmed and hence should be left + unchanged by a further programming, it is preferable to clear the + corresponding bits in the input value in order not to perform a new + hardware programming operation on these fuse bits). + + int fuse_override(u32 bank, u32 word, u32 val); + fuse override [...] + Override fuse words in the shadow cache. + + The fusebox is unaffected, so following this operation, the shadow cache + may differ from the fusebox values. Read or sense operations can then be + used to get the values from the shadow cache or from the fusebox. + + This is useful to change the behaviors linked to some cached fuse values, + either because this is needed only temporarily, or because some of the + fuses have already been programmed or are locked (if the SoC allows to + override a locked fuse). + +Configuration: + + CONFIG_CMD_FUSE + Define this to enable the fuse commands. -- cgit v1.1 From 0f67e09e9ef354ae2d282091adb3dc531f2aef7d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Tue, 23 Apr 2013 10:17:41 +0000 Subject: Add fsl_iim driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a fsl_iim driver common to i.MX and MPC. Signed-off-by: Benoît Thébaudeau --- doc/README.fsl_iim | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 doc/README.fsl_iim (limited to 'doc') diff --git a/doc/README.fsl_iim b/doc/README.fsl_iim new file mode 100644 index 0000000..e087f5e --- /dev/null +++ b/doc/README.fsl_iim @@ -0,0 +1,48 @@ +Driver implementing the fuse API for Freescale's IC Identification Module (IIM) + +This IP can be found on the following SoCs: + - MPC512x, + - i.MX25, + - i.MX27, + - i.MX31, + - i.MX35, + - i.MX51, + - i.MX53. + +The section numbers in this file refer to the i.MX25 Reference Manual. + +A fuse word contains 8 fuse bit slots, as explained in 30.4.2.2.1. + +A bank contains 256 fuse word slots, as shown by the memory map in 30.3.1. + +Some fuse bit or word slots may not have the corresponding fuses actually +implemented in the fusebox. + +See the README files of the SoCs using this driver in order to know the +conventions used by U-Boot to store some specific data in the fuses, e.g. MAC +addresses. + +Fuse operations: + + Read + Read operations are implemented as read accesses to the shadow registers, + using "Word y of Bank x" from the register summary in 30.3.2. This is + explained in detail in 30.4.5.1. + + Sense + Sense operations are implemented as explained in 30.4.5.2. + + Program + Program operations are implemented as explained in 30.4.5.3. Following + this operation, the shadow registers are reloaded by the hardware (not + immediately, but this does not make any difference for a user reading + these registers). + + Override + Override operations are implemented as write accesses to the shadow + registers, as explained in 30.4.5.4. + +Configuration: + + CONFIG_FSL_IIM + Define this to enable the fsl_iim driver. -- cgit v1.1 From 112fd2ec6c1a96c6ff51490c28eb971795a2dd95 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Tue, 23 Apr 2013 10:17:44 +0000 Subject: Add mxc_ocotp driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add an mxc_ocotp driver for i.MX6. Signed-off-by: Benoît Thébaudeau --- doc/README.mxc_ocotp | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 doc/README.mxc_ocotp (limited to 'doc') diff --git a/doc/README.mxc_ocotp b/doc/README.mxc_ocotp new file mode 100644 index 0000000..9a53311 --- /dev/null +++ b/doc/README.mxc_ocotp @@ -0,0 +1,50 @@ +Driver implementing the fuse API for Freescale's On-Chip OTP Controller (OCOTP) +on MXC + +This IP can be found on the following SoCs: + - i.MX6. + +Note that this IP is different from albeit similar to the IPs of the same name +that can be found on the following SoCs: + - i.MX23, + - i.MX28, + - i.MX50. + +The section numbers in this file refer to the i.MX6 Reference Manual. + +A fuse word contains 32 fuse bit slots, as explained in 46.2.1. + +A bank contains 8 fuse word slots, as explained in 46.2.1 and shown by the +memory map in 46.4. + +Some fuse bit or word slots may not have the corresponding fuses actually +implemented in the fusebox. + +See the README files of the SoCs using this driver in order to know the +conventions used by U-Boot to store some specific data in the fuses, e.g. MAC +addresses. + +Fuse operations: + + Read + Read operations are implemented as read accesses to the shadow registers, + using "Bankx Wordy" from the memory map in 46.4. This is explained in + detail by the first two paragraphs in 46.2.1.2. + + Sense + Sense operations are implemented as the direct fusebox read explained by + the steps in 46.2.1.2. + + Program + Program operations are implemented as explained by the steps in 46.2.1.3. + Following this operation, the shadow registers are not reloaded by the + hardware. + + Override + Override operations are implemented as write accesses to the shadow + registers, as explained by the first paragraph in 46.2.1.3. + +Configuration: + + CONFIG_MXC_OCOTP + Define this to enable the mxc_ocotp driver. -- cgit v1.1 From eec3f0242df7b96a4dc207515050c20ebaddabb2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Tue, 23 Apr 2013 10:17:47 +0000 Subject: imx: Document fuse assignments for MAC addresses MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Benoît Thébaudeau --- doc/README.imx25 | 10 ++++++++++ doc/README.imx27 | 10 ++++++++++ doc/README.imx5 | 6 ++++++ doc/README.imx6 | 10 ++++++++++ 4 files changed, 36 insertions(+) create mode 100644 doc/README.imx25 create mode 100644 doc/README.imx27 create mode 100644 doc/README.imx6 (limited to 'doc') diff --git a/doc/README.imx25 b/doc/README.imx25 new file mode 100644 index 0000000..0ca21b6 --- /dev/null +++ b/doc/README.imx25 @@ -0,0 +1,10 @@ +U-Boot for Freescale i.MX25 + +This file contains information for the port of U-Boot to the Freescale i.MX25 +SoC. + +1. CONVENTIONS FOR FUSE ASSIGNMENTS +----------------------------------- + +1.1 MAC Address: It is stored in the words 26 to 31 of fuse bank 0, using the + natural MAC byte order (i.e. MSB first). diff --git a/doc/README.imx27 b/doc/README.imx27 new file mode 100644 index 0000000..6f92cb4 --- /dev/null +++ b/doc/README.imx27 @@ -0,0 +1,10 @@ +U-Boot for Freescale i.MX27 + +This file contains information for the port of U-Boot to the Freescale i.MX27 +SoC. + +1. CONVENTIONS FOR FUSE ASSIGNMENTS +----------------------------------- + +1.1 MAC Address: It is stored in the words 4 to 9 of fuse bank 0, using the + reversed MAC byte order (i.e. LSB first). diff --git a/doc/README.imx5 b/doc/README.imx5 index e08941e..c5312b6 100644 --- a/doc/README.imx5 +++ b/doc/README.imx5 @@ -20,3 +20,9 @@ i.MX5x SoCs. This option should be enabled for boards having a SYS_ON_OFF_CTL signal connected to GPIO1[23] and triggering the MAIN_PWR_ON signal like in the reference designs. + +2. CONVENTIONS FOR FUSE ASSIGNMENTS +----------------------------------- + +2.1 MAC Address: It is stored in the words 9 to 14 of fuse bank 1, using the + natural MAC byte order (i.e. MSB first). diff --git a/doc/README.imx6 b/doc/README.imx6 new file mode 100644 index 0000000..513a06e --- /dev/null +++ b/doc/README.imx6 @@ -0,0 +1,10 @@ +U-Boot for Freescale i.MX6 + +This file contains information for the port of U-Boot to the Freescale i.MX6 +SoC. + +1. CONVENTIONS FOR FUSE ASSIGNMENTS +----------------------------------- + +1.1 MAC Address: It is stored in fuse bank 4, with the 32 lsbs in word 2 and the + 16 msbs in word 3. -- cgit v1.1 From 6cb83829a013ed2631cba5d5c9bf42eaf2380131 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 25 Apr 2013 10:16:02 +0000 Subject: tools: arm: imx: Implement BOOT_OFFSET command for imximage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implement BOOT_OFFSET command for imximage. This command is parallel to current BOOT_FROM command, but allows more flexibility in configuring arbitrary image header offset. Also add an imximage.cfg with default offset values into arm/arch/imx-common/ so the board-specific imximage.cfg can include this file to avoid magic constants. The syntax of BOOT_OFFSET command is "BOOT_OFFSET ". Signed-off-by: Marek Vasut Cc: Albert ARIBAUD Cc: Benoît Thébaudeau Cc: Fabio Estevam Cc: Scott Wood Cc: Stefano Babic Cc: Tom Rini Acked-by: Stefano Babic Acked-by: Stefan Roese --- doc/README.imximage | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'doc') diff --git a/doc/README.imximage b/doc/README.imximage index 073e3fc..802eb90 100644 --- a/doc/README.imximage +++ b/doc/README.imximage @@ -65,9 +65,27 @@ Configuration command line syntax: This command need appear the fist before other valid commands in configuration file. + BOOT_OFFSET value + + This command is parallel to BOOT_FROM and + is preferred over BOOT_FROM. + + value: Offset of the image header, this + value shall be set to one of the + values found in the file: + arch/arm/include/asm/\ + imx-common/imximage.cfg + Example: + BOOT_OFFSET FLASH_OFFSET_STANDARD + BOOT_FROM nand/spi/sd/onenand/nor/sata + + This command is parallel to BOOT_OFFSET and + is to be deprecated in favor of BOOT_OFFSET. + Example: BOOT_FROM spi + DATA type address value type: word=4, halfword=2, byte=1 -- cgit v1.1