From 9553df86d3a319c3a1a7cde7e4edd6eeb5aa64c7 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 16 Oct 2007 15:26:51 -0500 Subject: Initial mpc8610hpcd cpu/, README and include/ files. Signed-off-by: Ed Swarthout Signed-off-by: Mahesh Jade Signed-off-by: Jason Jin Signed-off-by: Jon Loeliger --- doc/README.mpc8610hpcd | 67 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 doc/README.mpc8610hpcd (limited to 'doc') diff --git a/doc/README.mpc8610hpcd b/doc/README.mpc8610hpcd new file mode 100644 index 0000000..949dcb2 --- /dev/null +++ b/doc/README.mpc8610hpcd @@ -0,0 +1,67 @@ +Freescale MPC8610HPCD board +=========================== + + +Building U-Boot +--------------- + + $ make MPC8610HPCD_config + Configuring for MPC8610HPCD board... + + $ make + + +Flashing U-Boot +--------------- +The flash is 128M starting at 0xF800_0000. + +The alternate image is at 0xFBF0_0000 +The boot image is at 0xFFF0_0000. + + +To Flash U-Boot into the booting bank: + + tftp 1000000 u-boot.bin + protect off all + erase fff00000 +$filesize + cp.b 1000000 fff00000 $filesize + + +To Flash U-boot into the alternate bank + + tftp 1000000 u-boot.bin + erase fbf00000 +$filesize + cp.b 1000000 fbf00000 $filesize + + +pixis_reset command +------------------- +A new command, "pixis_reset", is introduced to reset mpc8610hpcd board +using the FPGA sequencer. When the board restarts, it has the option +of using either the current or alternate flash bank as the boot +image, with or without the watchdog timer enabled, and finally with +or without frequency changes. + +Usage is; + + pixis_reset + pixis_reset altbank + pixis_reset altbank wd + pixis_reset altbank cf + pixis_reset cf + +Examples; + + /* reset to current bank, like "reset" command */ + pixis_reset + + /* reset board but use the to alternate flash bank */ + pixis_reset altbank + + /* reset board, use alternate flash bank with watchdog timer enabled*/ + pixis_reset altbank wd + + /* reset board to alternate bank with frequency changed. + * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio + */ + pixis-reset altbank cf 40 2.5 10 -- cgit v1.1 From 33ecdc2f9d64926e1a6067b28f3a0aefc3b6d23d Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Sun, 25 Nov 2007 02:39:31 +0900 Subject: sh: Add marubun's pcmcia driver Marubun pcmcia is a chip for PCMCIA used with SuperH. Of course, this can be used even by other architectures. When use this driver, came to be able to use CompactFlash and Ethernet. Signed-off-by: Nobuhiro Iwamatsu --- doc/README.marubun-pcmcia | 65 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 doc/README.marubun-pcmcia (limited to 'doc') diff --git a/doc/README.marubun-pcmcia b/doc/README.marubun-pcmcia new file mode 100644 index 0000000..73c9f7f --- /dev/null +++ b/doc/README.marubun-pcmcia @@ -0,0 +1,65 @@ + +U-Boot MARUBUN MR-SHPC-01 PCMCIA controller driver + Last update 21/11/2007 by Nobuhiro Iwamatsu + +======================================================================================== + +0. What's this? + This driver supports MARUBUN MR-SHPC-01. + url: http://www.marubun.co.jp/product/semicon/devices/qgc18e0000002n2z.html + (Sorry Japanese only.) + + This chip is used with SuperH well, and adopted by the + reference board. + ex. * MS7750SE01 + * MS7722SE01 + * other + + This chip doesn't support CardBus. + +1. base source code + The code is based on sources from the Linux kernel + ( arch/sh/kernel/cf-enabler.c ). + +2. How to use + The options you have to specify in the config file are (with the + value for my board as an example): + + * CONFIG_MARUBUN_PCCARD + If you want to use this device driver, should define CONFIG_MARUBUN_PCCARD. + ex. #define CONFIG_MARUBUN_PCCARD + + * CONFIG_PCMCIA_SLOT_A + Most devices have only one slot. You should define CONFIG_PCMCIA_SLOT_A . + ex. #define CONFIG_PCMCIA_SLOT_A 1 + + * CFG_MARUBUN_MRSHPC + This is MR-SHPC-01 PCMCIA controler base address. + You should do the setting matched to your environment. + ex. #define CFG_MARUBUN_MRSHPC 0xb03fffe0 + ( for MS7722SE01 environment ) + + * CFG_MARUBUN_MW1 + This is MR-SHPC-01 memory window base address. + You should do the setting matched to your environment. + ex. #define CFG_MARUBUN_MW1 0xb0400000 + ( for MS7722SE01 environment ) + + * CFG_MARUBUN_MW1 + This is MR-SHPC-01 attribute window base address. + You should do the setting matched to your environment. + ex. #define CFG_MARUBUN_MW2 0xb0500000 + ( for MS7722SE01 environment ) + + * CFG_MARUBUN_MW1 + This is MR-SHPC-01 I/O window base address. + You should do the setting matched to your environment. + ex. #define CFG_MARUBUN_IO 0xb0600000 + ( for MS7722SE01 environment ) + +3. Other + * Check Compact Flash only. + * Maybe, NE2000 compatible NIC is sure to move. + +Copyright (c) 2007 + Nobuhiro Iwamatsu -- cgit v1.1 From 130080874a3d28450098481a262c5f7c855e908d Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Sun, 25 Nov 2007 02:51:17 +0900 Subject: sh: Add document for SuperH. This document is a summary of information concerning SuperH of U-Boot. Signed-off-by: Nobuhiro Iwamatsu --- doc/README.sh | 62 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 doc/README.sh (limited to 'doc') diff --git a/doc/README.sh b/doc/README.sh new file mode 100644 index 0000000..0441a7a --- /dev/null +++ b/doc/README.sh @@ -0,0 +1,62 @@ + +U-Boot for Renesas SuperH + Last update 08/10/2007 by Nobuhiro Iwamatsu + +================================================================================ +0. What's this? + This file contains status information for the port of U-Boot to the + Renesas SuperH series of CPUs. + +================================================================================ +1. Overview + SuperH has an original boot loader. However, source code is dirty, and + maintenance is not done. + To improve sharing and the maintenance of the code, Nobuhiro Iwamatsu + started the porting to u-boot in 2007. + +================================================================================ +2. Supported CPUs + + 2.1. Renesas SH7750/SH7750R + 2.2. Renesas SH7722 + +================================================================================ +3. Supported Boards + + 3.1. Hitachi UL MS7750SE01/MS7750RSE01 + Board specific code is in board/ms7750se + To use this board, type "make ms7750se_config". + + 3.2. Hitachi UL MS7722SE01 + Board specific code is in board/ms7722se + To use this board, type "make ms7722se_config". + + ** README ** + In SuperH, S-record and binary of made u-boot work on the memory. + When u-boot is written in the flash, it is necessary to change the + address by using 'objcopy'. + ex) shX-linux-objcopy -Ibinary -Osrec u-boot.bin u-boot.flash.srec + +================================================================================ +4. Compiler + You can use the following of u-boot to compile. + - SuperH Linux Open site + http://www.superh-linux.org/ + - KPIT GNU tools + http://www.kpitgnutools.com/ + +================================================================================ +5. Future + I plan to support the following CPUs and boards. + 5.1. CPUs + - SH7710/SH7712 (SH3) + - SH7780(SH4) + - SH7785(SH4) + + 5.2. Boards + - Many boards ;-) + +================================================================================ +Copyright (c) 2007 + Nobuhiro Iwamatsu + -- cgit v1.1 From 61fb15c516fef5631e305f1976d7b3a679725856 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Thu, 27 Dec 2007 01:52:50 +0100 Subject: Fix coding style issues; update CHANGELOG. Signed-off-by: Wolfgang Denk --- doc/README.marubun-pcmcia | 34 +++++++++++++++++----------------- doc/README.sh | 19 +++++++++---------- 2 files changed, 26 insertions(+), 27 deletions(-) (limited to 'doc') diff --git a/doc/README.marubun-pcmcia b/doc/README.marubun-pcmcia index 73c9f7f..3ed5cd3 100644 --- a/doc/README.marubun-pcmcia +++ b/doc/README.marubun-pcmcia @@ -1,59 +1,59 @@ U-Boot MARUBUN MR-SHPC-01 PCMCIA controller driver Last update 21/11/2007 by Nobuhiro Iwamatsu - + ======================================================================================== -0. What's this? +0. What's this? This driver supports MARUBUN MR-SHPC-01. url: http://www.marubun.co.jp/product/semicon/devices/qgc18e0000002n2z.html (Sorry Japanese only.) - This chip is used with SuperH well, and adopted by the - reference board. + This chip is used with SuperH well, and adopted by the + reference board. ex. * MS7750SE01 * MS7722SE01 - * other - + * other + This chip doesn't support CardBus. -1. base source code +1. base source code The code is based on sources from the Linux kernel - ( arch/sh/kernel/cf-enabler.c ). + ( arch/sh/kernel/cf-enabler.c ). -2. How to use +2. How to use The options you have to specify in the config file are (with the value for my board as an example): * CONFIG_MARUBUN_PCCARD If you want to use this device driver, should define CONFIG_MARUBUN_PCCARD. ex. #define CONFIG_MARUBUN_PCCARD - + * CONFIG_PCMCIA_SLOT_A Most devices have only one slot. You should define CONFIG_PCMCIA_SLOT_A . ex. #define CONFIG_PCMCIA_SLOT_A 1 * CFG_MARUBUN_MRSHPC This is MR-SHPC-01 PCMCIA controler base address. - You should do the setting matched to your environment. - ex. #define CFG_MARUBUN_MRSHPC 0xb03fffe0 + You should do the setting matched to your environment. + ex. #define CFG_MARUBUN_MRSHPC 0xb03fffe0 ( for MS7722SE01 environment ) * CFG_MARUBUN_MW1 This is MR-SHPC-01 memory window base address. - You should do the setting matched to your environment. + You should do the setting matched to your environment. ex. #define CFG_MARUBUN_MW1 0xb0400000 ( for MS7722SE01 environment ) - + * CFG_MARUBUN_MW1 This is MR-SHPC-01 attribute window base address. - You should do the setting matched to your environment. + You should do the setting matched to your environment. ex. #define CFG_MARUBUN_MW2 0xb0500000 ( for MS7722SE01 environment ) - + * CFG_MARUBUN_MW1 This is MR-SHPC-01 I/O window base address. - You should do the setting matched to your environment. + You should do the setting matched to your environment. ex. #define CFG_MARUBUN_IO 0xb0600000 ( for MS7722SE01 environment ) diff --git a/doc/README.sh b/doc/README.sh index 0441a7a..075d360 100644 --- a/doc/README.sh +++ b/doc/README.sh @@ -1,5 +1,5 @@ -U-Boot for Renesas SuperH +U-Boot for Renesas SuperH Last update 08/10/2007 by Nobuhiro Iwamatsu ================================================================================ @@ -9,10 +9,10 @@ U-Boot for Renesas SuperH ================================================================================ 1. Overview - SuperH has an original boot loader. However, source code is dirty, and + SuperH has an original boot loader. However, source code is dirty, and maintenance is not done. - To improve sharing and the maintenance of the code, Nobuhiro Iwamatsu - started the porting to u-boot in 2007. + To improve sharing and the maintenance of the code, Nobuhiro Iwamatsu + started the porting to u-boot in 2007. ================================================================================ 2. Supported CPUs @@ -33,13 +33,13 @@ U-Boot for Renesas SuperH ** README ** In SuperH, S-record and binary of made u-boot work on the memory. - When u-boot is written in the flash, it is necessary to change the - address by using 'objcopy'. + When u-boot is written in the flash, it is necessary to change the + address by using 'objcopy'. ex) shX-linux-objcopy -Ibinary -Osrec u-boot.bin u-boot.flash.srec - + ================================================================================ 4. Compiler - You can use the following of u-boot to compile. + You can use the following of u-boot to compile. - SuperH Linux Open site http://www.superh-linux.org/ - KPIT GNU tools @@ -52,11 +52,10 @@ U-Boot for Renesas SuperH - SH7710/SH7712 (SH3) - SH7780(SH4) - SH7785(SH4) - + 5.2. Boards - Many boards ;-) ================================================================================ Copyright (c) 2007 Nobuhiro Iwamatsu - -- cgit v1.1 From f8900ce9094c462355eb792eea264ff16ac8fd16 Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Tue, 18 Sep 2007 12:38:53 +0800 Subject: mpc83xx: Add the MPC837xEMDS board readme Add the README.mpc837xemds to /doc Signed-off-by: Dave Liu --- doc/README.mpc837xemds | 104 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) create mode 100644 doc/README.mpc837xemds (limited to 'doc') diff --git a/doc/README.mpc837xemds b/doc/README.mpc837xemds new file mode 100644 index 0000000..3f0cdf7 --- /dev/null +++ b/doc/README.mpc837xemds @@ -0,0 +1,104 @@ +Freescale MPC837xEMDS Board +----------------------------------------- +1. Board Switches and Jumpers +1.0 There are four Dual-In-Line Packages(DIP) Switches on MPC837xEMDS board + For some reason, the HW designers describe the switch settings + in terms of 0 and 1, and then map that to physical switches where + the label "On" refers to logic 0 and "Off" is logic 1. + + Switch bits are numbered 1 through, like, 4 6 8 or 10, but the + bits may contribute to signals that are numbered based at 0, + and some of those signals may be high-bit-number-0 too. Heed + well the names and labels and do not get confused. + + "Off" == 1 + "On" == 0 + + SW4[8] is the bit labled 8 on Switch 4. + SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2. + SW2[1:8]= 0000_0001 refers to bits labeled 1 through 7 is set as "On" + and bits labeled 8 is set as "Off". + +1.1 For the MPC837xEMDS Processor Board + + First, make sure the board default setting is consistent with the + document shipped with your board. Then apply the following setting: + SW3[1-8]= 0011_0000 (BOOTSEQ, ROMLOC setting) + SW4[1-8]= 0000_0110 (core PLL setting) + SW5[1-8]= 1001_1000 (system PLL, boot up from low end of flash) + SW6[1-8]= 0000_1000 (HRCW is read from NOR FLASH) + SW7[1-8]= 0110_1101 (TSEC1/2 interface setting - RGMII) + J3 2-3, TSEC1 LVDD1 with 2.5V + J6 2-3, TSEC2 LVDD2 with 2.5V + J9 2-3, CLKIN from osc on board + J10 removed, CS0 connect to NOR flash; when mounted, CS0 connect to NAND + J11 removed, Hardware Reset Configuration Word load from FLASH(NOR or NAND) + mounted, HRCW load from BCSR. + + on board Oscillator: 66M + +2. Memory Map + +2.1. The memory map should look pretty much like this: + + 0x0000_0000 0x7fff_ffff DDR 2G + 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M + 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M + 0xc000_0000 0xdfff_ffff Empty 512M + 0xe000_0000 0xe00f_ffff Int Mem Reg Space 1M + 0xe010_0000 0xe02f_ffff Empty 2M + 0xe030_0000 0xe03f_ffff PCI IO 1M + 0xe040_0000 0xe05f_ffff Empty 2M + 0xe060_0000 0xe060_8000 NAND Flash 32K + 0xf400_0000 0xf7ff_ffff Empty 64M + 0xf800_0000 0xf800_7fff BCSR on CS1 32K + 0xfe00_0000 0xffff_ffff NOR Flash on CS0 32M + +3. Definitions + +3.1 Explanation of NEW definitions in: + + include/configs/MPC837XEMDS.h + + CONFIG_MPC83XX MPC83xx family for both MPC837x and MPC8360 + CONFIG_MPC837X MPC837x specific + CONFIG_MPC837XEMDS MPC837XEMDS board specific + +4. Compilation + + Assuming you're using BASH shell: + + export CROSS_COMPILE=your-cross-compile-prefix + cd u-boot + make distclean + make MPC837XEMDS_config + make + +5. Downloading and Flashing Images + +5.0 Download over serial line using Kermit: + + loadb + [Drop to kermit: + ^\c + send + c + ] + + + Or via tftp: + + tftp 40000 u-boot.bin + +5.1 Reflash U-boot Image using U-boot + + tftp 40000 u-boot.bin + protect off fe000000 fe1fffff + erase fe000000 fe1fffff + + cp.b 40000 fe000000 xxxx + +You have to supply the correct byte count with 'xxxx' from the TFTP result log. + +6. Notes + 1) The console baudrate for MPC837XEMDS is 115200bps. -- cgit v1.1