From ad5bb451ade552c44bef9119d907929ebc2c126f Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 6 Mar 2007 18:08:43 +0100 Subject: Restructure POST directory to support of other CPUs, boards, etc. --- cpu/ppc4xx/44x_spd_ddr2.c | 8 +++--- cpu/ppc4xx/start.S | 62 +++++++++++++++++++++++------------------------ 2 files changed, 35 insertions(+), 35 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index 35b2315..3ab050f 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -168,8 +168,8 @@ static void program_codt(unsigned long *dimm_populated, static void program_mode(unsigned long *dimm_populated, unsigned char *iic0_dimm_addr, unsigned long num_dimm_banks, - ddr_cas_id_t *selected_cas, - int *write_recovery); + ddr_cas_id_t *selected_cas, + int *write_recovery); static void program_tr(unsigned long *dimm_populated, unsigned char *iic0_dimm_addr, unsigned long num_dimm_banks); @@ -185,7 +185,7 @@ static void program_copt1(unsigned long *dimm_populated, static void program_initplr(unsigned long *dimm_populated, unsigned char *iic0_dimm_addr, unsigned long num_dimm_banks, - ddr_cas_id_t selected_cas, + ddr_cas_id_t selected_cas, int write_recovery); static unsigned long is_ecc_enabled(void); static void program_ecc(unsigned long *dimm_populated, @@ -1149,7 +1149,7 @@ static void program_codt(unsigned long *dimm_populated, static void program_initplr(unsigned long *dimm_populated, unsigned char *iic0_dimm_addr, unsigned long num_dimm_banks, - ddr_cas_id_t selected_cas, + ddr_cas_id_t selected_cas, int write_recovery) { u32 cas = 0; diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 24b30df..6b2c170 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -1916,43 +1916,43 @@ pll_wait: /*----------------------------------------------------------------------------+ | dcbz_area. +----------------------------------------------------------------------------*/ - function_prolog(dcbz_area) - rlwinm. r5,r4,0,27,31 - rlwinm r5,r4,27,5,31 - beq ..d_ra2 - addi r5,r5,0x0001 + function_prolog(dcbz_area) + rlwinm. r5,r4,0,27,31 + rlwinm r5,r4,27,5,31 + beq ..d_ra2 + addi r5,r5,0x0001 ..d_ra2:mtctr r5 ..d_ag2:dcbz r0,r3 - addi r3,r3,32 - bdnz ..d_ag2 - sync - blr - function_epilog(dcbz_area) + addi r3,r3,32 + bdnz ..d_ag2 + sync + blr + function_epilog(dcbz_area) /*----------------------------------------------------------------------------+ | dflush. Assume 32K at vector address is cachable. +----------------------------------------------------------------------------*/ - function_prolog(dflush) - mfmsr r9 - rlwinm r8,r9,0,15,13 - rlwinm r8,r8,0,17,15 - mtmsr r8 - addi r3,r0,0x0000 - mtspr dvlim,r3 - mfspr r3,ivpr - addi r4,r0,1024 - mtctr r4 + function_prolog(dflush) + mfmsr r9 + rlwinm r8,r9,0,15,13 + rlwinm r8,r8,0,17,15 + mtmsr r8 + addi r3,r0,0x0000 + mtspr dvlim,r3 + mfspr r3,ivpr + addi r4,r0,1024 + mtctr r4 ..dflush_loop: - lwz r6,0x0(r3) - addi r3,r3,32 - bdnz ..dflush_loop - addi r3,r3,-32 - mtctr r4 + lwz r6,0x0(r3) + addi r3,r3,32 + bdnz ..dflush_loop + addi r3,r3,-32 + mtctr r4 ..ag: dcbf r0,r3 - addi r3,r3,-32 - bdnz ..ag - sync - mtmsr r9 - blr - function_epilog(dflush) + addi r3,r3,-32 + bdnz ..ag + sync + mtmsr r9 + blr + function_epilog(dflush) #endif /* CONFIG_440 */ -- cgit v1.1 From e2ebe696818939e2b974628be9c921ea3fe9de13 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 7 Mar 2007 16:39:36 +0100 Subject: [PATCH] Fix AMCC 44x SPD SDRAM init code to support 2 DIMM's This patch fixes a problem that occurs when 2 DIMM's are used. This problem was first spotted and fixed by Gerald Jackson but this patch fixes the problem in a little more clever way. This patch also adds the nice functionality to dynamically create the TLB entries for the SDRAM (tlb.c). So we should never run into such problems with wrong (too short) TLB initialization again on these platforms. As this feature is new to the "old" 44x SPD DDR driver, it has to be enabled via the CONFIG_PROG_SDRAM_TLB define. Signed-off-by: Stefan Roese --- cpu/ppc4xx/44x_spd_ddr.c | 31 +++++++++++++++++++++++++++---- 1 file changed, 27 insertions(+), 4 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c index 32d44db..10b4c18 100644 --- a/cpu/ppc4xx/44x_spd_ddr.c +++ b/cpu/ppc4xx/44x_spd_ddr.c @@ -46,6 +46,7 @@ #include #include #include +#include #if defined(CONFIG_SPD_EEPROM) && \ (defined(CONFIG_440GP) || defined(CONFIG_440GX) || \ @@ -229,6 +230,22 @@ #define TRUE 1 #define FALSE 0 +/* + * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory + * region. Right now the cache should still be disabled in U-Boot because of the + * EMAC driver, that need it's buffer descriptor to be located in non cached + * memory. + * + * If at some time this restriction doesn't apply anymore, just define + * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup + * everything correctly. + */ +#ifdef CFG_ENABLE_SDRAM_CACHE +#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */ +#else +#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ +#endif + const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = { {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF}, @@ -259,6 +276,7 @@ typedef struct bank_param BANKPARMS; #ifdef CFG_SIMULATE_SPD_EEPROM extern unsigned char cfg_simulate_spd_eeprom[128]; #endif +void program_tlb(u32 start, u32 size, u32 tlb_word2_i_value); unsigned char spd_read(uchar chip, uint addr); @@ -377,6 +395,11 @@ long int spd_sdram(void) { total_size = program_bxcr(dimm_populated, iic0_dimm_addr, num_dimm_banks); +#ifdef CONFIG_PROG_SDRAM_TLB /* this define should eventually be removed */ + /* and program tlb entries for this size (dynamic) */ + program_tlb(0, total_size, MY_TLB_WORD2_I_ENABLE); +#endif + /* * program SDRAM Clock Timing Register (SDRAM0_CLKTR) */ @@ -1330,11 +1353,11 @@ unsigned long program_bxcr(unsigned long* dimm_populated, */ cr |= SDRAM_BXCR_SDBE; - for (i = 0; i < num_banks; i++) { - bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes = + for (i = 0; i < num_banks; i++) { + bank_parms[ctrl_bank_num[dimm_num]+i+dimm_num].bank_size_bytes = (4 * 1024 * 1024) * bank_size_id; - bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr; - } + bank_parms[ctrl_bank_num[dimm_num]+i+dimm_num].cr = cr; + } } } -- cgit v1.1