From b3fb663b20d995ca41327db877ddb168279b3f62 Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Tue, 19 Aug 2008 16:21:00 -0400 Subject: ARM DaVinci: Fix compilation error with new MTD code. ARM DaVinci: Fix compilation error with new MTD code. Signed-off-by: Hugo Villeneuve --- cpu/arm926ejs/davinci/nand.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'cpu') diff --git a/cpu/arm926ejs/davinci/nand.c b/cpu/arm926ejs/davinci/nand.c index 2aa01d6..080b32c 100644 --- a/cpu/arm926ejs/davinci/nand.c +++ b/cpu/arm926ejs/davinci/nand.c @@ -90,7 +90,6 @@ static void nand_davinci_select_chip(struct mtd_info *mtd, int chip) #ifdef CFG_NAND_HW_ECC #ifdef CFG_NAND_LARGEPAGE static struct nand_ecclayout davinci_nand_ecclayout = { - .useecc = MTD_NANDECC_AUTOPLACE, .eccbytes = 12, .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58}, .oobfree = { @@ -103,7 +102,6 @@ static struct nand_ecclayout davinci_nand_ecclayout = { }; #elif defined(CFG_NAND_SMALLPAGE) static struct nand_ecclayout davinci_nand_ecclayout = { - .useecc = MTD_NANDECC_AUTOPLACE, .eccbytes = 3, .eccpos = {0, 1, 2}, .oobfree = { -- cgit v1.1 From e39411674669cc880e1ec4a8ca4794fb15c33a45 Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Tue, 19 Aug 2008 16:21:03 -0400 Subject: ARM DaVinci: Removed redundant NAND initialization code. ARM DaVinci: Removed redundant NAND initialization code. Signed-off-by: Hugo Villeneuve --- cpu/arm926ejs/davinci/nand.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/arm926ejs/davinci/nand.c b/cpu/arm926ejs/davinci/nand.c index 080b32c..5a1da63 100644 --- a/cpu/arm926ejs/davinci/nand.c +++ b/cpu/arm926ejs/davinci/nand.c @@ -369,12 +369,11 @@ int board_nand_init(struct nand_chip *nand) nand->options = NAND_USE_FLASH_BBT; #endif #ifdef CFG_NAND_HW_ECC -#ifdef CFG_NAND_LARGEPAGE nand->ecc.mode = NAND_ECC_HW; +#ifdef CFG_NAND_LARGEPAGE nand->ecc.size = 2048; nand->ecc.bytes = 12; #elif defined(CFG_NAND_SMALLPAGE) - nand->ecc.mode = NAND_ECC_HW; nand->ecc.size = 512; nand->ecc.bytes = 3; #else -- cgit v1.1 From e8f1207bbf2df6fb693ee1aa3329b2014c92e5e6 Mon Sep 17 00:00:00 2001 From: Gururaja Hebbar K R Date: Mon, 25 Aug 2008 11:11:34 +0200 Subject: Correct ARM Versatile Timer Initialization - According to ARM Dual-Timer Module (SP804) TRM (ARM DDI0271), -- Timer Value Register @ TIMER Base + 4 is Read-only. -- Prescale Value (Bits 3-2 of TIMER Control register) can only be one of 00,01,10. 11 is undefined. -- CFG_HZ for Versatile board is set to #define CFG_HZ (1000000 / 256) So Prescale bits is set to indicate - 8 Stages of Prescale, Clock divided by 256 - The Timer Control Register has one Undefined/Shouldn't Use Bit So we should do read/modify/write Operation Signed-off-by: Gururaja Hebbar --- cpu/arm926ejs/versatile/timer.c | 39 +++++++++++++++++++++++++++++++++++---- 1 file changed, 35 insertions(+), 4 deletions(-) mode change 100644 => 100755 cpu/arm926ejs/versatile/timer.c (limited to 'cpu') diff --git a/cpu/arm926ejs/versatile/timer.c b/cpu/arm926ejs/versatile/timer.c old mode 100644 new mode 100755 index 32872d2..f01f318 --- a/cpu/arm926ejs/versatile/timer.c +++ b/cpu/arm926ejs/versatile/timer.c @@ -46,12 +46,43 @@ static ulong timestamp; static ulong lastdec; -/* nothing really to do with interrupts, just starts up a counter. */ +#define TIMER_ENABLE (1 << 7) +#define TIMER_MODE_MSK (1 << 6) +#define TIMER_MODE_FR (0 << 6) +#define TIMER_MODE_PD (1 << 6) + +#define TIMER_INT_EN (1 << 5) +#define TIMER_PRS_MSK (3 << 2) +#define TIMER_PRS_8S (1 << 3) +#define TIMER_SIZE_MSK (1 << 2) +#define TIMER_ONE_SHT (1 << 0) + int timer_init (void) { - *(volatile ulong *)(CFG_TIMERBASE + 0) = CFG_TIMER_RELOAD; /* TimerLoad */ - *(volatile ulong *)(CFG_TIMERBASE + 4) = CFG_TIMER_RELOAD; /* TimerValue */ - *(volatile ulong *)(CFG_TIMERBASE + 8) = 0x8C; + ulong tmr_ctrl_val; + + /* 1st disable the Timer */ + tmr_ctrl_val = *(volatile ulong *)(CFG_TIMERBASE + 8); + tmr_ctrl_val &= ~TIMER_ENABLE; + *(volatile ulong *)(CFG_TIMERBASE + 8) = tmr_ctrl_val; + + /* + * The Timer Control Register has one Undefined/Shouldn't Use Bit + * So we should do read/modify/write Operation + */ + + /* + * Timer Mode : Free Running + * Interrupt : Disabled + * Prescale : 8 Stage, Clk/256 + * Tmr Siz : 16 Bit Counter + * Tmr in Wrapping Mode + */ + tmr_ctrl_val = *(volatile ulong *)(CFG_TIMERBASE + 8); + tmr_ctrl_val &= ~(TIMER_MODE_MSK | TIMER_INT_EN | TIMER_PRS_MSK | TIMER_SIZE_MSK | TIMER_ONE_SHT ); + tmr_ctrl_val |= (TIMER_ENABLE | TIMER_PRS_8S); + + *(volatile ulong *)(CFG_TIMERBASE + 8) = tmr_ctrl_val; /* init the timestamp and lastdec value */ reset_timer_masked(); -- cgit v1.1 From 079edb913dbae147b50a488cf02e03f473fc5f28 Mon Sep 17 00:00:00 2001 From: Jens Gehrlein Date: Fri, 4 Jul 2008 16:50:05 +0200 Subject: MX31: fix bit masks in function mx31_decode_pll() Bits MPCTL[MFN] and MPCTL[MFD] were not fully covered. Signed-off-by: Jens Gehrlein --- cpu/arm1136/mx31/generic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/arm1136/mx31/generic.c b/cpu/arm1136/mx31/generic.c index dc031c9..1415d6c 100644 --- a/cpu/arm1136/mx31/generic.c +++ b/cpu/arm1136/mx31/generic.c @@ -27,8 +27,8 @@ static u32 mx31_decode_pll(u32 reg, u32 infreq) { u32 mfi = (reg >> 10) & 0xf; - u32 mfn = reg & 0x3f; - u32 mfd = (reg >> 16) & 0x3f; + u32 mfn = reg & 0x3ff; + u32 mfd = (reg >> 16) & 0x3ff; u32 pd = (reg >> 26) & 0xf; mfi = mfi <= 5 ? 5 : mfi; -- cgit v1.1