From 023889838282b6237b401664f22dd22dfba2c066 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 5 Jan 2007 10:38:05 +0100 Subject: [PATCH] Add DDR2 optimization code for Sequoia (440EPx) board This code will optimize the DDR2 controller setup on a board specific basis. Note: This code doesn't work right now on the NAND booting image for the Sequoia board, since it doesn't fit into the 4kBytes for the SPL image. Signed-off-by: Stefan Roese --- cpu/ppc4xx/cpu_init.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index 4b746b0..db0559b 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -31,9 +31,6 @@ DECLARE_GLOBAL_DATA_PTR; #endif - -#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data) - #ifdef CFG_INIT_DCACHE_CS # if (CFG_INIT_DCACHE_CS == 0) # define PBxAP pb0ap -- cgit v1.1