From aaf224ab4ec400abefa17982cbd2ae995adc9978 Mon Sep 17 00:00:00 2001
From: wdenk <wdenk>
Date: Sun, 14 Mar 2004 15:20:55 +0000
Subject: * Patch by Stephan Linz, 09 Mar 2004   - Add support for the SSV
 ADNP/ESC1 (Nios Softcore)

* Patch by George G. Davis, 9 Mar 2004:
  fix recent build failure for SA1100 target

* Patch by Travis Sawyer, 09 Mar 2004:
  Support native interrupt mode for the IBM440GX.
  Previously it was running in 440GP compatibility mode.
---
 cpu/ppc4xx/interrupts.c | 29 +++++++++++++++++++++++------
 cpu/sa1100/interrupts.c | 21 +++++++++++++++++++++
 2 files changed, 44 insertions(+), 6 deletions(-)

(limited to 'cpu')

diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c
index 71052b4..7fa2f77 100644
--- a/cpu/ppc4xx/interrupts.c
+++ b/cpu/ppc4xx/interrupts.c
@@ -170,9 +170,21 @@ int interrupt_init_cpu (unsigned *decrementer_count)
 #endif
 
 #if defined(CONFIG_440_GX)
+	/* Take the GX out of compatibility mode
+	 * Travis Sawyer, 9 Mar 2004
+	 * NOTE: 440gx user manual inconsistency here
+	 *       Compatibility mode and Ethernet Clock select are not
+	 *       correct in the manual
+	 */
+	mfsdr(sdr_mfr, val);
+	val &= ~0x10000000;
+	mtsdr(sdr_mfr,val);
+
 	/* Enable UIC interrupts via UIC Base Enable Register */
-	mtdcr(uicb0er, UICB0_ALL);
-	mtdcr(uicb0cr, UICB0_ALL);
+	mtdcr(uicb0sr, UICB0_ALL);
+	mtdcr(uicb0er, 0x54000000);
+	/* None are critical */
+	mtdcr(uicb0cr, 0);
 #endif
 
 	return (0);
@@ -194,11 +206,16 @@ void external_interrupt(struct pt_regs *regs)
 	/* 440 GX uses base uic register */
 	uic_msr = mfdcr(uicb0msr);
 
-	uic0_interrupt(0);
-	uic1_interrupt(0);
-	uic2_interrupt(0);
+	if ( (UICB0_UIC0CI & uic_msr) || (UICB0_UIC0NCI & uic_msr) )
+		uic0_interrupt(0);
 
-	mtdcr(uicb0sr, UICB0_ALL);
+	if ( (UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr) )
+		uic1_interrupt(0);
+
+	if ( (UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr) )
+		uic2_interrupt(0);
+
+	mtdcr(uicb0sr, uic_msr);
 
 	return;
 
diff --git a/cpu/sa1100/interrupts.c b/cpu/sa1100/interrupts.c
index 75f939c..00b6d2a 100644
--- a/cpu/sa1100/interrupts.c
+++ b/cpu/sa1100/interrupts.c
@@ -218,3 +218,24 @@ void udelay_masked (unsigned long usec)
 	while (tmo >= get_timer_masked ())
 		/*NOP*/;
 }
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+	ulong tbclk;
+
+	tbclk = CFG_HZ;
+	return tbclk;
+}
-- 
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