From 21fae8b2b4e4e6e648796e07e20ab13e9cb18923 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Wed, 27 Feb 2008 14:29:58 -0600 Subject: Invalidate INIT_RAM TLB mappings Commit 0db37dc... (and some others) changed the INIT_RAM TLB mappings to be unguarded. This collided with an existing "bug" where the mappings for the INIT_RAM were being kept around. This meant that speculative loads to those addresses were succeeding in the TLB, and going out to the bus, where they were causing an exception (there's nothing at that address). The Flash code was coincidentally causing such a speculative load. Rather than go back to mapping the INIT RAM as guarded, we fix it so that the entries for the INIT_RAM are invalidated. Thus the speculative loads will fail in the TLB, and have no effect. Signed-off-by: Andy Fleming --- cpu/mpc85xx/start.S | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'cpu') diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index eb24dbc..636ef5d 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -1007,6 +1007,17 @@ unlock_ram_in_cache: addi r3,r3,CFG_CACHELINE_SIZE bdnz 1b sync /* Wait for all icbi to complete on bus */ + + /* Invalidate the TLB entries for the cache */ + lis r3,CFG_INIT_RAM_ADDR@h + ori r3,r3,CFG_INIT_RAM_ADDR@l + tlbivax 0,r3 + addi r3,r3,0x1000 + tlbivax 0,r3 + addi r3,r3,0x1000 + tlbivax 0,r3 + addi r3,r3,0x1000 + tlbivax 0,r3 isync blr #endif -- cgit v1.1 From 534ea6b6f86f8b75ef2ac061ef110a98f103d7d6 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Wed, 27 Feb 2008 15:50:50 -0600 Subject: Fix source for ECM error IVPR The source vector for the ECM was being set to 2, but that's what the source vector for DDR was being set to. Change it to 1. Signed-off-by: Andy Fleming --- cpu/mpc85xx/interrupts.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/interrupts.c b/cpu/mpc85xx/interrupts.c index 18e5377..4fe1fac 100644 --- a/cpu/mpc85xx/interrupts.c +++ b/cpu/mpc85xx/interrupts.c @@ -91,7 +91,7 @@ int interrupt_init (void) set_msr (get_msr () | MSR_EE); #ifdef CONFIG_INTERRUPTS - pic->iivpr1 = 0x810002; /* 50220 enable ecm interrupts */ + pic->iivpr1 = 0x810001; /* 50220 enable ecm interrupts */ debug("iivpr1@%x = %x\n",&pic->iivpr1, pic->iivpr1); pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */ -- cgit v1.1 From 2b22fa4baee51e6b467c44ea1be0d1ecd86e8775 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 27 Feb 2008 16:30:47 -0600 Subject: 85xx: Don't icbi when unlocking the cache There is no reason to icbi when invalidating the temporary stack in the d-cache. Its impossible on e500 to have the i-cache contain any addresses in the temp stack and it can be problematic in generating transactions on the bus to non-valid addresses. Signed-off-by: Kumar Gala --- cpu/mpc85xx/start.S | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 636ef5d..15b804d 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -992,7 +992,6 @@ trap_reloc: blr -#ifdef CFG_INIT_RAM_LOCK .globl unlock_ram_in_cache unlock_ram_in_cache: /* invalidate the INIT_RAM section */ @@ -1002,11 +1001,10 @@ unlock_ram_in_cache: andi. r4,r4,0x1ff slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) mtctr r4 -1: icbi r0,r3 - dcbi r0,r3 +1: dcbi r0,r3 addi r3,r3,CFG_CACHELINE_SIZE bdnz 1b - sync /* Wait for all icbi to complete on bus */ + sync /* Invalidate the TLB entries for the cache */ lis r3,CFG_INIT_RAM_ADDR@h @@ -1020,4 +1018,3 @@ unlock_ram_in_cache: tlbivax 0,r3 isync blr -#endif -- cgit v1.1 From 4fae35a53b3e958254d6574a1cc7e10811fc6726 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Mon, 25 Feb 2008 20:54:04 +0100 Subject: ppc4xx: Fix problem in 4xx_enet.c driver U-Boot crashes in the net loop if CONFIG_4xx_DCACHE is enabled. To reproduce the problem ensure that 'ethrotate' environment variable isn't set to "no" and then run "tftp 200000 not_existent_file". This patch tries to fix the issue. Signed-off-by: Anatolij Gustschin --- cpu/ppc4xx/4xx_enet.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 44659ff..5ef1005 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -487,6 +487,9 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #endif u32 bd_cached; u32 bd_uncached = 0; +#ifdef CONFIG_4xx_DCACHE + static u32 last_used_ea = 0; +#endif EMAC_4XX_HW_PST hw_p = dev->priv; @@ -850,7 +853,12 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #ifdef CONFIG_4xx_DCACHE flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE); - bd_uncached = bis->bi_memsize; + if (!last_used_ea) + bd_uncached = bis->bi_memsize; + else + bd_uncached = last_used_ea + MAL_ALLOC_SIZE; + + last_used_ea = bd_uncached; program_tlb(bd_cached, bd_uncached, MAL_ALLOC_SIZE, TLB_WORD2_I_ENABLE); #else -- cgit v1.1 From 5f91db7f582ca17b1f19f10189c025696f333d2e Mon Sep 17 00:00:00 2001 From: John Rigby Date: Tue, 26 Feb 2008 09:38:14 -0700 Subject: MPC5121e ADS PCI support take 3 Adds PCI support for MPC5121 Tested with drivers/net/rtl8139.c Support is conditional since PCI on old silicon does not work. ads5121_PCI_config turns on PCI In this version, condition compilation of PCI code has been moved from ifdef in board/ads5121/pci.c to board/ads5121/Makefile as suggested by Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: John Rigby --- cpu/mpc512x/speed.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc512x/speed.c b/cpu/mpc512x/speed.c index 99e3495..cfaffb5 100644 --- a/cpu/mpc512x/speed.c +++ b/cpu/mpc512x/speed.c @@ -67,12 +67,14 @@ int get_clocks (void) u8 cpmf; u8 sys_div; u8 ips_div; + u8 pci_div; u32 ref_clk = CFG_MPC512X_CLKIN; u32 spll; u32 sys_clk; u32 core_clk; u32 csb_clk; u32 ips_clk; + u32 pci_clk; if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) return -1; @@ -95,8 +97,16 @@ int get_clocks (void) /* in case we cannot get a sane IPS divisor, fail gracefully */ ips_clk = 0; } + pci_div = (im->clk.scfr[0] & SCFR1_PCI_DIV_MASK) >> SCFR1_PCI_DIV_SHIFT; + if (pci_div != 0) { + pci_clk = csb_clk / pci_div; + } else { + /* in case we cannot get a sane IPS divisor, fail gracefully */ + pci_clk = 333333; + } gd->ips_clk = ips_clk; + gd->pci_clk = pci_clk; gd->csb_clk = csb_clk; gd->cpu_clk = core_clk; gd->bus_clk = csb_clk; @@ -115,11 +125,12 @@ ulong get_bus_freq (ulong dummy) int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { - printf ("Clock configuration:\n"); - printf (" CPU: %4d MHz\n", gd->cpu_clk / 1000000); - printf (" Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000); - printf (" IPS Bus: %4d MHz\n", gd->ips_clk / 1000000); - printf (" DDR: %4d MHz\n", 2 * gd->csb_clk / 1000000); + printf("Clock configuration:\n"); + printf(" CPU: %4d MHz\n", gd->cpu_clk / 1000000); + printf(" Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000); + printf(" IPS Bus: %4d MHz\n", gd->ips_clk / 1000000); + printf(" PCI: %4d MHz\n", gd->pci_clk / 1000000); + printf(" DDR: %4d MHz\n", 2 * gd->csb_clk / 1000000); return 0; } -- cgit v1.1 From 76957cb3d621bf664311908e5962e151c633c285 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sat, 1 Mar 2008 12:11:40 +0100 Subject: ppc4xx: EMAC: Fix 405EZ fifo size setup in EMAC_MR1 The 405EZ only supports 512 bytes of rx-/tx-fifo EMAC sizes. But currently 4k/2k is configured. This patch fixes this issue. Thanks to Thomas Kindler for pointing this out. Signed-off-by: Stefan Roese --- cpu/ppc4xx/4xx_enet.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 5ef1005..599f5ce 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -975,9 +975,10 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) /* set transmit enable & receive enable */ out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE); - /* set receive fifo to 4k and tx fifo to 2k */ mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr); - mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K; + + /* set rx-/tx-fifo size */ + mode_reg = (mode_reg & ~EMAC_MR1_FIFO_MASK) | EMAC_MR1_FIFO_SIZE; /* set speed */ if (speed == _1000BASET) { -- cgit v1.1 From 74eb0222594fd23aafdf168e60e872814eea8b62 Mon Sep 17 00:00:00 2001 From: Mike Nuss Date: Mon, 3 Mar 2008 15:27:05 -0500 Subject: PPC4xx (Sequoia): Fix Ethernet "remote fault" problems Every now and then a Sequoia board (or equivalent hardware) had problems connecting to a Gigabit capable network interface. There were differences in the PHY setup between Linux and U-Boot. This patch fixes the problem. Apparently "remote fault" is being set, which signals to some devices (on the other end of the cable) that a fault has occurred, while other devices ignore it. I believe the RF bit was causing the issue, but I removed T4 also, to match up with Linux. Signed-off-by: Mike Nuss --- cpu/ppc4xx/miiphy.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c index 4216f0b..3978773 100644 --- a/cpu/ppc4xx/miiphy.c +++ b/cpu/ppc4xx/miiphy.c @@ -143,9 +143,8 @@ int phy_setup_aneg (char *devname, unsigned char addr) u16 adv; miiphy_read (devname, addr, PHY_ANAR, &adv); - adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 | - PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD | - PHY_ANLPAR_10); + adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | + PHY_ANLPAR_10FD | PHY_ANLPAR_10); miiphy_write (devname, addr, PHY_ANAR, adv); miiphy_read (devname, addr, PHY_1000BTCR, &adv); -- cgit v1.1